JPH0634298B2 - Address circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital processing circuit in a PCM reproducing device,
Particularly, it relates to the address circuit.

[Background of the Invention]

A means for generating an address of reproduced digital data in a PCM reproducing apparatus is described in JP-A-58-125208.

However, such an address generating means is required to generate a correct address faster and to recover faster when an error is detected.

[Object of the Invention]

An object of the present invention is to provide an address circuit that correctly generates an address when a signal is lost due to dropout during reproduction.

[Outline of Invention]

According to the present invention, the continuity of the address code and the detection condition of the parity check circuit are changed by the output of the detection circuit that finds the beginning of the data, and a means for generating an address from the address code and a counter that receives the synchronization signal are used. It has other address generation means, and outputs this code when it correctly detects the address code,
Moreover, this counter is loaded, and in other cases, an address is generated by the output of this counter.

Example of Invention

 An embodiment of the present invention will be shown below in FIG.

In FIG. 1, 1 is a synchronization detection protection circuit, 2 is a timing circuit for operating each circuit based on a synchronization signal, 3
Is an S / P conversion circuit for converting input serial data into parallel data, 4 is a latch circuit for temporarily storing an address code in the data, 5 is an address code, and an identification code described later. A parity check circuit for detecting an error (hereinafter abbreviated as ID code). 6 is a counter circuit which counts up by +1 for each block to generate an address, 7 is a control circuit for controlling whether or not to protect the detected address code, and 8 is detected by a control signal of the control circuit 7. It is a multiplexer circuit for switching the output address code 21 and the protected output 22 and outputting them. 12 is a generated address output, 13 is a multiplexer switching output, and 14 is a counter load input.

Here, the control circuit 7 is composed of the circuit shown in FIG. In FIG. 2, 40 is a latch circuit 4.
Latch circuit for latching the address code 21 latched by, 41 is an adder circuit for adding +1 to the latched value, and 42 is a circuit for detecting a match between the added value and the next latched address code. A comparison circuit, 43 is a flag circuit for temporarily storing the parity check result and the sync code detection state, and 44 is a count of the number of undetectable sync signals. Deemed data area detection circuit, 45 is comparison circuit 42
And the flag circuit 43, further determines whether the address code is correct based on the output of the data area detection circuit 44,
A discriminating circuit for generating a control signal for address protection, and a first Sync detecting circuit 46 for detecting the first detected sync signal.

FIG. 3 shows a reproduced signal. The reproduction signal is an intermittent signal as shown in the figure. This signal is further divided into a plurality of block signals, and each block signal includes a Sync signal 60, an ID signal 61 for identification, a code unique to each block, for example, an address signal (step up from the beginning by one). It is composed of a parity code 63 and a data code 64 for detecting an error between these two codes at the time of reproduction by taking MOD2 of an AD signal) 62, for example, an ID code 61 and an AD code 62.

The operation of the present invention will be described below. When reproducing the intermittent signal shown in FIG. 3, it is necessary to correctly detect the beginning of the data and fetch the data 64 in order. For this reason, in this embodiment, correct address generation is performed based on the synchronization detection state using the continuity of the address code and the parity code.

First, a flag signal 10 indicating whether or not a signal is input and a synchronization signal is detected is obtained. This signal enters the discriminating circuit 7, and the first sync detection signal 50, which is a flag indicating that the signal is first detected by the first sync detection circuit, is output.

The ID code 61, the address code 62, the parity code 63, and the data 64 recorded after the synchronization signal 60 sequentially enter the S / P conversion circuit 3, and then the address code is stored in the latch circuit 4.
The ID code 61, the address code 62, and the parity code 63 are input to the parity circuit 5.

The address code 21 latched by the latch circuit 4 is input to the control circuit 7. The address code 21 is latched by the latch circuit 40 and then “+1” by the adder circuit 41. The output of the adder circuit 41 and the address code 21 are compared by the comparison circuit 42.
It is input to and it is checked whether these two codes match. This comparison output is sent to the discrimination circuit 45. During normal reproduction, since the address code is stepped up one by one for each block, the outputs of the comparison circuits are always in agreement and the continuity of the address code can be checked.

On the other hand, the output 23 of the parity check circuit 5 is also input to the discrimination circuit 45. Here, when the discrimination circuit 45 can check the parity check output and the continuity of the address code, it judges that the address code taken in by the latch circuit 4 is correct and switches the multiplexer circuit 8 to the latch circuit 4 side and also the counter circuit 6 Load this address code with load pulse 14.

On the other hand, when one or both of the two inputs to the discriminating circuit 45 become NG, the multiplexer circuit 8 is switched to the counter circuit 6 side configured to count up by one for each block and the address is changed. Is generated. However, the continuity of the address code cannot be checked in the first detected block signal.When the same pattern as the sync signal is erroneously detected due to noise in the area where data is not recorded, dropout etc. in the recording area Therefore, there is a problem in protection when a signal loss occurs. Therefore, protection is performed in the first sync detection circuit and the data area detection circuit.

The first detected address code 21 is discriminated based on the parity check output 23 without checking the continuity of the address code in the comparison circuit 42.
In other words, if the first synchronization is detected, the first SY
Since the NC output 50 is output, the discrimination circuit 45 does not perform continuity check of the address code for a certain period based on this output, and discriminates only by the parity check output 23. When the parity check circuit 5 detects no error, the discrimination circuit 45 determines that the address code 21 taken into the latch 4 is correct. As a result, the latch circuit 4 side is selected in the multiplexer circuit 8, and the counter circuit 6 is loaded with the address output 21.

If an error is detected by the parity check, the discrimination circuit 45 determines that the address code 21 is erroneous. As a result, the protection output 22 is selected in the multiplexer circuit 8. In the counter circuit 6, the address output 21 is not loaded and the previous value is +
It is incremented by 1. That is, since the protection counter circuit 6 is reset before the first synchronization detection is performed, the output corresponding to the first synchronization pulse is "0", and the value "0" is output as the address output. Is output.

As described above, for the first sync pulse, the continuity of the address code is not checked, but if no error is detected by the result of the parity check, the address code is output as the address and the error is detected. When is detected, the output of the counter 6 is output as an address to generate a correct address from the first data.

Next, the operation of address protection when a sync signal is detected outside the data area due to noise or the like will be described.

In FIG. 4, reference numeral 80 denotes a sync detection output that is erroneously detected outside the data area. Reference numeral 81 shows the operation in the conventional address protection circuit. The address protection operation is started based on the synchronization detection output 80, and the address protection operation is continued as it is until the synchronization detection is performed in the data area. As a result, the first address code in the data area could not be fetched, and the value "n" generated with the sync detection output 80 as a reference was output, causing an address error.

Reference numeral 82 shows the address output 21 in the address protection circuit of this embodiment. The data area detection circuit 44 in FIG. 2 detects that the number of undetectable synchronizations has continuously exceeded a predetermined number and inputs it to the discrimination circuit 45.

The discrimination circuit 45 resets the counter 6 and the first sync detection circuit 46 if the address code is already detected from the comparison circuit 42 and the parity check output 23, and detects the sync signal if it is outside the data area. It enters the waiting state until it is done.

On the other hand, in the case where the signal is lost due to the signal missing in the data area, only the first sync detection circuit 46 is reset and the address code is set to be fetched immediately by the result of the parity check circuit when the sync signal is obtained again. By doing so, the return of address generation is accelerated.

As a result, since the address is generated again from the point where the sync signal is detected next time, the data is written to the correct address.

As described above, according to the present invention, the first address protection has the conventional protection capability, and in the data continuous detection state, the parity check and the address code continuity check are performed. All address code errors can be detected and correct address protection can be performed. Further, by detecting the data area, it is possible to prevent an address error due to an incorrect synchronization code outside the data area.

FIG. 5 shows another embodiment according to the present invention. The same reference numerals as those in FIG. 1 have the same functions. Reference numeral 90 is a multiplexer circuit which switches the address output selected by the multiplexer 8 and the initial address 91 generated by the control circuit 7 to be the preset input of the count 6. A switching signal 92 is generated by the control circuit 7.

In the present embodiment, the output of the data area detection circuit 44 causes the counter circuit 6 to be loaded to an arbitrary preset value outside the data area. This is because when the AD code starts from an arbitrary address such as "128", the start address of the counter is set to "128".
To preset. This is because when the decision circuit 45 decides that it is out of the data area, the initial address 91 is set to "12".
The counter circuit 6 is set to 8 ", the multiplexer 90 is switched to the initial address 91 side, and the counter circuit 6 is loaded. In this way, the counter circuit can be started from an arbitrary address.

FIG. 6 shows another embodiment according to the present invention. 6, the same reference numerals as those in FIG. 1 have the same functions. In FIG. 6, 95 is an ID code check circuit, and 96 is an ID code check output. The ID code check circuit has the configuration shown in FIG. 7, and 97 is an n-number latch circuit, and 98 is a matching circuit for the outputs of the n ID-code latch circuits 97. FIG. 8 shows the configuration of the control circuit 7, and the same reference numerals as those in FIG. 2 have the same functions. Reference numeral 100 is a correction circuit for the AD code.

This embodiment utilizes the fact that the ID code does not change for each block, and detects whether or not the ID code continuously has the same value, thereby correcting the error of the address code and performing address generation. Is.

The ID code is a code indicating recording conditions and the like, and usually the same code is always input. As shown in FIG. 7, the ID code is sequentially taken in each block in the n latch circuits. This code is checked by the matching circuit 98, and it is judged whether or not the ID codes match n times in succession, and the ID code check output 96 is input to the control circuit 7.

On the other hand, when the parity check circuit 5 detects that the address code has an error, the correction circuit 100 corrects the address code. This is because the parity code is generated from the AD code and the ID code.
If the code is known by the ID check circuit 95, the address code can be obtained from the parity code and the ID code. However, in this case, to avoid erroneous correction of address code, to check the continuity of the address code corrected in the comparing circuit 42 ₂ is input to the determination circuit 45.

Even if the discrimination circuit detects an output from the parity check circuit or an error, if the corrected address code has continuity, the multiplexer 90 is switched to the correction address side and the correction address is loaded into the counter 6.

In this way, it becomes possible to generate a more correct address by using the ID code.

〔The invention's effect〕

According to the present invention, it is possible to generate a more accurate address, despite an error in transmission caused by dropout or the like.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a configuration diagram of a control circuit of an embodiment of the present invention, FIG. 3 is a diagram showing a reproduced intermittent signal, and FIG. FIG. 5 is a diagram showing an example of operation according to the invention, FIG. 5 is a circuit diagram showing another embodiment of the present invention, FIG. 6 is a circuit diagram showing still another embodiment of the present invention, and FIG. 7 is a correction circuit. A circuit diagram showing an example of
FIG. 8 is a circuit diagram showing an example of the discrimination circuit. 1 ... Synchronous detection protection circuit, 2 ... Timing circuit, 3 ... S / P conversion circuit, 4 ... Latch circuit, 5 ... Parity check circuit, 6 ... Counter circuit, 7 ... Control circuit, 46 ... First sync detection circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Keiji Noguchi Inventor Keiji Noguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Within the Home Appliance Research Laboratory, Hitachi, Ltd. (72) Inventor Hirohide Kobayashi 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Within Tate Video Engineering Co., Ltd. (72) Inventor Hiroki Fukuda, 292 Yoshida-cho, Totsuka-ku, Yokohama City, Kanagawa Prefecture Inside Hitate Video Engineering Co., Ltd. (56) Reference JP-A-58-125208 (JP, A) JP-A-59 -231713 (JP, A)

Claims (3)

[Claims] 1. Data is divided into blocks, and
A block synchronization signal, a block address code, and a parity code for detecting an error in this block address code are added to each block and recorded, and a block synchronization signal is detected in an address circuit that generates a block address from a reproduction signal during reproduction. A synchronous circuit and an address code circuit that takes in a block address code, a parity check circuit that performs a parity check, a first address circuit that counts the output of the synchronous circuit to generate a block address, and a block address that is generated by the address code circuit. A second address circuit, a comparison circuit for comparing whether the output of the address code circuit is stepped up or down, and a first synchronization signal detection circuit set by the synchronization signal first detected by the synchronization circuit. And the comparison And a switching circuit for switching the outputs of the first address circuit and the second address circuit, and the determination circuit for switching the output of the first address signal and the output of the parity check circuit. When there is no error in the outputs of the parity check circuit and the comparison circuit, the switching circuit selects the second address circuit, outputs the block address, and outputs the second address circuit first.
When the error is detected, the switching circuit is controlled to select the first address circuit and output the block address, and the discriminating circuit controls the first synchronizing signal detecting circuit to output the first synchronizing signal. An address circuit characterized in that an address is generated by controlling a switching circuit by the output of the parity check circuit until a signal is detected. 2. The determination circuit according to claim 1, further comprising a counter circuit that counts the number of undetectable synchronizations of the synchronization circuit and a comparison circuit that compares the output of the counter circuit. An address circuit characterized by resetting the first synchronization detection circuit and the first and second address circuits when the count value exceeds a predetermined value. 3. A parity check circuit according to claim 1, wherein the parity check circuit inputs the corrected address code to a comparison circuit of the discrimination circuit and generates an address from the corrected address code. Address circuit.