JP2573591B2 - Composite clock signal receiving and reproducing circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite clock signal receiving / reproducing circuit, and more particularly, to an 8 KHz sub clock signal from a composite bipolar clock signal comprising a 64 KHz clock signal as a main clock signal and an 8 KHz clock signal as a sub clock signal. And a composite clock signal receiving / reproducing circuit for receiving / reproducing.

2. Related Art As shown in the waveform example of FIG. 2, a composite bipolar clock signal of this kind has a sub clock signal of 8 kHz superimposed on a main clock signal of 64 kHz by violating the bipolar rule, that is, by a bipolar violation. In the drawing, a clock indicated by hatching is an 8 KHz sub clock signal by bipolar violation. By detecting the bipolar violation and resetting the frequency divider for dividing the composite bipolar clock signal by 1/8 in response to the detection timing, the 8 KHz sub clock signal is reproduced. .

Conventional reception and reproduction circuits for this kind of composite clock signal are:
Since the circuit is a signal receiving circuit in the same station and on the same floor, protection of the clock signal is generally not considered basically. Even if the protection of the clock signal is taken into consideration, the protection circuit is only added to the reception and reproduction circuit of the 64 KHz main clock signal, and in this case,
Since the presence or absence of protection is considered from the viewpoint of whether or not instantaneous interruption occurs in the composite clock signal, the protection circuit has a tuning circuit configuration.

In such a conventional composite clock signal receiving / reproducing circuit, a 64 KH
z The main clock signal is received and reproduced by the tuning circuit, but in the reception and reproduction of the 8 KHz sub-clock signal, a pseudo bipolar violation occurs due to the instantaneous interruption, which causes the reproduction of the incorrect 8 KHz sub-clock signal. Become. In other words, the 8 KHz sub-clock signal receiving / reproducing circuit is directly affected by the instantaneous interruption.

Even if the composite clock signal is not interrupted, if the bipolar rule is erroneous for some reason, pseudo bipolar violation will also occur, so 8 KHz
The sub clock signal reproducing circuit receives and reproduces an erroneous 8 KHz sub clock signal.

As described above, in the conventional circuit, the reception and reproduction of the 8 KHz sub-clock signal is configured to detect the bipolar violation and directly control the operation. Therefore, even if the pseudo bipolar violation as described above occurs, There is a drawback that the operation of receiving and reproducing the 8 KHz sub-clock signal is immediately performed assuming that it is a normal bipolar violation, and thus the reproduction of an incorrect sub-clock signal is performed.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in order to solve the above-mentioned drawbacks of the conventional device, and an object of the present invention is to provide a pseudo-bipolar circuit caused by an instantaneous interruption of a composite bipolar clock signal, an error in a bipolar rule, and the like. An object of the present invention is to provide a composite clock signal receiving / reproducing circuit capable of preventing reproduction of an erroneous sub clock signal caused by a violation.

A composite clock signal receiving and reproducing circuit according to the present invention is a composite clock signal receiving and reproducing circuit for reproducing a sub-clock signal by dividing a composite bipolar clock signal composed of a main clock signal and a sub-clock signal by a frequency divider. And
A detection circuit for detecting a bipolar violation of the composite bipolar clock signal; a shift register for shifting the detection signal by the period of the sub clock signal by the main clock signal; and a coincidence between the detection signal and an output signal of the register. And a reset circuit for resetting the frequency divider only when the determination result indicates a match.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, a bipolar violation detection circuit 1 receives a composite bipolar clock signal as shown in FIG.
Bipolar violation is detected at a portion (shown by oblique lines) where the 8 KHz sub-clock signal is inserted. The bipolar violation detected by the bipolar violation detection circuit 1 is input to an 8-bit register 2. The register 2 is controlled to be shifted by a 64 KHz main clock signal extracted and reproduced from the composite bipolar clock signal, and has an 8-bit shift register configuration.

The coincidence determination circuit 3 receives two inputs of the bipolar violation detected by the bipolar violation detection circuit 1 and the shift output of the 8-bit shift register 2, and determines the coincidence between these two inputs. The coincidence determination output controls the frequency division state of the 1/8 frequency divider 4.

The frequency divider 4 divides the frequency of the composite bipolar clock signal by 1/8, and is reset every time the coincidence determination circuit 3 generates a coincidence determination output.

In such a configuration, when the composite bipolar clock signal is received with the correct regularity as shown in FIG. 2, the bipolar violation detection circuit 1 sets every eight bits (corresponding to one cycle of the 8 KHz sub clock signal). In this case, a normal bipolar violation is detected. Therefore, in the match determination circuit 3, a match determination signal is obtained correctly every 8 bits, and the frequency division state of the 1/8 frequency divider 4 is correctly controlled. The signal is correctly received and reproduced.

In any of the composite bipolar clock signals,
If the bipolar rule is erroneously received for some reason, the erroneous signal is detected by the bipolar violation detection circuit 1, and the detection signal is shifted by 8 bits in the 8-bit register circuit 2 and sent to the match determination circuit 3. Is entered. At this time, since the bipolar violation detection circuit 1 no longer detects the bipolar violation, no detection signal is generated, and therefore the match determination circuit 3 does not make a match determination. As a result, since no coincidence output is generated from the coincidence determination circuit 3, the 1/8 frequency divider 4 is not reset and the abnormal frequency division operation is continued.

In this case, if there is no 8-bit register 2 and no match determination circuit 3 and the 1/8 frequency divider 4 is directly reset-controlled by the detection signal of the bipolar violation detection circuit 1 as described in the related art, The bipolar violation is immediately detected at the wrong place in the composite bipolar clock signal, so the 1/8 frequency divider is reset immediately, at which point an 8KHz clock is spuriously generated. Will be.

However, in the present invention, as shown in the block diagram of FIG.
Since the Hz sub-clock signal protection circuit is provided, it is possible to prevent false detection of pseudo bipolar violation as described above. It is clear that the same operation as described above is performed even when a momentary interruption of the composite clock signal occurs.

Effect of the Invention As described above, according to the present invention, a protection circuit for detecting a bipolar violation by an 8-bit register and a coincidence determination circuit is inserted into a circuit for receiving and reproducing an 8 KHz sub-clock signal from a composite bipolar signal. By providing such a structure, there is an effect that erroneous detection of pseudo bipolar violation caused by instantaneous interruption of a composite bipolar signal, erroneous bipolar law, or the like is prevented. Therefore, the reproduction of the 8 KHz sub clock signal can always be performed correctly.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 4 is a diagram illustrating a waveform example of a composite bipolar clock signal of a main clock signal and an 8 KHz sub clock signal. Description of Signs of Main Part 1 Bipolar violation detection circuit 2 8-bit register 3 Matching judgment circuit 4 1/8 frequency divider

Claims (1)

(57) [Claims] 1. A composite clock signal receiving / reproducing circuit for reproducing a sub-clock signal by dividing a composite bipolar clock signal comprising a main clock signal and a sub-clock signal by a frequency divider. A detection circuit for detecting the bipolar violation, a shift register for shifting the detection signal by the period of the sub clock signal by the main clock signal, and a judgment circuit for judging coincidence between the detection signal and an output signal of the register. Wherein the frequency divider is reset and the sub clock signal is output only when the determination result indicates a match.