JPH0575892A - Signal discrimination circuit - Google Patents

Abstract

PURPOSE:To provide the signal discrimination circuit capable of discriminating an NTSC system from a MUSE system in any bit stream. CONSTITUTION:A signal discrimination circuit consists of a frame synchronizing processing circuit 1, a timing circuit 3, and a synchronizing error state counter circuit 9. The frame synchronizing processing circuit 1 detects a synchronizing code in the inputted bit stream data Bs to protect the synchronization, outputting a synchronizing error flag CEF in a synchronizing error state. The synchronizing error flag CEF is counted by the synchronizing error state counter circuit 9. This synchronizing error state counter circuit 9 generates a mode switching signal ms when the counted value reaches to the prescribed value (i). This mode switching signal changes the synchronizing frame detection comparison cycle of the timing circuit 3 to another cycle. The discrimination between the NTSC and MUSE systems is enabled by this mode switching signal ms.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an NTSC (national telecommunications system) used in a satellite broadcast receiving system.
revision system committe
e) method and MUSE (multiple sub-ny)
The present invention relates to a signal discriminating circuit for discriminating between a “quist sampling encoding” system, and particularly by processing a bit stream signal of the NTSC system and the MUSE system
The present invention relates to a signal discriminating circuit capable of performing the two types of automatic discrimination.

[0002]

2. Description of the Related Art Conventionally, in a satellite broadcasting system using a broadcasting satellite, the frame structure of a bit stream of PCM audio data is, as is well known, NTSC system and M
Two types are used, the USE method. The frame structure of the NTSC system bit stream is 2048 [bits], and the frame structure of the MUSE system bit stream is 1350 [bits]. When such a bitstream is received by a single receiver, the currently received bitstream is NTSC or MU.
It is necessary to identify whether it is the SE system and process the PCM voice data and the like based on this identification.

FIG. 6 is a block diagram showing the configuration of a conventional signal identifying circuit for identifying the NTSC system or the MUSE system. The signal identification circuit shown in FIG. 6 is an NTSC system or MU.
This is to identify whether it is the SE method. In this signal identification circuit, the bit stream Bs is input to the frame synchronization processing circuit 101. The frame synchronization processing circuit 101
A synchronization pattern is detected from the bit stream Bs, synchronization is established so that synchronization can be established even if some synchronization detection error occurs, and the data string and the synchronization detection synchronization signal Cc from the timing circuit 103 are synchronized.

Next, the number of frame constituent bits of the bit stream Bs currently being received is 204 in the NTSC system.
In case of 8 bits, the input clock CL is 2.048
[MHz], and this input clock CL is input to the timing circuit 103 and the PLL circuit 105. At this time,
If the PLL circuit 105 is set to lock at 2.048 [MHz], the PLL circuit 105 does not output the PLL error flag EF, which is the lock release.

On the other hand, the received bit stream Bs
1350 in which the number of frame constituent bits is MUSE
When changed to [bit], the input clock CL is also 1.3
Change to 5 [MHz]. Then, until now, 2.048
The PLL circuit 105 set to lock to the input clock CL of [MHz] cannot lock to the input clock CL of 1.350 [MHz], and the PLL circuit 105
Outputs the PLL error flag EF. This allows
In the data processing circuit 107 which processes the output data DT from the frame synchronization processing circuit 101, the clock given from the PLL circuit 105 becomes abnormal and the data processing becomes impossible.

Therefore, P is set by the PLL error flag EF.
When the clock lock setting of the LL circuit 105 is changed to the other, the PLL circuit 105 is locked to the input clock CL of 1.350 [MHz]. As a result, the data processing circuit 107 normally performs data processing. The synchronization error state counter 109 counts the synchronization error flag CEF from the frame synchronization processing circuit 101.

In the case of the signal identifying circuit, when the data rates of the NTSC system and the MUSE system are different, the PLL error flag EF is output from the PLL circuit 105, but the bit stream of the bit stream having the same data rate has the same frame configuration. If the PLL circuit 105
Since the error flag EF is not output, it is impossible to distinguish between both types, and the data processing of the data processing circuit 107 becomes abnormal.

[0008]

In the above-mentioned conventional signal identifying circuit, when the data rates of the bit streams are the same, the input clocks that are input are the same even if the frame configuration changes, so that the PLL circuit is input. The synchronous lock is not released, and the PLL error flag is not set. Therefore, when the data rates of the bit streams are the same as described above, there is a case where the automatic discrimination between the NTSC system and the MUSE system becomes impossible.

Therefore, an object of the present invention is to provide a signal discrimination circuit which can discriminate between the NTSC system and the MUSE system in any bit stream.

[0010]

In order to achieve the above object, a signal identifying circuit according to the present invention detects a synchronization state from a synchronization pattern in input bit stream data and outputs a synchronization error state. In the case of, a synchronization processing means for outputting a synchronization error flag, a counter means for counting the synchronization error flag output from the synchronization processing means, and for outputting a mode switching signal when the count value reaches a predetermined value, The gist of the present invention is to have a detection cycle changing means for changing the detection cycle of the synchronization pattern in the synchronization processing means when the mode switching signal output from the counter means is input.

Further, the signal identifying circuit according to the second aspect of the present invention includes a synchronization processing means for detecting a synchronization state from the synchronization pattern in the input bit stream data and outputting a synchronization error flag in the synchronization error state. The counter means for counting the synchronization error flag output from the synchronization processing means and outputting a mode switching signal when the count value reaches a predetermined value, and the mode switching signal output from the counter means are input. And a synchronization pattern changing means for changing the synchronization pattern in the synchronization processing means.

[0012]

According to the first aspect of the present invention, the synchronization detection processing is performed based on the synchronization detection cycle of the input bitstream data, and when the synchronization error is detected, the synchronization error flag is set and the synchronization error flag is set. The flag is counted, and when the counted value reaches a predetermined numerical value, synchronization is measured and signal identification is performed by changing the detection cycle of the synchronization pattern in the synchronization processing means.

According to the second aspect of the present invention, the synchronization detection processing is performed based on the synchronization detection cycle of the input bitstream data, and when a synchronization error is detected, a synchronization error flag is set and the synchronization error flag is set. Counting flags,
When the count value reaches a predetermined numerical value, the synchronization is measured by changing the synchronization pattern in the synchronization processing means to identify the signal.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a signal identifying circuit according to the present invention.

In the signal discrimination circuit shown in FIG. 1, the PCM
The bit stream data Bs of audio data is supplied from the terminal Ti to the frame synchronization processing circuit 1 as a synchronization processing means. The frame synchronization processing circuit 1 detects a synchronization code as a synchronization pattern from the input bitstream data Bs and protects the synchronization.

Now, the synchronization protection executed in the frame synchronization processing circuit 1 will be described with reference to the state transition diagram of FIG. The state of the frame synchronization processing circuit 1 is changed by the synchronization error flag CEF accompanying the synchronization detection. First, the frame synchronization processing circuit 1, when the initial state is "0", shifts to the state of "1" when the synchronization is first detected (S1). Further, the frame synchronization processing circuit 1
Then, if the synchronization is normally detected, the state shifts to the state of "7" (S2), and thereafter, if the synchronization is normally detected, "7".
Will be maintained (S3). Here, if the frame synchronization processing circuit 1 does not correctly detect the synchronization,
The state of "7" is sequentially shifted to the lower states such as "6", "5", "4", ... (S4, S5, ..., S).
10). In the process of sequentially shifting to the lower state (S4,
(S5, ..., S10), and if the synchronization is achieved, the state shifts to the state "7" again (S11, S12, ..., S15). Also,
When "0" cannot be synchronized at all,
"0" will be maintained (S16).

Here, the states "0" and "1" are set to the asynchronous state (Ang), and the states "2" to "7" are set to the synchronous state (Aok).
Then, the frame synchronization processing circuit 1 outputs the synchronization error flag CEF when it is "0" or "1". This frame synchronization processing circuit 1 has a data string DT in the synchronized state.
And a timing signal, the synchronization detection signal TC is output at the frame synchronization cycle, the synchronization detection signal TC is output to the timing circuit 3 as the detection cycle changing means, and the data string DT is output to the data processing circuit 7. The synchronization error flag CEF is supplied to the synchronization error state counter circuit 9 as the counter means.

The data processing circuit 7 forms the audio data Sa from the input data string DT and outputs it from the output terminal Toa. The synchronization error state counter circuit 9 counts the synchronization error flag CEF from the frame synchronization processing circuit 1 based on the clock Ck from the timing circuit 3, and when the count value reaches a constant value, the current frame configuration bit The mode switching signal ms for changing the number processing is output from the output terminal Tom, and the mode switching signal ms is supplied to the timing circuit 3. The timing circuit 3 forms a sync detection sync signal Cc based on the mode switching signal ms. The timing circuit 3 and the data processing circuit 7 include
The reference clock CL is input from the outside.

The operation of the embodiment thus configured is shown in FIG.
3 will be described with reference to the timing chart of FIG. 3 and the bit configuration explanatory diagram of FIG. 3 (a) is shown in FIG. 4 (a).
3 (b) shows the cycle of the synchronization code Cx of the bit stream data 401, FIG. 3 (b) shows the cycle of the synchronization code Cy of the bit stream data 403 of FIG. 4 (b), FIG. d) is a synchronization error flag CEF,
3E shows the count value of the synchronization error state counter circuit 9, and FIG. 3F shows the mode switching signal ms. Note that Dx in FIG. 4A is the m [bit] data of the bitstream data 401, and Dx in FIG.
y represents n [bit] data of the bit stream data 403, and has a relationship of m <n.

Now, the signal discriminating circuit having the above configuration is shown in FIG.
It is assumed that the mode is set to receive the bit stream data Bs having the number of frame constituent bits of n [bit] as shown in (b). Here, the bit stream data 401 having the number of frame constituent bits of m [bits] shown in FIG. 4A is input to the frame synchronization processing circuit 1 from the input terminal Ti. The frame synchronization processing circuit 1 is set to a mode in which the number of frame constituent bits is n [bit], and the input bitstream data 401.
Since the cycle of the synchronization code Cx is m clocks (see FIG.
(See (a)), the synchronization cannot be detected, and the synchronization error flag CEF is given to the synchronization error state counter circuit 9 in a cycle of n clocks (time ti to ti-1 in FIG. 3, where i is a synchronization error). It corresponds to a predetermined value of the state counter circuit 9). The synchronization error state counter circuit 9 counts the synchronization error flag CEF (time ti to ti- in FIG. 3).
1), the count value is a predetermined value i (here, i = “6”)
When it reaches, the mode switching signal ms changing from the logic "1" to the logic "0" is output (time ti in FIG. 3). The mode switching signal ms is output to the outside from the output terminal Tom and is also supplied to the timing circuit 3. Then, the timing circuit 3 changes the mode to a mode in which the synchronization detection synchronizing signal Cc that can be synchronized with the m clocks is given to the frame synchronization processing circuit 1 to process the bit stream data 401 having the frame constituent bit number m [bit]. As a result, the frame synchronization processing circuit 1 detects the synchronization in the state where the cycle of the synchronization code Cx of the bit stream data 401 is m clocks and obtains the synchronization detection signal TC (time ti + 1-), so that the state transition is performed again. Shifts to "7" and the synchronization error flag CEF is no longer output.

Further, as described above, the bit stream data data 40 having the number of frame constituent bits of m [bits]
1 is being processed by the frame synchronization processing circuit 1,
Even if the number of frame constituent bits is changed to the bit stream data 403 of n [bits] again, the synchronization error flag CEF is generated in the same manner as the above-mentioned operation, and this is counted by the synchronization error state counter circuit 9, and the count value is obtained. Reaches a predetermined value i, a mode switching signal ms for outputting the bit stream data 403 is output. As a result, the frame synchronization processing circuit 1 again causes the bit stream data 403 with the number of frame constituent bits to be n [bit].
Will be processed.

The above-described embodiment is a configuration example in which even if the bit rate is the same, if the number of bits constituting the frame is different, the signal can be identified only by the bit stream data.

FIG. 5 is a block diagram showing a second embodiment of the present invention. In the second embodiment, the two methods can be distinguished when the frame synchronization patterns are different.

The second embodiment shown in FIG. 5 is a modification of the frame synchronization processing circuit 1 of the first embodiment. The frame synchronization processing circuit 1a according to the second embodiment executes automatic identification of the NTSC system or the MUSE system by the frame synchronization pattern. This frame synchronization processing circuit 1a is
Bit stream data B input from the input terminal Ti
A shift register 11 that holds s and can output a k-bit data string DT, a synchronization pattern comparison circuit 13 that compares data from the shift register 11 with an input synchronization pattern, and a synchronization pattern comparison circuit 13 It is composed of a sync pattern circuit 15 for giving a pattern, and a sync protection circuit 17 for taking in the coincidence pulse IP output from the sync pattern comparison circuit 13 for synchronous protection and for outputting a sync error flag CEF when they do not coincide. Note that the second embodiment is the same as the first embodiment in the other respects, and the description thereof will be omitted. In addition,
The shift register 11, the synchronization pattern comparison circuit 13 and the synchronization pattern circuit 15 constitute a synchronization pattern changing means.

Now, it is assumed that the signal identification circuit is modified so as to perform the processing corresponding to the NTSC system bit stream data Bs. At this time, for example, the a pattern corresponding to the NTSC bit stream data Bs is supplied from the sync pattern circuit 15 to the sync pattern comparison circuit 13.

At this time, the MUSE type bit stream data Bs is transferred from the input terminal Ti to the shift register 11
Input to the shift register 11, the shift register 11 holds the bitstream data Bs. The held bit stream data Bs is compared with the pattern a from the sync pattern circuit 15 by the sync pattern comparison circuit 13, but since they do not match, the sync protection circuit 17 outputs the sync error flag CEF. As a result, the synchronization error state counter circuit 9 counts the synchronization error flag CEF.

In the synchronization error state counter circuit 9, when the synchronization error flag CEF reaches a predetermined value, the mode switching signal ms is output. This mode switching signal ms
Is the synchronization pattern circuit 15 as a synchronization pattern switching signal.
Entered in. The sync pattern circuit 15 outputs a b pattern corresponding to the MUSE bitstream data Bs. As a result, since the coincidence pulse IP is output from the synchronization pattern comparison circuit 13, the synchronization protection circuit 1
7 performs synchronization protection as in the first embodiment, and normal processing is performed.

If the NTSC bit stream data Bs is input from the input terminal Ti, the same processing as described above can be performed for identification.

According to the second embodiment, when the frame synchronization patterns are different, the two methods can be identified and dealt with.

Although the first embodiment and the second embodiment have been separately described above, in actual identification, the synchronization pattern detection cycle and the second embodiment in the first embodiment are changed. It goes without saying that the frame structure can be identified and dealt with more reliably by changing the synchronization pattern in the embodiment.

[0031]

As described above, according to the first aspect of the present invention, the identification can be performed based on the synchronization error flag. Therefore, even if the bit rate is the same or the number of bits constituting the frame is different. According to the second aspect of the present invention, the frame structure can be surely identified, and even in the case of bit stream data having a frame structure having a different synchronization pattern in the frame, the frame structure can be surely identified. It is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment according to the present invention.

FIG. 2 is a diagram for explaining a synchronization state transition according to the first embodiment of this invention.

FIG. 3 is a timing chart for explaining a mode switching signal according to the synchronization error flag of the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a frame configuration processed in the first embodiment of the present invention.

FIG. 5 is a partial block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional device.

[Explanation of symbols]

 1 frame synchronization processing circuit 3 timing circuit 7 data processing circuit 9 synchronization error state counter circuit 11 shift register 13 synchronization pattern comparison circuit 15 synchronization pattern circuit 17 synchronization protection circuit

Claims (2)

[Claims] 1. A synchronization processing means for detecting a synchronization state from a synchronization pattern in input bit stream data and outputting a synchronization error flag when in a synchronization error state, and a synchronization error flag output from this synchronization processing means. Counter means for outputting a mode switching signal when the counted value reaches a predetermined value, and for detecting a synchronization pattern in the synchronization processing means when the mode switching signal output from the counter means is input. A signal recognition means comprising: a detection cycle changing means for changing a cycle. 2. A synchronization processing means for detecting a synchronization state from a synchronization pattern in input bit stream data and outputting a synchronization error flag when in a synchronization error state, and a synchronization error flag output from this synchronization processing means. Counter means for outputting a mode switching signal when the counted value reaches a predetermined value, and for changing the synchronization pattern in the synchronization processing means when the mode switching signal output from the counter means is input. And a synchronization pattern changing means for performing the signal identification means.