JPH0795445A - Detection of synchronizing signal - Google Patents

Abstract

PURPOSE:To prevent omission of data which can become effective data by varying the number of bits, which coincide with a synchronizing signal as the reference for discrimination of the synchronizing signal, by the error rate of a digital reproduced signal. CONSTITUTION:A signal A inputted to a synchronous detection circuit 4 is inputted to an input data register 11 and is compared with the synchronizing pattern generated by a synchronizing pattern generator 13 by a synchronizing pattern coincidence detecting circuit 12 with each bit as the unit, and the number of coincident bits is counted by a coincident bit counter 15. A signal E of the number of coincident bits is inputted to a synchronizing pulse generator 16, and it is discriminated whether the signal A is the synchronizing signal or not by a threshold signal F from a microcomputer 10; and if it is discriminated that the signal A is the synchronizing signal, a synchronizing pulse signal G is generated and is sent to a data separating circuit 14. By this constitution, the synchronizing signal can be tentatively detected even in the case of a high error rate, and a part which is not the synchronizing signal is prevented from erroneously discriminated as the synchronizing signal in the case of a low error rate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync signal detecting method used in a digital signal reproducing apparatus having a digital sync signal.

[0002]

2. Description of the Related Art Conventionally, when a sync signal is detected, the number of bits matching the sync signal, which is a reference for determining the sync signal, is fixed. First, FIG. 6 shows a reproducing circuit of a digital VTR using a conventional synchronizing signal detecting method.
In FIG. 6, the digital signal recorded on the magnetic tape 31 is reproduced by the reproducing head 17 and amplified by the reproducing preamplifier 18 by about 60 dB. The equalizer circuit 19 corrects the frequency characteristic of the electromagnetic conversion system, and at the same time, it is converted into a digital signal by a circuit (not shown) using a comparator. The signal H output from the equalizer circuit 19 is input to the sync detection circuit 20, the sync signal is detected, and the sync signal part and the data part are separated. On the other hand, the output of the equalizer circuit 19 is the clock recovery PLL circuit 25.
Is also input to the reference clock signal J of the sync signal detection circuit.
Is generated. The data separated by the sync signal detection circuit 20 is input to the error correction circuit 22, the memory 21 is used as a working area, error correction and interpolation are performed, and the data is input to the deshuffling circuit 23. Here, after undergoing deshuffling processing, the data is rearranged in time-series order, converted into an analog signal M by the DA conversion output circuit 24, and output as a reproduced video signal from the VTR main body (not shown). It

Next, FIG. 7 shows details of the synchronization detection circuit 20 of FIG. In FIG. 7, the signal H input to the sync detection circuit is input to the input data register 26, and the sync pattern generated by the sync pattern generator and the sync pattern match detection circuit are compared for each bit, and all the bits match. In this case, the output signal K of the sync pattern coincidence detection circuit 27 becomes High level, and the sync pulse signal L is sent from the sync pulse generator 30 to the data separation circuit 29. The data separation circuit 29 separates the reproduction signal into a sync signal portion and a data portion by the sync pulse signal L, and outputs a data signal I.

Further, in FIG. 8, the input data register 26,
Sync pattern match detection circuit 27, sync pattern generator 2
8 shows a concrete circuit example. R _{0 to} R ₇ are shift registers, which form the input data register 34. S ₀ ~ S ₇
Is a NOR gate, one input terminal of each gate is fixed to the High level or the Low level in the same order as the synchronization signal "10011101", and the signal of the same level as the synchronization signal is input to the other input terminal. When it is turned on, the output of the gate becomes "High". The outputs of S _{0 to} S ₇ are input to the AND gate 35, respectively. Therefore,
R ₀ to R ₇ shift register data every sync signal "
No in S _{0 to} S ₇ only when it matches 10011101 "
All R gate outputs go to "High" level, and AN
The output signal K of the D gate 35 becomes "High" level.

[0005]

However, in the prior art, when the sync signal is detected, the number of bits matching the sync signal, which is the reference for determining the sync signal, is fixed. The synchronization signal is determined only when all the bits match, and if even one bit of the synchronization signal is incorrect, it is not determined to be the synchronization signal.

Therefore, all the digital data of the block having the synchronizing signal becomes invalid. When the error rate is large, the probability that an error will occur in the synchronization signal also increases. However, since the digital data is corrected by the error correction circuit, it can be valid data even if there is an error. Therefore, data that can be valid data is truncated.

Further, in the case of determining a sync signal by matching a small number of bits, if the error rate is small, the probability that an error occurs in the sync signal is low, and the portion that is not the sync signal is erroneously determined to be the sync signal. Becomes higher.

It is an object of the present invention to provide a synchronization signal detecting method that solves the above conventional problems.

[0009]

According to the present invention, the number of bits which coincide with a reference sync signal for determining a sync signal when the sync signal is detected is varied according to the error rate of the digital reproduction signal. ing.

[0010]

Therefore, according to the present invention, the number of bits matching the reference sync signal for determining the sync signal when the sync signal is detected is varied according to the error rate of the digital reproduction signal. If the error rate is small, set a large number of bits that match the synchronization signal that serves as the reference for determining the synchronization signal, and if the error rate is large, use the synchronization signal that serves as the reference for determining the synchronization signal. Set a small number of matching bits.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a reproducing circuit of a digital VTR using the sync signal detecting method of the present invention. In FIG.
The digital signal recorded on the magnetic tape 31 is reproduced by the reproducing head 1 and about 60 by the reproducing preamplifier 2.
It is amplified by dB. Thereafter, the equalizer circuit 3 corrects the frequency characteristic of the electromagnetic conversion system, and at the same time, it is converted into a digital signal by a circuit (not shown) using a comparator. The signal output from the equalizer circuit 3 is input to the sync detection circuit 4, the sync signal is detected, and the sync signal part and the data part are separated. Next, in order to determine the sync signal as the sync signal, error rate information that determines the number of bits that match the original sync signal is sent from the error correction circuit 6 to a microcomputer (hereinafter abbreviated as microcomputer) 10. , The threshold signal F having the same number of bits as the original synchronization signal is input to the synchronization signal detection circuit 4.

On the other hand, the output of the equalizer circuit 3 is also input to the clock recovery PLL circuit 9 and the reference clock (C) of the sync signal detection circuit 4 is generated. Sync signal detection circuit 4
The data separated by is input to the error correction circuit 6, the memory 5 is used as a working area, error correction and interpolation are performed, and the data is input to the deshuffling circuit 7. The deshuffling circuit 7 receives the deshuffling processing, rearranges the data in a time series order, converts it into an analog signal N by the DA conversion output circuit 8, and outputs it as a reproduced video signal from the VTR main body (not shown). To be done.

The synchronization detection circuit 4 according to the synchronization signal detection method of the present invention will be described in detail with reference to FIG. First, the signal A input to the synchronization detection circuit 4 is input to the input data register 11
Is input to the sync pattern generator 13 and is compared with the sync pattern generated by the sync pattern generator 13 for each bit in the sync pattern match detection circuit 12, and the number of matched bits is counted in the match bit counter 15. Signal E of the number of matched bits
Is input to the sync pulse generator 16, and it is determined by the threshold value signal F from the microcomputer 10 whether or not it is a sync signal. When it is determined that it is a sync signal, a sync pulse signal G is generated and data separation is performed. It is sent to the circuit 14. The data separation circuit 14 separates the reproduction signal into a sync signal part and a data part by the sync pulse signal G, and outputs a data signal B.

Further, in FIG. 3, the input data register 11,
Sync pattern match detection circuit 12 and sync pattern generator 1
3, specific circuit examples of the coincidence bit counter 15 and the synchronization pulse generator 16 are shown. In this figure, R _{0 to} R ₇ are shift registers, which form the input data register 33. S _{0 to} S ₇ are NOR gates, and one input terminal of each gate is fixed to “High” level or “Low” level in the same order as the synchronization signal “10011101” and synchronized with the other input terminal. The output of the gate becomes “High” when a signal of the same level as the signal is input. Therefore, the number of “High” signals E of the outputs of S _{0 to} S ₇ is the number of bits that matches the synchronization signal. This number of signals E is compared with the threshold signal F of the number of bits matching the original synchronization signal sent from the microcomputer 10, and if E ≧ F, it is determined to be a synchronization signal and output as a synchronization pulse generation control signal G. To do.

FIG. 4 shows an example of the relationship between the error rate and the threshold value, which determines the threshold value signal F having the number of bits which coincides with the synchronization signal judged as the synchronization signal output from the microcomputer 10.

Next, an operation example of the circuit shown in FIG. 3 will be described with reference to FIG. Here, the input signal input to the circuit of FIG.
In the case of the input signal 1 shown in (2), the number of bits matching the synchronization signal shown in (1) of FIG.
The threshold signal F from 0 is the value shown in FIG.
In both cases of 7 and 6, the comparator of FIG.
As shown in -b), the sync pulse generation control signal G that outputs the sync signal period of "High" is output.

In the case of the input signal shown in (4) of FIG. 5, the number of bits matching the synchronization signal shown in (1) of FIG. 5 is 6, and the threshold signal F from the microcomputer 10 is shown in FIG. In the case of 8 and 7 out of the values shown, the comparator 32 of FIG. 3 remains “Low” as shown in (4-b-1) of FIG. 5, and the synchronization pulse generation control signal G is output. Not done. Microcomputer 10
If the threshold signal F from 6 is 6 out of the values shown in FIG. 4, the comparator 34 of FIG. 3 indicates that the synchronization signal period is “High” as shown in (4-b-2) of FIG. A sync pulse generation control signal G that satisfies the above condition is output.

[0018]

As described above, according to the present invention, when the sync signal is detected, the number of bits matching the sync signal which is the reference for determining the sync signal is varied according to the error rate of the digital reproduction signal. Therefore, when the error rate of the sync signal is large, by setting the number of bits that match the sync signal that is the reference for determining the sync signal to be small, all bits are As in the case of determining the synchronization signal only when they match, if the synchronization signal is erroneous even one bit, it is not determined to be the synchronization signal, and the digital data of the block having the synchronization signal is never invalidated.

This is based on the fact that when the error rate is high, the probability that an error will occur in the synchronization signal increases, and since the digital data is corrected by the error correction circuit, it becomes valid data even if there is an error. The property of gaining can be effectively used.

If the error rate is small, the probability that an error will occur in the sync signal is small. Therefore, by setting a large number of bits that match the sync signal, which is the reference for determining the sync signal, the sync signal is set. It is possible to prevent erroneous determination of a portion that is not a synchronization signal.

[Brief description of drawings]

FIG. 1 is a block diagram of a reproducing circuit of a digital VTR using the sync signal detecting method of the present invention.

FIG. 2 is a configuration diagram of a synchronization detection circuit according to the synchronization signal detection method of the present invention.

FIG. 3 is a block diagram of an input data register 1 in FIG. 2 according to the present invention.
1 is a specific circuit diagram of a sync pattern match detection circuit 12, a sync pattern generator 13, a match bit counter 15, and a sync pulse generator 16. FIG.

FIG. 4 is a diagram showing an example of a relationship between an error rate and a threshold value according to the present invention.

5 is an operation timing diagram of the circuit of FIG. 3 according to the present invention.

FIG. 6 is a block diagram of a reproducing circuit of a digital VTR using a conventional sync signal detecting method.

FIG. 7 is a configuration diagram of a synchronization detection circuit according to a conventional synchronization signal detection method.

FIG. 8 relates to a conventional example, and the input data register 2 in FIG.
6 is a specific circuit diagram of the sync pattern matching detection circuit 27 and the sync pattern generator 28. FIG.

[Explanation of symbols]

 4 Sync Detection Circuit 6 Error Correction Circuit 10 Microcomputer 12 Sync Pattern Match Detection Circuit 13 Sync Pattern Generator 15 Match Bit Counter 16 Sync Pulse Generator

Claims (1)

[Claims] 1. A digital signal reproducing apparatus, wherein the number of bits that coincide with a synchronizing signal which is a reference for determining a synchronizing signal when detecting the synchronizing signal is varied according to an error rate of the digital reproducing signal. Sync signal detection method.