JP3213439B2 - Sync signal detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PCM still picture reproducing apparatus.

[0002]

2. Description of the Related Art In an 8 mm VTR, a standard for recording PCM still image data in a PCM audio recording region independent of a recording region for FM-modulated video data (hereinafter referred to as "new standard") has been proposed. I have. In this new standard, one screen is composed of 768 pixels × 488 lines, and P
The recording of CM still image data is PC of 8 pixels x 4 lines
M still image data is defined as one block, and PCM still image data for four lines recorded in block units is defined as one recording unit.

When reproducing the PCM still image data recorded in this way, the read PCM still image data is corrected for each word, but an erroneous signal is generated due to the limit of the correction capability. May not be corrected. Synchronous signals containing incorrect signals are not recognized as synchronous signals,
There is a need for a synchronization signal detection circuit that detects a synchronization signal including an erroneous signal as a synchronization signal.

As a conventional technique, there is no technique that can be directly applied to the new standard. However, regarding detection of a synchronization signal, it is conceivable to detect a synchronization signal by matching or mismatching with predetermined synchronization signal data. .

[0005]

However, when a synchronous signal is detected due to coincidence or non-coincidence with predetermined synchronous signal data, there is a problem that a synchronous signal that has not been error-corrected is not detected as a synchronous signal. . In view of the above problems, an object of the present invention is to provide a synchronization signal detection circuit that can detect a synchronization signal having an error as a synchronization signal.

[0006]

In order to solve the above-mentioned problems, a first aspect of the present invention is a synchronous signal detecting apparatus for detecting a synchronous signal composed of M words in PCM still image data recorded in a PCM audio recording area. A predetermined data generating means for generating predetermined data that is predetermined data for each word constituting a synchronization signal; a receiving means for receiving PCM still image data; and a PCM still image data received by the receiving means. Data holding means for holding, and comparing means for reading data of M words in a continuous receiving order from the data holding means and comparing the data with the predetermined data in a corresponding order;
Counting means for counting the number of words which do not match the predetermined data in the comparison result for each M words and outputting a count value; and determining whether the count value output by the count means is equal to or less than a predetermined value. Determining means for outputting a determination flag when the value is equal to or less than a predetermined value; and determining whether an Nth word in the M words of the signal compared by the comparing means matches the predetermined data in a corresponding order. And a specific word judging means for outputting a match flag when a match is made, and synchronizing the data of the M words when receiving a judgment flag from the judging means and simultaneously receiving a match flag from the specific word judging means. And synchronizing signal determining means for determining a signal.

[0007]

According to the present invention, when it is determined whether or not a received signal is a synchronizing signal composed of M words, each word constituting the signal is compared with predetermined data that each word of the synchronizing signal should have. Then, the number of words that do not match the predetermined data is counted for every M words, and as a result of the counting, when the count value is equal to or less than the predetermined value and the word present at a specific position of the signal matches the predetermined data. Is determined that the received signal is a synchronization signal.

[0008]

FIG. 1 is a drawing showing an example of the configuration of a synchronization signal detection circuit. The reproduction data handled by the synchronization signal detection circuit is PCM still image data for four lines on the display screen, and the synchronization signal existing at the head of the reproduction data is composed of 8 bytes and is shown in FIG. The data is input from the input terminal B in synchronization with the reproduction data transfer timing pulse.

1 to 8 are 8-bit latches, 9 is 8 CLOC
Kwindow, 10 is a 3-bit counter, 11 is an initialization circuit, 12 is an 8-word selector, 13 is a synchronization signal pattern generation circuit, 14 is a comparison circuit, 15 is a mismatch flag counter, 16 is a judgment circuit, 17 is an FFH comparison circuit, 1
8 is an output circuit. The 8-bit latches 1 to 8 are 8-bit latch circuits that hold demodulated and error-corrected reproduced data input from the input terminal B. Here, the control of storage of the reproduction data is performed by a latch signal input through the input terminal A.

The 8CLOCK window 9 has a gate. When the latch signal is received, the gate is opened, and when the initialization flag is received from the initialization circuit 11, the gate is closed. Here, when this gate is open,
The clock shown in FIG. 2A is output to the 3-bit counter 10 and is not output in the closed state. 3b
The it counter 10 reads the 8CLOCK window 9
The counter is a 3-bit counter that counts the clock (see FIG. 2A) received from the CPU and outputs the count value to the initialization circuit 11, the 8-word selector 12, and the synchronization signal pattern generation circuit 13. Upon receipt, the count value is set to 0.

The initialization circuit 11 uses, for example, a 3-bit matching circuit. When the count value of the 3-bit counter 10 becomes 7, the initialization flag is set to the 8CLOCKw.
output 9, the 3-bit counter 10, the mismatch flag counter 15, and the output circuit 18. 8 words
The selector 12 uses, for example, an 8-channel multiplexer. The selector 12 reads reproduced data from the 8-bit latches 1 to 8 according to the count value of the 3-bit counter 10 and outputs the read data to the comparison circuit 14.

The synchronizing signal pattern generating circuit 13 includes a memory for holding predetermined data (synchronizing signal predetermined data) of each word constituting the synchronizing signal, and a memory control unit for reading out the predetermined data held in the memory. In response to the output signal of the counter, the memory control unit reads out the predetermined data of the corresponding synchronization signal, outputs it to the comparison circuit 14, and sets the count value to 0 when receiving the initialization flag. In the present embodiment, it is assumed that, for example, the synchronization signal predetermined data shown in FIG. 3 is used as the synchronization signal predetermined data held by the memory.

The comparing circuit 14 uses, for example, an 8-bit matching circuit. The comparing circuit 14 compares the reproduced data output from the 8-word selector 12 with the corresponding synchronization signal predetermined data of the synchronization signal pattern generation circuit 13 and determines whether the data match. If not, the mismatch flag is output to the mismatch flag counter 15. The non-coincidence flag counter 15 is, for example, a 3-bit counter, counts the non-coincidence flag of the comparison circuit 14, outputs the count value to the determination circuit 16, and sets the count value to 0 when the initialization flag is received.

The judgment circuit 16 is, for example, a 3-bit comparison circuit. When the count value received from the mismatch flag counter 15 is, for example, 2 or less, a judgment flag indicating that the count value is 2 or less. Output circuit 1
8 is output. The FFH comparison circuit 17 is, for example, 8 bi
The comparison circuit of t is used to compare the reproduction data stored in the 8-bit latch 3 with "FF" (in hexadecimal notation), and output a match flag to the output circuit 18 if they match.

The output circuit 18 is a three-input AND circuit. When an initialization flag is received in a state where the judgment flag and the coincidence flag are received, a detection flag indicating that a synchronization signal has been detected is output through an output terminal C. Output. Hereinafter, the operation of the synchronization signal detection circuit will be described with reference to FIG. Here, at time t _13, indicating the playback data stored in 8bit latch 1-8 in 41 of FIG.

The signal waveform shown in FIG. 2A is a signal waveform of a clock, and the clock is a signal serving as a reference for all operations. The signal waveform shown in FIG. 2B is a signal waveform of a reproduced data transfer timing pulse generated in synchronization with the clock. When the rising of this signal is detected, the 8-bit latches 1 to 8 The received data stored in each 8-bit latch is shifted from the 8-bit latch 8 to the 8-bit latch 7, from the 8-bit latch 7 to the 8-bit latch 6,...

The signal waveform shown in FIG. 2 (c) is a signal waveform of a latch signal generated in synchronization with a reproduction data transfer timing pulse. When the 8-bit latches 1 to 8 receive the latch signal, they perform reproduction after shifting. Store the data. Here, the latch signal is input from the input terminal A. FIG.
The signal waveform (d), the indicated reproduction data inputted from the input terminal B, in the figure, at time t _13, each 8bi
This indicates that the reproduction data stored in the t latches 1 to 8 is updated.

The waveform shown in FIG. 2 (e) is 8CLOCKw
The open / close state of the gate of the window 9 is shown. A high level indicates that the gate is open, and a low level indicates that the gate is closed. The opening / closing is controlled by a reproduction data transfer timing pulse. The signal waveform shown in FIG. 2F shows an output signal for outputting the count value of the 3-bit counter 10. In the figure, the output signal f0 is 0, the output signal f1 is 1,... The signal which has as a count value is shown.

The signal waveform shown in FIG. 2G is a signal waveform of an output signal of the predetermined data of the synchronization signal output from the synchronization signal pattern generation circuit 13. In the figure, a high level signal corresponds to "FF" and a low level signal corresponds to "00". The signal waveform shown in FIG. 2H is the signal waveform of the output signal of the FFH comparison circuit 17. In the figure, when this output signal is at a high level, the result of the comparison by the FFH comparison circuit 17 indicates that the third word of the reproduced data matches "FF" (in hexadecimal notation). A match flag is set.

The signal waveform shown in FIG. 2 (i) is the signal waveform of the initialization signal. Here, the initialization signal at the high level is used as an initialization flag. The signal waveform shown in FIG. 2J is the signal waveform of the output signal of the output circuit 18. When this signal is at a low level, it indicates that a synchronization signal has not been detected, when it is at a high level, it indicates that a synchronization signal has been detected, and a signal at a high level is used as a detection flag. .

[0021] At time t _13, when receiving the latch signal of high level through the input terminal A, 8bit latch 1
8 store reproduction data (see 42 in FIG. 4). At time t _13, the FFH comparator circuit 17 determines whether the third word is "FF", if "FF",
The match flag is transmitted to the output circuit 18. Here, since the third word is “FF”, a match flag is output (see FIG. 2H).

Further, as shown in FIG.
CKwindow 9 opens the gate and responds accordingly.
The bit counter 10 starts counting (FIG. 2 (f)).
Reference), according to the count value of the 3-bit counter 10,
The synchronization signal pattern generation circuit 13 reads out predetermined data of the synchronization signal (see FIG. 2G). At the same time, 3bi
In accordance with the count value received from the t counter 10, the 8-word selector 12 reads out one of the 8-bit latches 1 to 8 to read out stored reproduction data, and outputs the reproduction data to the comparison circuit 14. At time t _13, since the count value received from 3bit counter 10 is 0, the synchronization signal pattern generating circuit 13 reads out the synchronous signals prescribed data corresponding to the count value "0" to "00", the comparison circuit 14 Output. At time t _13, since the count value received from 3bit counter 10 is 0, reproduced from 8bit latch 1 corresponding to the count value "0" data "00" is read out.

[0023] Here, at time t _13, since the reproduction data read out from the 8bit latch 1 is "00", the comparator circuit 14 does not transmit the mismatch flag to the mismatch flag counter. The same operation up to time t _20, mismatch flag counter 15 counts the mismatch flag received from the comparator circuit 14, determines the count value circuit 16
Send to

The determination circuit 16 includes a mismatch flag counter 1
When the count value is received from 5, it is determined whether the count value is 2 or less. If the count value is 2 or less, a determination flag is output to the output circuit 18. Here, the 8-bit counters 1 to
Stored reproduced data 2 is "00", since the reproduction data stored in the 8bit counter 3-8 is "FF", at time t _20, since the count value is 0, the determination circuit 16 determines Output flags.

[0025] At time t ₂₀ is the signal shown in f7 in FIG. 2 (f), the next count value is 7 3bit counter 10, the initialization circuit 11, as shown in FIG. 2 (i), the initialization Set the flag to the 8CLOCKwindow
9, the 3-bit counter 10, the mismatch flag counter 15, and the output circuit 18. Upon receiving this initialization flag, the 8CLOCK window 9 closes the gate, and the 3-bit counter 10 and the mismatch flag counter 15 set the count value to 0.

Further, the output circuit 18 at time t _20, since receiving a match flag and the determination flag, and outputs a detection flag (see FIG. 2 (j)).

[0027]

As described above, according to the present invention, a synchronization signal in which an error has occurred due to a scratch on a magnetic tape or the like can be detected as a synchronization signal. This makes it possible to detect a synchronization signal including uncorrected data in a data string including a synchronization signal in a data string that has been subjected to a correction process, as in the new standard, and a detection rate of the synchronization signal. Therefore, the practical utility of the present invention is high.

[Brief description of the drawings]

FIG. 1 is a drawing showing a circuit diagram of a synchronization signal detection circuit in an embodiment.

FIG. 2 is a diagram showing a timing at the time of detecting a synchronization signal in the embodiment.

FIG. 3 is a diagram showing predetermined synchronization signal data held by a synchronization signal pattern generation circuit of the synchronization signal detection circuit in the embodiment.

FIG. 4 is a diagram showing data stored in 8-bit latches 1 to 8 in the embodiment.

[Explanation of symbols]

1 to 8 8bit latch 9 8CLOCKwindow 10 3bit counter 11 initializes circuit 12 8-word selector 13 synchronizing signal pattern generating circuit 14 comparison circuit 15 inconsistency flag counter 16 determination circuit 17 FFH comparator circuit 18 8bit latch 1 to the output circuit 41 time t ₁₃ Data stored in 8 f0 to f7 Output signal g0 to g7 Output signal A Input terminal B Input terminal C Output terminal

Claims (1)

(57) [Claims] 1. PCM recorded in a PCM audio recording area
A synchronization signal detection circuit for detecting a synchronization signal consisting of M words in the still image data, a predetermined data generation means for generating predetermined data which is predetermined data for each word constituting the synchronization signal, and receiving PCM still image data Receiving means for receiving the PCM still image data received by the receiving means; and reading the data of M words in a continuous receiving order from the data holding means and comparing with the predetermined data in the corresponding order. Means, counting means for counting the number of words which do not match the predetermined data among the comparison results of the comparing means for every M words and outputting a count value, and when the count value output by the counting means is equal to or less than a predetermined value. Determining means for determining whether or not there is a signal, and outputting a determination flag when the value is equal to or less than a predetermined value; A specific word determining means for determining whether the Nth word in the word matches the predetermined data in the corresponding order and outputting a match flag when matching, receiving a determination flag from the determining means, A synchronization signal detection circuit comprising: a synchronization signal determination unit configured to determine the data of the M words as a synchronization signal when receiving a match flag from the specific word determination unit.