JPH0727696B2 - Burst error detector for digital signals - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst error detection device for a digital signal, which detects a burst error generated during signal reproduction in a digital video tape recorder, for example.

[Conventional technology]

2. Description of the Related Art Conventionally, a digital video tape recorder (hereinafter referred to as a digital VTR) that converts, for example, a video signal into a digital amount and performs recording and reproduction on a magnetic tape is generally known. In this digital VTR, an error (code error) may occur in a data bit of a reproduced digital video signal due to a defect of a magnetic tape or a level fluctuation of a reproduced signal. The above errors are roughly classified into so-called random errors and burst errors. The former is a discrete error with a relatively short period, and the latter is a continuous error with a long period.

Detecting such an error is very important for taking measures against the error. As a method of detecting an error, for example, a method using CRCC (cyclic code) is known, in which an inspection bit is added to a data bit for recording, and the error is detected by checking the inspection bit during reproduction. It has become so.

[Problems to be solved by the invention]

By the way, in the error detection method by CRCC as described above, if even one bit in the check bit is different from the predetermined bit, it is detected as an error, so that not only burst error but also random error is detected. . Therefore, it is unsuitable when only burst errors are detected and error countermeasures are taken. In addition, it is necessary to add the check bit to the data bit, which causes a problem that the bit redundancy increases.

Therefore, the present invention has been proposed in view of the above-described conventional problems, and among the errors that occur in the data bits of the input digital signal, random errors cannot be detected, and only burst errors can be detected. An object is to provide a burst error detection device for digital signals. Another object of the present invention is to provide a burst error detecting apparatus for a digital signal which can detect burst errors without adding check bits to data bits.

[Means for solving problems]

In order to achieve the above object, a burst error detecting apparatus for a digital signal according to the present invention has a pattern detecting means for detecting a fixed pattern of input data, and a pulse generating means for outputting a pulse having a constant cycle based on the fixed pattern. A data extracting means for extracting data corresponding to the fixed pattern from the input data according to a pulse output timing from the pulse generating means, a pattern of data extracted by the data extracting means, and the fixed pattern. And an error amount detecting means for detecting an error amount of the data and a burst error determining means for determining a burst error when the error amount is equal to or more than a predetermined number of bits and outputting a burst error determination pulse. It is characterized by being formed.

[Work]

According to the present invention, the data extraction means extracts data corresponding to the fixed pattern in the input data, and the burst error determination means determines whether or not there is a burst error based on the error amount of the extracted data. Done.

〔Example〕

An embodiment of a digital signal burst error detecting apparatus according to the present invention will be described below in detail with reference to the drawings. In this embodiment, the present invention is applied to a burst error detecting device in a digital VTR.

Hereinafter, description will be given with reference to the block diagram of FIG. 1 and the time chart of FIG. The digital video signal S _VD supplied to the signal input terminal 1 during reproduction includes an image data group D _PI representing an image signal in a predetermined range on the screen and the image data group D _PI located in front of the image data group D _PI. Repeating cycle T in units of one block consisting of address data D _AD that represents address information related to _PI and synchronization signal data D _SY that is located in front of this address data D _AD and that represents a synchronization signal.
_{It is} a continuous signal of _VD . Where the sync signal data
D _SY is data of a fixed pattern arranged at a predetermined position in one block, and is composed of 16 bits, for example.

The sync signal detection circuit 2 detects the sync signal data D _SY in the supplied digital video signal S _{VD and} detects a sync detection pulse.
_PSY is output. The detection of the sync signal data D _SY may store data having the same pattern as the predetermined bit pattern of the synchronizing signal data D _SY advance the synchronizing signal detection circuit 2, a video signal S _VD sequentially incoming This is performed by constantly comparing with the reference sync signal pattern, and when the two patterns match, the sync detection pulse P _SY is output. As the synchronizing signal detecting circuit 2, for example, a synchronizing signal extracting circuit as described in the specification of Japanese Patent Application No. 58-249281 previously proposed by the applicant of the present application may be used.

If an error occurs in the bit of the sync signal data _{SY in} the supplied digital video signal S _VD , the pattern of the sync signal data D _SY does not match the above-mentioned reference sync signal pattern. The pulse P _SY is not output. That is, in FIG. 2, the synchronization signal data D
_SY that places the synchronization detection pulse P _SY despite there is no there is for this.

Sync detection pulse P _SY output from sync signal detection circuit 2
Is sent to the pulse generation circuit 3. This pulse generation circuit 3
Is composed of, for example, a PLL (Phase Locked Loop), and a synchronization pulse P ₀ having a constant repetition period T ₀ synchronized with the synchronization detection pulse P _SY is generated and output from the synchronization pulse output terminal 4. The repetition cycle T ₀ is set equal to the repetition period T _VD of the digital video signal S _VD . The sync pulse P ₀ is fed back to the sync signal detection circuit 2 and is also sent to the data extraction circuit 5 to which the digital video signal S _VD is supplied. In the data extraction circuit 5, the sync signal data D in the digital video signal S _VD is received in accordance with the timing of the sync pulse P _0.
SY is extracted. The extracted synchronization signal data D _SY is sent to the error amount detection circuit 6, the bit error amount is detected, and error amount detection data D _ER representing the error amount is output. To detect the error amount, data having the same pattern as the predetermined bit pattern of the synchronization signal data D _SY is stored in the error amount detection circuit 6 in advance, and the pattern of the synchronization signal data D _SY that sequentially arrives is used as the reference. It is performed by comparing with the sync signal pattern of. As a result, as schematically shown in FIG. 2, the error amount of each data D _SY is, for example, 0 bit, 2 bits, 0 bit, 5 bits, 8 bits, in order.
... is detected.

Then, the error amount detection data D _ER from the error amount detection circuit 6 is sent to the burst error determination circuit 7 and it is determined whether or not there is a burst error. That is, the threshold value is set to, for example, 3 bits, and if the error amount is 3 bits or more, it is determined to be a burst error,
The burst error determination pulse P _BU is output from the burst error detection terminal 8. At this time, one block including the sync signal data D _SY which is determined to be a burst error and the previous one block, that is, a total of two blocks of data, are regarded as a burst error, and the burst error determination pulse P _BU Is output with a pulse width corresponding to the period of the above two blocks. In the case of the present embodiment, as shown in FIG. 2, each data D _SY having an error amount of 5 bits and 8 bits is continuously determined to be a burst error, and a total of 3 blocks of data are burst errors. Is considered to be. Therefore, the burst error determination pulse P _BU is output with a pulse width W corresponding to the period of the above three blocks. The burst error determination pulse P _BU originally corresponds to the period of 3 blocks as shown by the broken line, but is actually output with a delay of one cycle T _VD (T ₀ ). .

Thus, in the burst error detection device of this embodiment,
Sync signal data D _SY existing in digital video signal S _VD
Is extracted to detect a burst error. Therefore, it is not necessary to add check bits to the data bits as in the conventional case, and the bit redundancy does not increase due to error detection. Further, since the judgment of whether or not it is a burst error is made by setting a threshold value of an error amount of 3 bits in this embodiment, a random error is hardly detected and only a burst error is detected. Can be detected. This is because it is possible to judge that an error occurs in 3 or more bits out of 16 bits of the synchronization signal data D _{SY as} a burst error.

The present invention is not limited to the above-described embodiment, but can be widely used for detecting a burst error of a digital signal including data having a fixed bit pattern.

〔The invention's effect〕

As is clear from the above description of the embodiments, the apparatus for detecting a Barts error of a digital signal according to the present invention extracts data corresponding to a fixed pattern in an input digital signal to detect a burst error. ing. Therefore, it is not necessary to add the check bit to the data bit as in the conventional case, and the burst error can be detected without increasing the bit redundancy. In addition, the amount of error that occurs in the bits of the data corresponding to the fixed pattern is
Since it is determined whether or not there is a burst error by determining whether or not the number of bits is equal to or more than a predetermined number of bits set as an appropriate threshold value, a random error is rarely detected, and a burst error is rarely detected. Only can be detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital signal burst error detection apparatus according to the present invention, and FIG. 2 is a time chart showing the operation of the burst error detection apparatus of the above embodiment. 2 ... Synchronization signal detection circuit, 3 ... Pulse generation circuit 5 ... Data extraction circuit, 6 ... Error amount detection circuit 7 ... Burst error determination circuit

Claims (1)

[Claims] 1. A pattern detecting means for detecting a fixed pattern of input data, a pulse generating means for outputting a pulse of a constant cycle based on the fixed pattern, and the pulse generating means for outputting the pulse according to the output timing of the pulse. Data extracting means for extracting data corresponding to the fixed pattern from the input data, and error amount detecting means for comparing the pattern of the data extracted by the data extracting means with the fixed pattern to detect the error amount of the data. A burst error determination means for determining a burst error when the error amount is equal to or larger than a predetermined number of bits and outputting a burst error determination pulse.