JPS61137286A - Burst error detector of digital signal - Google Patents

Abstract

PURPOSE:To detect only a burst error by providing the titled device with a data extracting means for extracting data corresponding to a fixed pattern from input data in accordance with the output timing of a pulse obtained from a pulse generating means and an error volume detecting means for detecting the volume of the error of the data. CONSTITUTION:A synchronization detection pulse PSY outputted from a synchronizing signal detecting circuit 2 is sent to a pulse generating circuit 3 and the circuit 3 generates a synchronization detecting pulse P0 having a fixed repeating period synchronized with the synchronization detecting pulse PSY and outputs the pulse P0 from a synchronizing pulse output terminal 4. The pulse P0 is fed back to the circuit 2 and also sent to a data extracting circuit 5 to which a digital video signal SVD is supplied. The circuit 5 extracts synchronizing signal data DSY included in the video signal SVD in accordance with the timing of the pulse P0. The extracted data DSY is sent to an error amount detecting circuit 6 to detect the amount of bit error and error amount detecting data DER indicating the amount of error are outputted.

Description

[Detailed Description of the Invention] Industrial Field of Application] The present invention is applicable to digital video tape recorders, for example.
The present invention relates to a digital signal burst error detection device for detecting burst errors occurring during signal reproduction.

BACKGROUND ART Conventionally, digital video tape recorders (hereinafter referred to as digital VTRs), which convert video signals into digital signals and record and reproduce them on magnetic tape, have been generally known. In this digital VTR, errors (code errors) may occur in the data bits of the reproduced digital video signal due to defects in the magnetic tape or fluctuations in the level of the reproduced signal. The above errors are broadly classified into so-called random errors and birth I-errors, and the former are discrete errors with a relatively short period.
The latter is a long-term continuous error. □Detecting such errors is extremely important in order to take countermeasures against them. One method of error detection is, for example, a method based on 4CC (cyclic code), in which a test bit is added to data bits for recording, and the test bits are checked during playback. Errors are now detected.

[Problem that the invention seeks to solve]

By the way, in the error detection method using c n, c c as described above, if there is even one bit in the test hit that differs from the predetermined bit, it will be detected as an error, so not only burst errors but also random errors are detected. It will be detected. For this reason, it is not suitable for cases where only burst errors are detected and error countermeasures are taken. Furthermore, there is a problem in that a check hint must be added to the disk hit, which increases the redundancy of bits.

Therefore, the present invention was proposed in view of the above-mentioned conventional problems, and provides a digital signal that can detect only burst errors, but not random errors, among errors that occur in the take-hit of input digital signals. An object of the present invention is to provide a signal burst error detection device. Another object of the present invention is to provide a digital signal burst I error detection device that can detect burst errors without adding test hits to take hits.

[Means for resolving the gap]

In order to achieve the above-mentioned object, the digital signal burst error detection and output device according to the present invention includes a pattern detection means for detecting a fixed pattern of an input take, and a pulse outputting device for outputting a pulse with a constant period based on the fixed pattern. generating means; data extracting means for extracting a take corresponding to the fixed pattern from the input catheter according to the output timing of the pulse from the pulse generating means; It is characterized by comprising an error amount detection means for detecting the error amount of the data by comparing it with a pattern, and a burst error determination means for determining a burst error based on the error amount.

[Operation] According to the present invention, the take extracting means extracts a take corresponding to a fixed pattern in the input takes, and the burst error determining means determines whether or not it is a burst error based on the error amount of the extracted take. A judgment is made.

〔Example〕

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, one embodiment of a digital signal signal burst I/error detection device according to the present invention will be described in detail with reference to the drawings. Note that in this embodiment, the present invention is applied to a digital V T
This is applied to a burst error detection device in R.

Below are the block diagram in Figure 1 and the Guimchart in Figure 2.
This will be explained with reference to 1. Signal input terminal 1 during playback
The digital hiteo signal Svn supplied to the
an image take group Dpr representing image signals in a predetermined range; and an image data group 1 located in front of this image data group DpT.
) Address data D representing address information related to pr
This is a continuous signal with a repetition period Tvn in units of one block, which is composed of AD and a synchronization signal take l')sy located in front of this address data [)A11 and representing a synchronization signal. Here, the above synchronization signal take I)sy is 1
This is fixed pattern data placed at a predetermined position in a block, and is composed of 6 bits (for example, 4-6 bits).

The synchronization signal detection circuit 2 detects synchronization signal data Dsy in the supplied digital video signal Svo and outputs a synchronization detection pulse Psy. This synchronization signal take Dsy
is detected by storing in advance in the synchronization signal detection circuit 2 a take having the same predetermined bit pattern as the predetermined bit pattern of the synchronization signal data DSY, and then detecting the video signal 5 that arrives sequentially.
vI) with the reference synchronization signal pattern, and when the two patterns match, a synchronization detection pulse PSY is output. As the synchronization signal detection circuit 2, for example, a synchronization signal extraction circuit as described in Japanese Patent Application No. 58-249281, Mei #I, previously proposed by the applicant of the present invention may be used.

Furthermore, if an error occurs in the synchronization signal data Dsy in the supplied digital video signal SVD, the pattern of the synchronization signal take Dsy will no longer match the reference synchronization signal pattern, so the synchronization detection pulse Ps
y is not output. That is, in FIG. 2, even though the synchronization signal data DSY exists, the synchronization detection pulse P
This is why there are places where SY does not exist.

The synchronization detection pulse Psyi output from the jtll signal detection circuit 2 is sent to the opulse generation circuit 3. This pulse generating circuit 3 has, for example, P, I, L(Pl]ase
I/)C-ked Loop), -
A synchronization pulse Po having a constant repetition period To in synchronization with the synchronization detection pulse PSY is generated and output from the synchronization pulse output terminal 4. 2. The above repetition period T.

is the repetition period Tvn of the digital video signal SVD
is set equal to . Also, this synchronization pulse Po
is fed back to the synchronization signal detection circuit 2, and the take extraction circuit 5 is supplied with the digital video signal SVD.
sent to. The take 44A1 output circuit 5 extracts the synchronizing signal DSY from the digital hito signal SVI'1 in accordance with the timing of the synchronizing pulse Po.

The extracted synchronization signal data 1) sy is sent to the error amount detection circuit 6, the bit error amount is detected, and error amount detection data I) ER representing the error amount is output. This error amount detection is carried out by storing a predetermined pattern of the synchronization signal take Dsy in advance in the error amount detection circuit 6, and detecting the pattern of the synchronization signal take DsY that will arrive next. This is done by comparing with the reference synchronization signal pattern. As a result, as schematically shown in FIG. 2, the error t of each take DSY is
For example, the following sequence (0 hits, 2 hits, 0 bits, 5 hits, 8 bits, . . . ) is detected.

The error amount detection data DER from the error amount detection circuit 6 is sent to the burst error determination circuit 7, and it is determined whether or not it is a burst error. That is, the threshold value is set to 3 hits, for example, and if the error amount is 3 hits or more, it is determined that there is a burst error, and a burst error determination pulse Pnu is output from the burst error detection terminal 8. . At this time, the block containing the synchronization signal take Dsy that was determined to be a burst error, and the previous one block, a total of 2 blocks of takes, are considered to be burst errors, and Saturday/Sunday self-buff - one burst error. The determination pulse PR1l is output with a pulse width corresponding to the period of the two blocks. In the case of this embodiment, as shown in FIG. 2, each take I)sy with an error amount of 5 bits and 8 bits I) is determined to be a burst error consecutively, and a total of 3 blocks worth of data is is considered to be a burst error.

Therefore, the burst error determination pulse PHI is output with a pulse width W corresponding to the period of the three blocks. old,
The burst error determination pulse PBU originally corresponds to a three-block period as shown by the broken line, but it is actually output with a delay of one cycle Tvn (To).

In this way, in the burst error detection device of this embodiment,
Synchronous signal data 1)sY present in the digital video signal Svn is extracted to detect burst errors. Therefore, there is no need to add check bits to the data bits as in the past, and the redundancy of bits does not increase due to error detection. In addition, in this embodiment, the determination of whether or not it is a burst error is made by setting a threshold of 3 bits of error, so random errors are almost never detected, and only burst errors are detected. can be detected. This is because if an error occurs in 3 or more out of 6 bits of synchronization signal take Dsy(7-), it can be determined to be a burst error.

2. The present invention is not limited to the above-described embodiments, and can be widely used for detecting burst errors in digital signals including takes having a fixed pit pattern.

〔Effect of the invention〕

As is clear from the description of the embodiments described above, the digital signal part error detection device according to the present invention detects burst errors by extracting data corresponding to a fixed pattern in the input digital signal. ing. For this reason, there is no need to add the test history I to the take pic I as in the prior art, and burst errors can be detected without increasing the redundancy of bits. In addition, since a suitable threshold is set for the amount of errors that occur in the pits of data corresponding to the fixed pattern to determine whether or not it is a burst error, there is no chance that a rank error will be detected. There are almost no errors, and only burst errors can be detected.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital signal burst error detection device according to the present invention, and FIG. 2 is a time chart showing the operation of the burst error detection device of the above embodiment.

Claims (1)

[Claims] a pattern detection means for detecting a fixed pattern of input data; a pulse generation means for outputting a pulse of a constant period based on the fixed pattern; a data extraction means for extracting data corresponding to the pattern; an error amount detection means for comparing the data pattern extracted by the data extraction means with the fixed pattern and detecting the amount of error in the data; A burst error detection device for a digital signal, comprising: burst error determination means for determining a burst error based on the burst error determination means.