KR0178724B1 - Apparatus for measuring a bit rate in the digital image signal recording and reproducing apparatus - Google Patents

Abstract

The present invention relates to a bit error rate measuring apparatus of a digital video signal recording and reproducing apparatus capable of measuring in real time whether or not reproduced data faithfully restores recorded data. The present invention delays the recording data output from the signal generator during reproduction for a predetermined time. As another example, the ID decoder and the initial address generator change the initial address value of the ROM to generate recording data such as the currently reproduced sync block number, and delay the reproduction data for a predetermined time in the delay unit. The first and second flip flops using a common clock signal are used to synchronize the reproduction data with the recording data. The error comparison and counting unit compares the output data of the first and second flip flops for each bit to detect an error and counts the number of detected errors by one track. Therefore, the bit error rate measuring device can be configured with a simple combination of hardware and low cost, and the number of errors can be counted even when some sync blocks are lost.

Description

Bit error rate measuring device of digital video signal recording and reproducing device

1 is a block diagram showing a bit error rate measuring apparatus in a conventional digital communication system.

2 is a block diagram showing a block configuration of a bit error rate measuring apparatus in a digital video signal recording and reproducing apparatus according to the present invention.

3 is a circuit diagram showing the internal configuration of the comparator of FIG.

4 is a circuit diagram showing the internal configuration of the signal generator of FIG.

(A)-(i) of FIG. 5 are the input / output signal waveforms of each part of FIG.

6 is a configuration diagram of a sync block recorded or reproduced in a digital video signal recording and reproducing apparatus.

7 is a data structure for recording on one track in a digital video signal recording and reproducing apparatus.

8 is another exemplary block diagram showing a block configuration of a bit error rate measuring apparatus in a digital video signal recording and reproducing apparatus according to the present invention.

9 (a) to 9 (e) are timing diagrams of input / output signals of respective parts of FIG.

* Explanation of symbols for main parts of the drawings

11,15,24,85: Signal generator 16,25,86: Delay

26,27,33,41,87,88: flip flop 28,29: error comparison and counting unit

31: Exclusive Oagate 81: Sync Signal Detector

83: derandomizer 85B: address controller

85A: ID Decoder and Initial Address Generator

85C: ROM 90: Display drive unit

The present invention relates to performance measurement of a digital video signal recording and reproducing apparatus, and more particularly to a bit error rate measuring apparatus of a digital video signal recording and reproducing apparatus capable of measuring in real time a bit error rate indicating whether or not a reproduced signal is decoded faithfully. It is about.

Currently, video signal recording and reproducing apparatus is undergoing a process of transition from analog equipment to digital equipment. The reason for developing the digital video signal recording and reproducing apparatus as described above is that it has the advantage of obtaining high quality image quality and the deterioration of image quality even after repeated dubbing several times. In developing such a digital video signal recording and reproducing apparatus, it is necessary to measure a bit error rate (BER) indicating how faithfully the reproduced signal restores the recorded signal. The reason is that the bit error rate can be used as a measure of the stability of the device.

1 is a block diagram showing the configuration of a bit error rate measuring apparatus in a conventional digital communication system. In Fig. 1, reference numerals 11 and 15 are signal generators, which make the signals to be transmitted in the communication system the same on the transmitting side and the receiving side. The signal generated by the signal generator 11 is transmitted to the transmitter 12, and the transmitter 12 encodes the input signal and transmits the encoded signal to the receiver through the transmission line 13.

The signal transmitted through the transmission line 13 is received by the receiver 14, and the receiver 14 decodes the transmitted signal and transmits it to the comparator and the counter 17. On the other hand, the signal generator 15 for generating the same signal as the signal generated on the transmission side, and the delay terminal 16 is connected to the output terminal, the signal generated by the signal generator 15 from the transmitter 12 to the receiver 14 Delay by the time taken by the transmission line 13 to The comparator and counter 17 connected to the output of the delayer 16 compare the signal decoded at the receiver 14 with the signal delayed at the delayer 16 and counts the number of errors.

In the bit error rate measuring apparatus configured as described above, the signal generator 11 supplies the promised signal to the transmitter 12, and the transmitter 12 performs a predetermined encoding on the input transmission signal and transmits it to the receiver 14. In this case, a specific transmission time is required in the transmission line 13 from the transmitter 12 to the receiver 14. In order to detect an error on the receiving side, the signal output from the signal generator 15 must be delayed by the transmission time in the transmission line 13. When the signal output from the delay unit 16 is supplied to the comparator and the counter 17, the error is detected here by comparison with the signal decoded by the receiver 14 and the number of detected errors is counted.

Since the conventional technology operated as described above is a technique applied to a digital communication system, a constant delay time is required for transmission from a transmitting side to a receiving side. However, in the case of the digital video signal recording and reproducing apparatus, the delay time is not constant because the recording and reproducing is performed using a medium called tape instead of using the transmission line. In other words, since the playback starts from the moment the user presses the play button, the delay time is arbitrarily changed. Therefore, there has been a problem that it is impossible to apply the bit error rate measuring method in the digital communication system to the digital video signal recording and reproducing apparatus.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to detect an error by comparing a reproduced signal with a recorded signal, and count and reproduce the digital video signal recording count by counting the number of errors during one track length. An object of the present invention is to provide a bit error rate measuring apparatus for a digital video signal recording and reproducing apparatus capable of measuring the performance of the apparatus.

Another object of the present invention is a bit error rate of a digital video signal recording / reproducing apparatus which can count the number of errors by decoding the ID signal and accurately matching the playback time and the recording data even when the sync block in front of the track is lost. To provide a measuring device.

In the digital video signal recording and reproducing apparatus of the present invention for achieving the above objects, the bit error rate measuring apparatus receives the detected synchronization signal, the head switching signal and the clock signal of the reproducing decoder, and the same as they are recorded and reproduced. A signal generator for generating data for tracks is provided. The delay unit connected to the output of the derandomizer or the signal generator delays the recording data of the reproduction data or the signal generator by a predetermined time in order to meet the point of comparison between the reproduction data and the recording data.

The first and second flip flops receive the reproduction data and the recording data, respectively, and use the reproduction clock signal as a common clock signal to synchronize the two input data. An error comparison and counting unit is connected to the output terminals of the first and second flip flops, and the output data of the two flip flops is compared for each bit according to the reproduction clock signal to detect an error and count the number of detected errors by one track. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 through 9.

2 is a block diagram showing the configuration of a bit error rate measuring apparatus in a digital video signal recording and reproducing apparatus according to one embodiment of the present invention. In FIG. 2, the A block is a part belonging to the digital video signal recording and reproducing apparatus, and the B block is the bit error rate measuring apparatus of the present invention. The block A includes a recording encoder 21 for encoding the data to be recorded and recording it on the tape 22, and a reproduction decoder 23 for decoding the data reproduced on the tape 22 and outputting the decoded data to the bit error rate measuring device B. Included.

The bit error rate measuring apparatus B according to the present invention supplies data for one track to be recorded in accordance with the recording enable signal REC-EN of the recording encoder 21 to the recording encoder 21, and reproduces and decodes the data. According to the playback enable signal PB-EN, the same data as that of the recording is repeatedly generated, and the head switching signal HD-SW and the clock signal CLK of the playback decoder 23 are generated. And a signal generator 24 for generating the set signal RST. A delay unit 25 and a counter 28B are connected to an output terminal of the signal generator 24, and the delay unit 25 signals one track of data output from the signal generator 24 by the reproduction decoder 23. Delay by the time required for processing.

The recording data for one track output from the delay unit 25 is applied to the second flip flop 27, and the playback data for one track output from the reproduction decoder 23 is supplied to the first flip flop 26. Is input. The first and second flip flops 26 and 27 output data in accordance with the clock signal CLK output from the reproduction decoder 23 so as to synchronize the two input data. An error comparison and counting unit 28 composed of a comparator 28A and a counter 28B is connected to the output terminals of the first and second flip flops 26 and 27.

The comparator 28A receives the clock signal CLK of the reproduction decoder 23 and compares the output data of the two flip flops 26 and 27 for each bit, thereby not restoring the signal recorded by the reproduced signal as it is. Detect. A counter 28B is connected to the output terminal of the comparator 28A to count the number of errors detected by the comparator 28A, and is reset every time the reset signal RST of the signal generator 24 is input. Count the number of errors.

In the bit error rate measuring apparatus configured as described above, when the signal generator 24 receives the high-potential recording enable signal REC-EN from the recording encoder 21, the signal generator 24 generates data for one track to be recorded and generates a recording encoder ( 21). The recording encoder 21 performs predetermined encoding on the input n-bit recording data and records it on the tape 22 while the recording enable signal REC-EN has a high potential. When the user presses the play button, the play decoder 23 supplies the play enable signal PB-EN, the clock signal CLK, the head switching signal HD-SW, and the like to the signal generator 24, The clock signal CLK is also supplied to the first and second flip flops 26 and 27 and the comparator 28A.

The reproduction decoder 23 decodes the data reproduced from the tape 22 and transmits it to the first flip flop 26 while the reproduction enable signal PB-EN has a high potential. At this time, the signal generator 24 detects the edge of the head switching signal HD-SW when the high potential regeneration enable signal PB-EN is input from the reproducing decoder 23, and is the same as when recording. After repeating generation of data for one track, this data is output to the delay unit 25. The delay unit 25 delays the input data by the clock required for signal processing by the reproduction decoder 23 so as to synchronize the input n-bit data with the n-bit data reproduced by the reproduction decoder 23. Transfer to the second flip flop (27).

Here, n bit data input to the first and second flip flops 26 and 27 are shown in (a) and (b) of FIG. As shown in (a) of FIG. 5, the reproduced data has a jitter component due to tape skew and the like, so that the reproduced data and the recorded data (see (b) of FIG. 5) are not synchronized with each other. Will not.

The first and second flip-flops 26 and 2 flip the flip-flops 26 to the clock signal CLK (see (c) of FIG. 5) output from the reproduction decoder 23 in order to synchronize the two input data. It is used as a common clock signal of (). Therefore, the n-bit data output from the two flip-flops 26 and 27 coincide with the transition points as shown in (d) (e) of FIG. The comparator 28A compares the playback data and the recording data synchronized by the flip flops 26 and 27 for each bit to detect an error.

3 is a circuit diagram showing an internal configuration of the comparator 28A. As illustrated, the comparator includes an exclusive OR gate that receives logically the reproduction data output from the first flip flop 26 and the recording data output from the second flip flop 27 in units of bits. 31 is provided by the number of bits n. The exclusive OA gate 31 outputs 0 when the two input bits are the same and 1 when the input bits are the same, and therefore outputs a high potential signal 1 when there is an error.

The output terminal of the exclusive oragate 31 is connected to the oragate 32, and even if only one bit of the n-bit data has an error, it is determined that the n-bit data is different from the original signal and outputs a high potential signal. The flip-flop 33 at the rear end of the oragate 32 delays the output data of the oragate 32 in accordance with the clock signal CLK output from the reproduction decoder 23, and outputs it in a stable state. The AND gate 34 multiplies the error signal output from the flip-flop 33 and the clock signal CLK of the reproduction decoder 23 and outputs the result to the clock terminal of the counter 28B. To increase.

When the original data recorded by the comparator 28A and the reproduced data are detected in this manner and an error is detected, the counter 28B counts the number of errors detected by the comparator 28A by one track. At this time, in order to count the error by one track, the counter 28B is reset every time the low potential reset signal RST output from the signal generator 24 is input.

4 is a circuit diagram showing the internal structure of the signal generator 24, and shows only the circuit of the part which generates the reset signal RST. As shown, when the head switching signal HD-SW (see (f) in FIG. 5) and the clock signal CLK (see (h) in FIG. 5) are input from the reproduction decoder 23, the head switching signal ( The HD-SW is input to the input terminal D of the flip flop 41 and the exclusive noar gate 42, and the clock signal CLK is input to the clock signal CLK of the flip flop 41. .

The flip flop 41 delays the input head switching signal HD-SW by one clock as shown in (g) of FIG. 5 and outputs the result to the exclusive noar gate 42. The exclusive noar gate 42 compares the original head switching signal HD-SW with the head switching signal delayed by the flip flop 41, and outputs '1' when they are the same and 0 when they are different. Therefore, as shown in FIG. 5 (i), it is possible to obtain the reset signal RST at which the low potential is output at the edge (rising or falling) of the head switching signal HD-SW.

The number of errors in the track unit output from the counter 28b is recorded in the memory or displayed on the display device. At this time, the number of errors in a large amount of time can be recorded in a small memory by recording at the end of the track. Therefore, the number of errors for a desired time can be recorded or displayed, and the average error rate can be measured.

6 is a configuration diagram of a sync block (SB) recorded or reproduced in a digital video signal recording and reproducing apparatus. As shown, one sync block consists of M words (M x N bits) when one word is N bits. The sync block is composed of a sync signal 61, an ID signal 62 representing a sync block number, a track number, and the like, and data 63 composed of a video and audio signal, an error correction additional signal, and the like.

FIG. 7 is a data configuration diagram in which a digital video signal recording / reproducing apparatus records on one track, in which data of one track is composed of q sync blocks (SBs). At this time, the ID signal included in each sync block informs the current sync block number. The ID signal of the first sync block 71 indicates that the first sync block number is 0, and the second sync block 72 indicates that the ID signal is 1 on the second sync block number. Also in the remaining sync blocks 73 to q, it can be seen that each sync block number sequentially changes from 2 to q-1 according to the ID signal.

In this way, the sync blocks for one track are recorded in the sync block number order. However, according to the embodiment of the present invention described above, even when the synchronization block in front of the track is damaged in the data reproduced by the reproduction decoder, the recording data of the signal generator is output in a state including the damaged synchronization block. Therefore, when comparing the recorded data with the reproduced data in the comparator, there is a disadvantage in that data having the same sync block number cannot be compared. As a result, data other than the corrupted sync block may be determined and counted as an error even though it is not actually an error.

FIG. 8 is a block diagram of a bit error rate measuring apparatus of a digital video signal recording and reproducing apparatus according to another embodiment of the present invention, and shows another embodiment in which the shortcomings of the embodiment of FIG. In Fig. 8, block A is a part of blocks belonging to the reproduction system of the digital video signal recording and reproducing apparatus, and block B is the bit error rate measuring apparatus of the present invention. The block A includes a synchronization signal detector 81 which detects a synchronization signal and an ID signal from reproduction data input from a reproduction equalizer (not shown) and outputs the synchronization signal and the ID signal to the ID decoder and the initial address generator 85A.

The serial reproduction data passing through the synchronization signal detector 81 is applied to the serial-parallel converter 82 and converted into a parallel data form. The derandomizer 83 connected to the output of the serial-to-parallel converter 82 restores the input data mixed with each other by a certain rule back to the original data array so that errors are not concentrated in encoding. The parallel reproduction data output from the derandomizer 83 is applied to the error correction decoder 84, the ID decoder, the initial address generator 85A, and the delay 86, respectively. The error correction decoder 84 demodulates the parallel reproduction data and performs error detection, correction, and interpolation by the error correction additional signal, and outputs the decoded parallel reproduction data.

The bit error rate measuring apparatus B of the present invention includes an ID decoder and an initial address generator 85A, a signal generator 85 composed of an address controller 85B and a ROM 85C. The ID decoder and the initial address generator 85A receive the output data and the reproduction clock signal CLK of the sync signal detector 81 and the derandomizer 83, decode the ID signal, and initialize the initial signal according to the currently input sync block number. Change the address value. The initial address value output from the ID decoder and the initial address generator 85A is input to the load terminal Load of the address controller 85B.

The address controller 85B controls the reading operation of the recording data by specifying the address of the ROM (ROM) 85C in accordance with the initial address value and the reproduction clock signal CLK, and at this time, writes one track for recording in the ROM 85C. The data is stored. The delay unit 86 connected to the output terminal of the derandomizer 83 delays the parallel reproduction data input according to the reproduction clock signal CLK by the time required for signal processing by the ID decoder and the initial address generator 85A. The playback data for one track output from the delay unit 86 is applied to the first flip flop 87, and the recording data for one track read out from the ROM 85C is input to the second flip flop 88. do.

The first and second flip flops 87 and 88 output data in accordance with the reproduction clock signal CLK in order to synchronize the two input data. The error comparison and counting unit 89 connected to the output terminals of the first and second flip flops 87 and 88 receives the reproduction clock signal CLK and the head switching signal HD-SW, and the two flip flops 87 By comparing the output data of (88) for each bit, an error is detected and the number of detected errors is counted by one track. The number of errors output from the error comparison and counting unit 89 is input to the display device driver 90, and the display device driver 90 controls the driving of the display device 91 according to the number of errors to determine the number of errors. To check.

The operation of the bit error rate measuring apparatus configured as described above will be described based on the timing diagram of FIG.

In Fig. 8, one track of data stored in the ROM 85C is recorded on a tape and used for bit error rate measurement. When the tape is played back, it is assumed that the first sync block (ID = 0) is damaged and cannot be played, and the second sync block (ID = 1) has been played back. In this case, a case where one sync block has an M word and one word has 8 bits (1 byte) will be described. When the first synchronization signal detected by the synchronization signal detector 81 (see FIG. 9A) and the ID signal are input, the ID decoder and the initial address generator 85A decode the ID signal as a result of decoding the ID signal (FIG. 9B). Note that the first synchronization signal inputted by the reference) is actually the synchronization signal of the second synchronization block.

In this case, in order to properly compare the recorded data with the reproduced data, it is necessary to read from the Mth address of the ROM 85C. To perform this function, the ID decoder and initial address generator 85A output a load value as shown in FIG. 9C to the address controller 85B. The address controller 85B outputs an address signal as shown in (d) of FIG. 9 in accordance with the input load value, and thus changes the initial address value of the ROM 85C so as to read from the second sync block of the stored write data. do.

At this time, the retarder 85 decodes the ID signal, generates a load value, and reproduces the input from the de-randomizer 83 during the time taken until the recording data of the ROM 85C is read out (see (e) in FIG. 9). Delay the data. The reproduction data output from the delay unit 86 is input to the first flip flop 87, and the recording data read out from the ROM 85C is input to the second flip flop 88, wherein the reproduction data is a jitter component. The playback data and recording data are not synchronized with each other.

In the first and second flip flops 87 and 88, the reproduction clock signal CLK is used as a common clock signal of the two flip flops 87 and 88 to synchronize the two input data. The error comparison and counting unit 89 compares the synchronized playback data with the recording data for each bit to detect an error, and counts the number of detected errors by one track for each track using the head switching signal HD-SW. . When the display device driver 90 repeatedly displays the number of errors for the S tracks on the display device 91, the display device driver 90 adds the number of errors by the number of S using the head switching signal HD-SW and adds the value to the display device ( 91 is encoded as a signal for driving.

As described above, the present invention has the effect of finding out the number of errors in real time by comparing and synchronizing the reproduced signal with the recorded signal using the head switching signal, and detecting and displaying errors in track units. In addition, a bit error rate measuring device capable of measuring the performance of a digital video signal recording and reproducing apparatus can be configured with a simple combination of hardware and low cost. In particular, even if the sync block in front of the track is lost, the number of errors can be counted since the ID signal is decoded to precisely match the point of comparison between the playback data and the recording data.

Claims (11)

An apparatus for recording and reproducing a digital video signal, comprising a recording encoder and a reproduction decoder, comprising: receiving a head switching signal and a clock signal of the reproduction decoder, the same predetermined time being recorded on the recording encoder and during reproduction of the reproduction decoder; A signal generator for generating data for tracks; A delay unit for delaying the recording data by the predetermined time in the signal generator in order to meet the point of comparison of reproduction and recording data; First and second flip flops which receive the reproduction data and the recording data, respectively and sequentially output the input data using a common clock signal generated by the recording and reproduction apparatus; And comparing the output data of the first and second flip flops for each bit according to the clock signal to detect an error, and including an error comparison and counting unit for counting the number of detected errors by a predetermined track. Bit error rate measuring apparatus of digital video signal recording and reproducing apparatus. The apparatus of claim 1, wherein the bit error rate measuring device outputs a predetermined track unit output from the error comparison and counting unit to measure an error number and / or an average error rate of a desired time at an output terminal of the error comparing and counting unit. And a memory for recording the number of errors of the digital video signal recording and reproducing apparatus. 2. The signal generator according to claim 1, wherein the signal generator supplies video data of a predetermined track to be recorded every time a record enable signal is input from the record encoder to the record encoder, and a play enable signal is output from the playback decoder. A bit error rate measuring apparatus of a digital video signal recording and reproducing apparatus, characterized by supplying video data for a predetermined track to a retarder each time it is input. The apparatus of claim 1, wherein the delay unit delays the recording data output from the signal generator by the time required for signal processing in the reproduction decoder. 2. The apparatus of claim 1, wherein the signal generator comprises: a flip flop for receiving a head switching signal and a clock signal from the reproduction decoder and delaying the head switching signal by one clock in accordance with the clock signal; And an exclusive oragate for generating a reset signal by comparing the head switching signal output from the reproduction decoder with the output signal of the flip flop. 2. The apparatus of claim 1, wherein the error comparison and counting unit comprises: a comparator for detecting an error by comparing output data of the first and second flip flops for each bit according to a clock signal; And a counter which is reset according to the reset signal output from the signal generator and counts the number of errors detected by the comparator by a predetermined track. 7. The apparatus of claim 6, wherein the comparator comprises: a plurality of exclusive oragates for logically receiving the reproduction data output from the first flip flop and the recording data output from the second flip flop in units of bits; An orifice for ORing signals output from the plurality of exclusive orifices; A flip-flop for delaying an error signal output from the oragate in accordance with a clock signal of a reproduction decoder and outputting the stable signal; And an AND gate for logically multiplying the output signal of the flip-flop and the clock signal of the reproduction decoder to increase the counter upon successive errors. 2. The apparatus of claim 1, wherein the bit error rate measuring device comprises: a display device driver for driving the display device according to the number of errors output from the error comparison and counting unit at an output of the error comparing and counting unit; And a display device for displaying the number of detected errors. The ID generator of claim 1, wherein the signal generator receives an output data from the sync signal detector and a reproduction clock signal of the derandomizer, decodes an ID signal, and changes an initial address value according to a currently input sync block number. A decoder and an initial address generator; An address controller which controls the reading of recorded data by designating an address of a ROM according to the initial address value and a reproduction clock signal; A bit error rate measuring apparatus of a digital video signal recording and reproducing apparatus, comprising: a ROM storing recording data for a predetermined track. 10. The method of claim 9, wherein the ID decoder and the initial address generator decode the ID signal to set an initial address value of a ROM for reading recording data stored in the ROM from a synchronization block such as a currently reproduced synchronization block number. A bit error rate measuring apparatus of a digital video signal recording and reproducing apparatus. 10. The apparatus of claim 9, wherein the delayer delays the playback data output from the derandomizer included in the playback decoder by the time required for signal processing in the ID decoder, the initial address generator, the address controller, and the ROM. Bit error rate measuring apparatus of digital video signal recording and reproducing apparatus.