JPS6390070A - Synchronizing signal detecting system - Google Patents
Synchronizing signal detecting systemInfo
- Publication number
- JPS6390070A JPS6390070A JP61234607A JP23460786A JPS6390070A JP S6390070 A JPS6390070 A JP S6390070A JP 61234607 A JP61234607 A JP 61234607A JP 23460786 A JP23460786 A JP 23460786A JP S6390070 A JPS6390070 A JP S6390070A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- synchronization
- circuit
- synchronization signal
- synchronizing signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims abstract description 9
- 238000001514 detection method Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はディジタル信号の同期信号検出方式に係わり、
特に不連続部分を有するデータの同期信号検出方式に関
する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a synchronization signal detection method for digital signals.
In particular, the present invention relates to a synchronization signal detection method for data having discontinuous portions.
ディジタル信号を伝送又は記録再生するシステムにおい
ては、再生信号から元のデータを復元するためにビット
同期、ワード同期さらにブロック同期を取ることが必須
である。このため、一定周期で同期信号を付加し、再生
時にはこの同期信号を検出することによりワード同期、
ブロック同期を取るといった手段が採用されている。し
かし、伝送中に発生する外乱等釦よりこれらの同期が検
出できない場合にはこのブロックのデータすべて誤りと
なる。この問題に対処するため種々の同期保護の方式が
提案されている。これらの多くは確定した同期信号が得
られた場合、これ以降の同期信号を予測し、もし再生同
期信号が誤まった場合には補間するという考え方である
。In a system for transmitting, recording and reproducing digital signals, it is essential to perform bit synchronization, word synchronization, and block synchronization in order to restore the original data from the reproduced signal. Therefore, by adding a synchronization signal at a fixed period and detecting this synchronization signal during playback, word synchronization and
Measures such as block synchronization are adopted. However, if these synchronizations cannot be detected due to disturbances occurring during transmission, all data in this block will be erroneous. Various synchronization protection schemes have been proposed to deal with this problem. Most of these methods are based on the idea that when a determined synchronization signal is obtained, the subsequent synchronization signal is predicted, and if the reproduced synchronization signal is incorrect, interpolation is performed.
しかし回転ヘッドを使用した装置や、データの伝送が間
欠的に行なわれるシステムにおいては、予測が適用でき
ない最初の同期信号の再生が非常に困難であった。この
ため最初の同期信号の位置を確定させる他の補助手段を
適用する装置が提案され−Ｃいる。例えば特開昭５８−
９４２５４号公報のディジタル信号伝送装置のように最
初のブロックにのみ特定のデータを挿入して先頭ブロッ
クに対する識別能力を向上させる方法が提案されている
。また、特開昭５９−１６８９６１号公報の回転ヘッド
式記録再生装置におけ・る頭出し信号の記録再生方法の
ようにＰＣＭ信号の記録領域とは別個に頭出し信号の記
録領域を設けて特殊な信号を記録する方法などが提案さ
れている。However, in devices using rotating heads or systems in which data transmission is performed intermittently, it is extremely difficult to reproduce the initial synchronization signal for which prediction cannot be applied. For this reason, devices have been proposed which apply other auxiliary means to determine the position of the first synchronization signal. For example, JP-A-58-
A method has been proposed, such as the digital signal transmission device disclosed in Japanese Patent No. 94254, in which specific data is inserted only into the first block to improve the ability to identify the first block. In addition, as in the method for recording and reproducing cue signals in a rotary head type recording and reproducing apparatus disclosed in Japanese Patent Application Laid-Open No. 59-168961, a special recording area for cueing signals is provided separately from the recording area for PCM signals. Several methods have been proposed for recording signals.
しかし、これらの方法は特殊な信号を記録しなければな
らず、ま九その位置に誤りが発生した場合には、同期検
出の誤シが起こるという問題があ゛（３）
つた。However, these methods require recording a special signal, and if an error occurs at that position, there is a problem that an error in synchronization detection will occur (3).
本発明の目的は、特殊な信号を記録できない装置におい
ても、先頭ブロックの同期検出能力を向上できる同期信
号検出方式を供提することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization signal detection method that can improve the synchronization detection ability of a leading block even in an apparatus that cannot record special signals.
本発明は、再生データを同期信号の繰り返し周期Ｔｏの
整数倍だけ遅延し、元の信号と相関をとることによシ同
期信号の検出効率を向上させることを特徴とする。The present invention is characterized in that the detection efficiency of the synchronization signal is improved by delaying the reproduced data by an integral multiple of the repetition period To of the synchronization signal and correlating it with the original signal.
第２図に同期信号（ＳＹ）を含むディジタルデータのタ
イミングチャートの１例を示し、この図を用いて本発明
の詳細な説明する。入力信号Ａは、同期信号１に先行す
るダミーデータ部２と、ディジタルデータ部３よ多構成
されているとする。Ｂは入力信号Ａを同期信号の１周期
Ｔｏだけ遅延させた信号である。これらの信号に対して
それぞれ同期信号を検出寺を行ない、この２つの信号の
論理和Ｃと論理積りをとる。いま先頭のブロックの同期
信号に誤りが発生すると、点線で示すように先頭の同期
信号が欠損する。しかし論理和Ｃの出力信号は図示した
ように、遅延データＢに対しては先頭の同期信号が検出
できたと等価になる。このように信号を遅延することに
よシ後方の同期信号によシ前方の同期信号を推定するこ
とが可能となる。FIG. 2 shows an example of a timing chart of digital data including a synchronization signal (SY), and the present invention will be explained in detail using this diagram. It is assumed that the input signal A is composed of a dummy data section 2 preceding the synchronizing signal 1 and a digital data section 3. B is a signal obtained by delaying the input signal A by one cycle To of the synchronization signal. A synchronization signal is detected for each of these signals, and the logical sum and AND of these two signals are calculated. If an error occurs in the synchronization signal of the first block, the first synchronization signal will be lost as shown by the dotted line. However, as shown in the figure, the output signal of the OR C is equivalent to the detection of the leading synchronization signal for the delayed data B. By delaying the signal in this manner, it becomes possible to estimate the front synchronization signal from the rear synchronization signal.
まな、同期信号を検出するＫあたっては、元の信号Ａと
遅延信号Ｂの関の相関を求め、はぼ一致した場合にこれ
を同期信号とすればよい。このため、ＡとＢの排他論理
和を求め、一定時間幅（同期パターンの幅）の中の一致
したビット数を計数し、この結果が設定値以上の場合に
はこれを同期信号とすればよい。Furthermore, in order to detect the synchronization signal, the correlation between the original signal A and the delayed signal B may be determined, and if they match, this may be used as the synchronization signal. Therefore, calculate the exclusive OR of A and B, count the number of matching bits within a certain time width (width of the synchronization pattern), and if the result is greater than the set value, use this as the synchronization signal. good.
以下、本発明の一実施例を第１図、第２図によシ説明す
る。入力端子１０に入力された信号Ａは遅延回路１１に
より同期信号の繰勺返し周期Ｔ。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. The signal A input to the input terminal 10 is processed by the delay circuit 11 so that the synchronization signal repeats at a repetition period T.
だけ遅延される［Ｆ］）。次に、同期信号検出回路１２
で後述のような手段により元の信号Ａと遅延信号Ｂから
同期信号を検出する。この同期信号Ｅはディジタル処理
回路１３に送られ、遅延信号Ｂに対して種々の演算処理
、たとえば誤シ訂正やデータ時間軸変換などが行なわれ
た後、出力端子１４に出力される。[F]). Next, the synchronization signal detection circuit 12
Then, a synchronizing signal is detected from the original signal A and the delayed signal B by means described later. This synchronizing signal E is sent to a digital processing circuit 13, and after various arithmetic processing is performed on the delayed signal B, such as error correction and data time axis conversion, it is outputted to an output terminal 14.
同期信号検出回路１２の詳しい構成図を第３図に示す。A detailed configuration diagram of the synchronization signal detection circuit 12 is shown in FIG.
入力端子１０からの信号Ａは第１の同期パターン検出回
路２０に入力される。この回路では信号Ａの中から同期
パターンを検出し、同期検出パルスＡ／（図示せず）を
ＡＮＤ回路２２とＯＲ回路２３に出力する。同様に遅延
回路１１の出力信号Ｂは第２の同期パターン検出回路２
１に入力され、同期検出パルスＢ／（図示せず）を出力
する。ＡＮＤ回路２２の出力信号りとＯＲ回路２３の出
力信号Ｃ１同期判定回路２４に入力される。この回路で
はＡＮＤ回路２２の出力信号りがＯＮになった場合には
完全に正しい同期信号が得られたとして後述の同期予測
などの動作を初期化する。同期判定回路２４では、数周
期にわたシＡＮＤ回路２２からの出力信号りが得られな
い場合には０几回路２３の出力信号Ｃを正しい同期信号
と見なす。これによジブロックの先頭の同期信号はＯＲ
回路の出力となり正しく検出することが可能となる。な
お、同期検出が確定した後には同期保護処理回路２５に
より、データ中に含まれる同期信号と同じパターンによ
る誤まった同期検出が行なわれないように保護する。Signal A from input terminal 10 is input to first synchronization pattern detection circuit 20 . This circuit detects a synchronization pattern from the signal A and outputs a synchronization detection pulse A/ (not shown) to an AND circuit 22 and an OR circuit 23. Similarly, the output signal B of the delay circuit 11 is transmitted to the second synchronization pattern detection circuit 2.
1 and outputs a synchronization detection pulse B/ (not shown). The output signal of the AND circuit 22 and the output signal C1 of the OR circuit 23 are input to the synchronization determination circuit 24. In this circuit, when the output signal of the AND circuit 22 turns ON, it is assumed that a completely correct synchronization signal has been obtained, and operations such as synchronization prediction, which will be described later, are initialized. If the output signal C from the AND circuit 22 is not obtained for several cycles, the synchronization determination circuit 24 considers the output signal C of the zero-pass circuit 23 to be the correct synchronization signal. As a result, the synchronization signal at the beginning of the diblock is OR
It becomes the output of the circuit and can be detected correctly. Note that after the synchronization detection is confirmed, the synchronization protection processing circuit 25 protects the data from being erroneously detected due to the same pattern as the synchronization signal included in the data.
以上の回路によシ、データや同期が不連続となる場合、
すなわち間欠的な信号の先頭の同期が誤まった場合であ
っても効率良く同期信号を検出することができる。If the above circuit causes discontinuity in data or synchronization,
That is, even if the synchronization at the beginning of an intermittent signal is incorrect, the synchronization signal can be detected efficiently.
本発明の他の実施例を第４図を用いて説明する。Another embodiment of the present invention will be described with reference to FIG.
この図は第３図の同期信号検出回路１２の部分を示した
ものである。第１及び第２の同期パターン検出回路２０
、ＯＲ回路２３は第３図と同じである。この例では入力
端子ｌＯからの信号Ａと遅延回路１１からの信号Ｂとを
排他論理和ＥＸＯＲ回路３０に入力し、２つの信号の相
関を計算する。This figure shows a portion of the synchronizing signal detection circuit 12 of FIG. 3. First and second synchronization pattern detection circuits 20
, the OR circuit 23 is the same as in FIG. In this example, the signal A from the input terminal 10 and the signal B from the delay circuit 11 are input to the exclusive OR EXOR circuit 30, and the correlation between the two signals is calculated.
このＥＸＯＲ回路３０の出力ＨとＯＲ回路２３の出力を
同期判定回路３１に入力する。この回路では、たとえば
信号ＣがＯＮとなシかつＥＸＯＲ回路の出力信号Ｈの′
″１”の個数が、同期期間中に設定値以上となった場合
、これを正しい同期信号とする。つまＣＡかＢどちらか
の信号に同期パターンが存在し、かつ両信号に強い相関
があった場合に同期信号を検出できたとするものである
。また同期保護処理回路２５は１１ｇ３図と同じである
ので省略する。The output H of the EXOR circuit 30 and the output of the OR circuit 23 are input to a synchronization determination circuit 31. In this circuit, for example, if the signal C is not ON and the output signal H of the EXOR circuit is
If the number of "1"s becomes equal to or greater than the set value during the synchronization period, this is regarded as a correct synchronization signal. In other words, it is assumed that a synchronization signal can be detected when a synchronization pattern exists in either signal CA or B, and there is a strong correlation between both signals. Further, the synchronization protection processing circuit 25 is the same as that shown in Fig. 11g3, so its description will be omitted.
なお、上記の例では信号の遅延は周期信号の繰シ返し周
期分としだが、この整数倍であってもよいことは言うま
でもない。In the above example, the signal delay is equal to the repetition period of the periodic signal, but it goes without saying that it may be an integral multiple of this.
以上述べたように、本発明によれば簡単な遅延回路及び
ゲート回路等を使用することによシ、回転ヘッドなどを
使用した記録再生方式など間欠的なデータを処理するシ
ステムにおいて、先頭ブロックの同期信号の検出能力を
大幅に向上することができる。As described above, according to the present invention, by using a simple delay circuit, gate circuit, etc., it is possible to use a system that processes intermittent data such as a recording/reproducing method using a rotating head. The ability to detect synchronization signals can be greatly improved.
また、ドロップアウト等によシ比較的長い誤シが発生し
、同期信号が検出不能の場合にも、この回路により同様
の効果が得られ、同期検出の能力が向上するという長所
もある。Further, even when a relatively long error occurs due to dropout or the like and the synchronization signal cannot be detected, this circuit has the advantage that the same effect can be obtained and the synchronization detection ability is improved.
第１図は本発明の一実施例を示すブロック図、第２図は
第１図の各部の波形を示すタイミングチャート図、第３
図は第１図の同期信号検出回路の詳細を示す図、第４図
は第１図の同期信号検出回路の別の例を示す図である。
１１・・・遅延回路、１２・・・同期信号検出回路、１
３・・・ディジタル処理回路。
憂 １ 図
埠 ２ 図
（Ｅ）FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing waveforms of each part of FIG. 1, and FIG.
1 is a diagram showing details of the synchronizing signal detection circuit of FIG. 1, and FIG. 4 is a diagram showing another example of the synchronizing signal detection circuit of FIG. 1. 11...Delay circuit, 12...Synchronization signal detection circuit, 1
3...Digital processing circuit. Ue 1 Zubo 2 Diagram (E)
Claims (1)
ータを伝送又は記録再生する方式において、再生信号を
同期信号の繰り返し周期Ｔｏの整数倍だけ再生信号を遅
延させる手段と、上記遅延信号から同期信号位置を検出
する第１の同期検出手段と、前記遅延する前の再生信号
から同期信号位置を検出する第２の同期検出手段を有し
、上記第１及び第２の同期信号検出した信号を演算処理
を行なつて同期信号を確定することを特徴とする同期信
号検出方式。 ２、特許請求の範囲第１項において、上記第１及び第２
の同期信号検出出力の論理和を同期信号とすることを特
徴とする同期信号検出方式。 ３、特許請求の範囲第１項において、上記第１及び第２
の同期信号の排他論理和を取つた後、この信号の“１”
の数を一定期間計数した結果が設定値以上の場合に同期
信号が確定したとすることを特徴とする同期信号検出方
式。[Claims] 1. In a method for transmitting, recording and reproducing digital data including at least two synchronization signals, means for delaying the reproduction signal by an integral multiple of the repetition period To of the synchronization signal; a first synchronization detection means for detecting a synchronization signal position from a delayed signal; and a second synchronization detection means for detecting a synchronization signal position from the reproduced signal before being delayed; A synchronization signal detection method is characterized in that a synchronization signal is determined by performing arithmetic processing on a detected signal. 2. In claim 1, the above-mentioned first and second
A synchronization signal detection method characterized in that a logical sum of synchronization signal detection outputs is used as a synchronization signal. 3. In claim 1, the above-mentioned first and second
After taking the exclusive OR of the synchronization signals, this signal becomes “1”.
A synchronization signal detection method is characterized in that a synchronization signal is determined to be determined when the result of counting the number of for a certain period of time is equal to or greater than a set value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61234607A JPS6390070A (en) | 1986-10-03 | 1986-10-03 | Synchronizing signal detecting system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61234607A JPS6390070A (en) | 1986-10-03 | 1986-10-03 | Synchronizing signal detecting system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6390070A true JPS6390070A (en) | 1988-04-20 |
Family
ID=16973685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61234607A Pending JPS6390070A (en) | 1986-10-03 | 1986-10-03 | Synchronizing signal detecting system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6390070A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01137844A (en) * | 1987-11-25 | 1989-05-30 | Nec Corp | Block synchronizing circuit |
| US5546243A (en) * | 1992-10-22 | 1996-08-13 | Hitachi, Ltd. | Data and synchronization signal outputting apparatus for recovering missing data and synchronization signals |
| JP2010063020A (en) * | 2008-09-05 | 2010-03-18 | Japan Radio Co Ltd | Synchronization establishment system |
-
1986
- 1986-10-03 JP JP61234607A patent/JPS6390070A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01137844A (en) * | 1987-11-25 | 1989-05-30 | Nec Corp | Block synchronizing circuit |
| US5546243A (en) * | 1992-10-22 | 1996-08-13 | Hitachi, Ltd. | Data and synchronization signal outputting apparatus for recovering missing data and synchronization signals |
| JP2010063020A (en) * | 2008-09-05 | 2010-03-18 | Japan Radio Co Ltd | Synchronization establishment system |
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