JP2982320B2 - Synchronous signal extraction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous signal extracting circuit for extracting a synchronous signal from a digital data signal in which the synchronous signal is inserted at predetermined time intervals.

[0002]

2. Description of the Related Art As a digital signal in which a synchronization signal is inserted so as to keep a predetermined time interval, there is a video signal as shown in FIG. 3 which is processed in, for example, a digital video tape recorder (digital VTR).

That is, a video signal is obtained by adding address data AD representing position information on a screen to the head of an image data group DD representing a predetermined range of image signals on the screen.
It has a signal format in which video signal portions BD for blocks are sequentially and continuously transmitted in time series, and reproduces an analog video signal for one frame based on address data AD assigned to each video signal portion BD. It has been made like that. The synchronizing signal necessary to obtain a reproduced image is, for example, a video signal portion B at the front position of each address data AD.
By inserting the synchronization signal data SD as a part of D, the interval from the time when the synchronization signal data SD of one video signal part BD arrives to the time when the synchronization signal data SD of the next video signal part BD arrives can be set. The reproduction is performed as one cycle of the synchronization signal.

In a digital video signal of this kind, address data AD of a video signal portion BD which follows sequentially
Are assigned with address numbers whose contents are sequentially changed in accordance with a predetermined regularity. For example, the address number has an address content that is incremented by one address for each video signal portion BD, so that the position information of each image data group DD can be easily identified on the reproduction side. .

Here, the synchronization signal data SD has a data length of, for example, 16 bits, and is arranged in the image data group DD as an array of logic "H" or "L" within the data length (this is called a pattern). Is selected so that the synchronization signal data SD is not erroneously determined to have arrived while the image data group DD is actually being transmitted.

When the video signal VD having such a configuration is received by the video signal reproducing apparatus and a digital data signal including a synchronizing signal, for example, a standard television signal is to be reproduced, the synchronizing signal data SD is extracted. As a method, data having the same pattern as the synchronizing signal data SD is stored in the video signal reproducing apparatus in advance, and the sequentially arriving video signal VD is constantly compared with the reference synchronizing signal pattern. When a signal portion having the same pattern as that described above arrives, a method may be considered in which the arrival time is determined to be the time when the synchronization signal data SD arrives.

[0007]

However, when the above method is employed, the probability that a data array having the same pattern as the synchronization signal data SD will occur in the image data group DD is sufficiently reduced, and erroneous determination is made in practice. In order to avoid this, it is necessary to increase the number of bits of the synchronization signal data SD considerably, and therefore, there is a problem that the probability of occurrence of errors in the synchronization signal data SD increases.

The present invention solves the above-mentioned problem. The present invention has been made to solve the above-mentioned problem, and to make it possible to reliably identify the synchronization signal data SD and the data portion of the image data group DD while minimizing the data amount of the entire video signal VD. It is an object to provide an extraction circuit.

[0009]

In order to achieve the above object, the present invention is constructed by sequentially inserting synchronization signal data, address data and error detection code data at predetermined time positions of continuous digital data. A word synchronization circuit for distinguishing one word at a time in serial data of a transmission signal, and detecting whether or not a pattern of first conversion data obtained corresponding to the synchronization signal data in the synchronization circuit matches a predetermined reference pattern. Signal detecting circuit for sending out a detection signal, and whether or not an error has occurred in the address data based on the second and third converted data obtained corresponding to the address data and the error detection code data in the word synchronizing circuit. And an address error detecting circuit for detecting the error and transmitting a detection signal based on the first and third converted data in the word synchronizing circuit. A synchronization signal error detecting circuit for transmitting a detection signal by detecting whether the synchronizing signal data error has occurred, and the N-th address data (N + 1) th
A relative relationship detecting circuit for detecting a relative relationship with the third address data, a synchronous signal detecting circuit, an address error detecting circuit, a synchronous signal error detecting circuit, and synchronous signal data and address data obtained by taking in the detection signals of the relative relationship detecting circuit. And an output signal forming circuit for transmitting a synchronous output signal based on the logic levels of the determination signals of the N error location determination circuits.

[0010]

According to the present invention, the video signal V
D is taken into the word synchronizing circuit, and an address error detection, a synchronizing signal detection and a synchronizing signal error detection are performed from the output signal data, and the Nth address data and the (N + 1) th address data of the video signal portion BD are compared. The error location is determined from the relative relationship detection, and the synchronization signal data SD
And the data portion of the image data group DD.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A synchronous signal extracting circuit according to an embodiment of the present invention will be described below in detail with reference to the drawings. In the case of the present invention, the video signal VD has the same reference numerals as those in FIG. 3 and, as shown in FIG. 2, an error detection code is provided between the address data AD and the image data group DD for each video signal portion BD. Data ED has been inserted. This error detection code ED
Is composed of 16 bits, so that error correction by parity check can be executed on the synchronization signal data SD and the address data AD also composed of 16 bits. Note that, as the error detection code data ED, generally, data prepared for the synchronization signal data SD and the address data AD can be applied.

FIG. 1 is a block diagram of a synchronization signal extracting circuit according to one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an input terminal of a video signal VD, and 2 denotes a signal of one block of the video signal VD input from the input terminal 1 (a signal of one block is synchronizing signal data SD, address data AD, error detection code data). A holding circuit 3 for holding the ED and the image data group DD) collects an output signal from the holding circuit 2 and converts the serial data into parallel data (serial-parallel conversion circuit (serial-parallel conversion). The circuit is an example of a word synchronization circuit in the claims.) The error detection code data conversion unit 3P, the address data conversion unit 3A, and the synchronization signal data conversion unit 3S are cascaded from the input terminal, and thus are connected. Sync signal data S of each video signal portion BD
When D is shifted into the synchronization signal data conversion unit 3S, the address data AD and the error detection code data ED are input to the conversion units 3A and 3P, respectively. Reference numeral 4 denotes an address error detection circuit which takes in the conversion data S1P from the error detection code data conversion unit 3P and the conversion data S1A from the address data conversion unit 3A to detect an address error, and 5 denotes a synchronization signal data conversion unit 3S.
A synchronization signal detecting circuit for comparing the converted data S1S from the data with a predetermined pattern;
A synchronous signal error detecting circuit for detecting an error of the synchronous signal by taking in the converted signal S1S and the converted data S1S; a detecting signal S1 of an address error detecting circuit 4, a synchronous signal detecting circuit 5, a synchronous signal error detecting circuit 6 and a relative relationship detecting circuit 13; , S
2, an error portion discriminating circuit which takes in S3 and S7 to detect errors in synchronization signal data and address data, and a serial-parallel conversion circuit 8 which takes in video signal VD and converts serial data into parallel data. , An address error detection code data conversion unit 8P, an address data conversion unit 8A, and a synchronization signal data conversion unit 8S are connected in cascade, and the circuit operation is the same as that of the serial-parallel conversion circuit 3.
Reference numeral 9 denotes conversion data S2P from the error detection code data conversion unit 8P and conversion data S2P from the address data conversion unit 8A.
An address error detection circuit which takes in 2A and detects an address error, 10 is a synchronization signal detection circuit which compares the conversion data S2S from the synchronization signal data conversion unit 8S with a predetermined pattern, and 11 is conversion data S2P and conversion data. A synchronizing signal error detecting circuit which takes in S2S and detects an error of the synchronizing signal. Reference numeral 12 denotes an address error detecting circuit 9, a synchronizing signal detecting circuit 10, a synchronizing signal error detecting circuit 11, and detecting signals S4 and
An error location discriminating circuit which takes in S5, S6, and S7 and detects errors in synchronization signal data and address data;
Reference numeral 3 denotes a correlation detection circuit that detects a correlation between the converted data S1A and S2A, 14 denotes an output signal forming circuit (AND circuit), and 15 denotes an output terminal of a synchronous output signal (from the serial-parallel conversion circuit 3). The circuit up to the error location detection circuit 7 is an N-block circuit, and the serial-parallel conversion circuit 8
To the error point detection circuit 12 are defined as (N + 1) block circuits. ).

The relationship between the components and the operation of the synchronization signal extracting circuit of the above components will be described below with reference to FIGS. 1, 2 and 3.

In FIG. 1, a video signal VD is input in time series from an input terminal 1 and a holding circuit 2 holds one block of data. (1) output from the holding circuit 2
The video signal VD (delayed by a block) is input to the serial-parallel conversion circuit 3, and is sent out as conversion data S1S, S1A, S1P of parallel bits by the conversion units 3S, 3A, 3P, respectively. Conversion data S1 for address data AD
A and the conversion data S1P for the error detection code data ED are supplied to the address error detection circuit 4. The address error detection circuit 4 converts the converted data S1A and S1A
The parity check operation is performed by 1P, and when no error occurs in the address data AD, the logic becomes "H", and when an error occurs, the logic outputs a detection signal S1 which becomes "L".

The conversion data S1S for the synchronization signal data SD is given to the synchronization signal detection circuit 5. The synchronization signal detection circuit 5 stores and stores a predetermined pattern for the synchronization signal data SD, compares it with the sequentially-arriving conversion data S1S, and outputs a detection signal S2 that rises to logic "H" when they match. I do.

The conversion data S1S for the synchronization signal data SD and the conversion data S1P for the error detection code data ED are given to the synchronization signal error detection circuit 6. The synchronization signal error detection circuit 6 converts the converted data S1S
And a parity check operation by S1P,
If no error occurs in the synchronization signal data SD, the logic becomes "H", and if an error occurs, the logic outputs a detection signal S3 which becomes "L".

The circuit operation of the serial-to-parallel conversion circuit 8 to the synchronization signal error detection circuit 11 shown in FIG. 1 is equivalent to the circuit operation of the serial-to-parallel conversion circuit 3 to the synchronization signal error detection circuit 6.

The conversion data S1A from the address data conversion unit 3A and the conversion data S2A from the address data conversion unit 8A are provided to the relative relationship detection circuit 13.
The relative relationship detection circuit 13 converts the converted data S1A and S1A
When the relationship of 2A is maintained at a constant interval, the logic becomes "H", and when the interval is not maintained, the logic outputs a detection signal S7 which becomes "L".

Next, the detection signals S1, S2, S3, and S7 are supplied to the error location discriminating circuit 7 of the N block, and when all the data have a correct relative relationship, a logic "H" is output. The circuit operation of the error location determination circuit 12 of the (N + 1) block is equivalent to that of the error location determination circuit 7 of the N block.

The operation of the error location discriminating circuits 7 and 12 is as follows: when the synchronizing signal data SD of N blocks or (N + 1) blocks is not detected or is erroneous, or
When the synchronization signal data SD and the address data AD are incorrect, when the error detection code data ED is detected, the synchronization output signal data VO is transmitted as logic "L".

Next, when the synchronizing signal data SD and the address data AD are correct in the video signal portion of the N block and the error detection code data ED is detected as having no error, the address of the video signal portion BD of the (N + 1) block is determined. If it is detected that the error detection code data ED is incorrect, even though the data AD is correct and the correlation position between the address data AD of the N block and the (N + 1) block is correct, it is determined that there is no synchronization signal data SD, and the logic " As L, the synchronous output signal data VO is transmitted.

Next, if the synchronization signal data SD and the address data AD are correct in the video signal portion of the N block and the error detection code data ED is detected as having no error, the address of the video signal portion BD of the (N + 1) block is determined. If the data AD is correct, but there is no correlation between the address data AD of the N block and the (N + 1) block and the error detection code data ED is detected in spite of the fact that the synchronization signal data SD is not detected, the pseudo synchronization signal is output. It determines that the data is data and sends out the synchronous output signal data VO as logic "L".

The output signal forming circuit 14 is constituted by an AND circuit, and includes an error location determination circuit 7 and an error location determination circuit 12
Is "H" when the output signal logic becomes "H".
Is output from the output terminal 15. Therefore, the output signal forming circuit 14 sends out the synchronous output signal VO at the timing each time the synchronous signal data SD arrives at the synchronous signal extracting circuit.

This operation is executed at the timing each time the synchronization signal data SD arrives. Thus, the synchronization output signal VO synchronized with the synchronization signal data SD can be transmitted from the synchronization signal extraction circuit.

The address data AD and the synchronizing signal data SD are respectively attached to the image data groups DD of the respective video signal portions BD, and the error detection code data ED for correcting them are also attached to each image data group DD. . Therefore, the timing at which the error check for the address data is obtained is determined by the synchronization signal extraction circuit.
This has a meaning equivalent to D representing the arrival timing.

On the other hand, the synchronization signal data S at the N-th address
A data portion between the timing when D arrives at the synchronization signal extraction circuit and the timing when the next (N + 1) th synchronization signal data SD arrives, for example, the same pattern as the pattern of the synchronization signal data SD in the image data group DD When the data portion enters the synchronization signal data conversion section 3S, the synchronization signal detection circuit 5 outputs a coincidence detection output S2 of logic "H". However, at this time, the address data AD and the error detection code data ED are not included in the address data conversion unit 3A and the address error detection code data conversion unit 3P. Signal S
1 is extremely small, and therefore, the output signal V of the logic "H" is actually output from the output signal forming circuit 14.
It can be said that there is no risk of O being transmitted.

As described above, according to the synchronization signal extracting circuit of the embodiment of the present invention, in addition to the detection result of the synchronization signal coincidence detection operation for the synchronization signal data SD, the detection result of the address error detection operation, the synchronization signal error detection operation , And the synchronization output signal VO is obtained based on the detection result of the correlation between the address data of the N block and the address data of the (N + 1) block. Even in the group DD, the probability of detecting erroneous synchronization signal data can be significantly reduced. Therefore, the synchronization signal data SD
, It is possible to reliably obtain a synchronization output signal VO synchronized with the synchronization signal data SD even if the length is shortened.

In this embodiment, the present invention is applied to the case of transmitting a digital video signal, but the present invention is not limited to this.
In short, the present invention can be widely applied to digital signals formed by inserting synchronization signal data.

[0029]

As is apparent from the above embodiments, according to the present invention, based on the detection result of the synchronization signal data, the error detection result of the synchronization signal data, the error detection result of the address and the correlation between the address data. Since the synchronization signal is arranged to be extracted, it is possible to provide a synchronization signal extraction circuit having a very small probability of malfunction even when using synchronization signal data having a short data length.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronization signal extracting circuit according to the present invention.

FIG. 2 is a pattern diagram of digital data used in a synchronization signal extracting circuit according to the present invention.

FIG. 3 is a pattern diagram of digital data including a conventional synchronization signal.

[Explanation of symbols]

 2 holding circuit 3P error detection code data conversion unit 3A address data conversion unit 3S synchronization signal data conversion unit 4 address error detection circuit 5 synchronization signal detection circuit 6 synchronization signal error detection circuit 7 error location determination circuit 8P error detection code data conversion unit 8A Address data conversion section 8S Synchronization signal data conversion section 9 Address error detection circuit 10 Synchronization signal detection circuit 11 Synchronization signal error detection circuit 12 Error location determination circuit 13 Relative relation detection circuit 14 Output signal formation circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 5/91-5/956 H04N 5/10

Claims (1)

(57) [Claims] 1. A word synchronization circuit for distinguishing one word at a time in serial data of a transmission signal constituted by sequentially inserting synchronization signal data, address data and error detection code data at predetermined time positions of continuous digital data. A synchronization signal detection circuit for detecting whether or not the pattern of the first converted data obtained corresponding to the synchronization signal data in the word synchronization circuit matches a predetermined reference pattern, and transmitting a detection signal; The word synchronization circuit detects whether or not an error has occurred in the address data based on the second and third conversion data obtained corresponding to the address data and the error detection code data, and sends a detection signal. An address error detecting circuit for detecting the synchronization signal based on the first and third converted data in the word synchronization circuit. A synchronization signal error detecting circuit for transmitting a detection signal by detecting whether an error has occurred in the data,
A relative relationship detection circuit for detecting a relative relationship between the Nth address data and the (N + 1) th address data;
The synchronization signal detection circuit, the address error detection circuit,
An error location discriminating circuit which takes in the detection signals of the synchronization signal error detection circuit and the relative relationship detection circuit to detect errors in the synchronization signal data and the address data; and a logic of a discrimination signal of the N error location discrimination circuits. A synchronizing signal extracting circuit for transmitting a synchronizing output signal based on the level;