JPS60137187A - Synchronizing signal extracting circuit - Google Patents

Abstract

PURPOSE:To reduce the probability of extracting malfunction by extracting a synchronizing signal on the basis of the detection result of synchronizing signal data and the error detection result of address data. CONSTITUTION:A video signal VD has address error detection code data AE interposed between address data AD and an image data group DA as to each video signal part DP. When this video signal VD is inputted to the series-parallel converting circuit 2 of a synchronizing signal extracting circuit, data SY is supplied as conversion data S1S at the input timing of data SY, AD, and AE and a synchronizing signal coincidence detection output S2 is sent out. At the same time, an error check is made on the basis of conversion data S1A and S1P and an error detection signal S3 is outputted unless there is an error. Therefore, every time synchronizing data SY arrives, a synchronizing output signal V0 is outputted at the timing.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a synchronization signal extraction circuit, and is particularly applicable to extracting a synchronization signal from a digital data signal in which a synchronization signal is inserted at predetermined intervals. It is suitable for this purpose.

[Background technology and its problems]

An example of a digital signal obtained by inserting a synchronizing signal so as to maintain a predetermined time interval is a video signal as shown in FIG. 1, which is processed in, for example, a digital video tape recorder (digital VTR).

In other words, the video signal consists of one block of video signal portion DP, which is formed by adding address data AD representing position information on the screen to the head position of an image data group DA representing a predetermined range of image signals on the screen, in a time series manner. The signal format is such that each video signal portion D is transmitted sequentially and continuously.
The analog video signal for one frame is reproduced based on the address data AD attached to P. The synchronizing signal necessary to obtain a reproduced image can be generated by inserting the same 311I signal data SY as a part of the video signal portion DP in the front position of each address data AD, for example, to generate a synchronizing signal of one video signal portion DP. The interval from the time when the data SY arrives until the time when the synchronizing signal data SY of the next video signal portion DP arrives is reproduced as one cycle of the synchronizing signal.

Please use L7A for this kind of digital video signal.)1
The address data AD of the video signal portion DP that follows the top is assigned address numbers such that the contents change sequentially according to a predetermined regularity.

For example, the address number is made to have address contents that are incremented by one address for each video signal portion DP, thus making it easier for the playback side to determine the position information of each image data group DA. .

Here, the synchronizing signal data SY has a data length of, for example, 16 bits (that is, 2 words), and is generated within the image data group DA as an array of logic rHJ or rLJ (this is called a pattern) within the data length. In this way, it is possible to avoid erroneously determining that the synchronization signal data SY has arrived while the image data group DA is actually being transmitted.

When a video signal reproducing device receives a video signal VD having such a configuration and reproduces a digital data signal including a synchronization signal, such as a standard television signal, the method for extracting the synchronization signal data SY is to Data having the same pattern as the synchronization signal data SY is stored in advance on the playback device side, and sequentially arriving video signals VD are constantly compared with the reference synchronization signal pattern. A method may be considered in which when the signal portion of SY arrives, the time of arrival is determined to be the time of arrival of the synchronizing signal data SY.

However, when such a method is adopted, in order to sufficiently reduce the probability that a data array having the same pattern as the synchronization signal data SY will occur within the image data group DA, and to prevent misjudgment in practice, the synchronization signal data SY is It is necessary to keep the number of bits of the video signal V
There is a disadvantage that the transmission time required to transmit l) is long.

[Purpose of the invention]

The present invention has been made in consideration of the above points, and it is possible to reduce the data ambiguity of the video signal V'D as a whole as much as possible, while also being able to reliably distinguish between the synchronizing signal data SY and the data portion of the image data group DA. This paper attempts to propose a synchronization signal extraction circuit based on the following.

[Summary of the invention]

In order to achieve this object, in the present invention, a transmission signal obtained by sequentially inserting synchronization signal data, address data, and address error detection code data at predetermined time positions of a series of digital data is parallelized by a serial-parallel conversion circuit. Based on the first converted data obtained corresponding to the synchronization signal data in this serial-parallel conversion circuit, it is determined whether the pattern of the first converted data matches a predetermined reference pattern. At the same time, an error is detected in the address data as a result of second and third conversion data obtained corresponding to the address data and address error detection code data in the serial-to-parallel conversion circuit. A second detection signal is obtained by detecting whether or not this occurs, and a synchronous output signal is sent out based on the logic levels of the first and second detection signals.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

In the case of the present invention, the video signal VD includes address data AD and an image data group DA for each video signal portion DP, as shown in FIG.
Address error detection code data AE is inserted between them. The error detection code data AE for this address is 16
Similarly, the address data AD is made up of 16 bits, and error correction can be performed using a parity check. Furthermore, as the address error detection code data AE, one generally prepared for address data can be applied.

A video signal having such a configuration is input in a time series manner to a serial-to-parallel conversion circuit 2 of a synchronizing signal extraction circuit 1 shown in FIG. The serial-parallel conversion circuit 2 is composed of an address error detection code data conversion section 2P, two address data conversion sections, and a synchronization signal data conversion section 2S connected in cascade from the input end.
Thus, when the synchronization signal data SY of each video signal portion DP is manually shifted into the synchronization signal data converter 2S, the address data AD and the address error detection code data AE are
are input into converters 2A and 2P, respectively.

The data input into the converters 23, 2A, and 2P are parallel bit conversion data SIS and SIA.

The converted data SIS regarding the synchronizing signal data SY is sent as SIP and is given to the synchronizing signal detection circuit 3.

This synchronization signal detection circuit 3 stores a predetermined pattern for the synchronization signal data SY, and compares this with sequentially arriving conversion data, and when they match, a logic "H" is detected.
It sends out the synchronization signal coincidence detection output S2 that rises at ``, and supplies it to the output signal forming circuit 4.

On the other hand, conversion data S for address data AD
Conversion data SIP for IA and address error detection code data AE is provided to the address error detection circuit 5. This address error detection circuit 5 converts the converted data SI.
performing a parity check operation by A and SIP;
An error detection signal S3 is sent to the output signal forming circuit 4, which becomes logic "H" when no error occurs in the address data AD, and becomes logic rLJ when an error occurs.

The output signal forming circuit 4 is composed of two manual AND circuits, and the error detection signal S3 is in the logic 1-H state with no error detected in the address data AD, and the synchronization signal S
When Y arrives and the synchronization signal coincidence detection output S2 becomes the logic rHJ state, the synchronization output signal vO rises to logic "H".
Send out.

In the above configuration, at the timing when the synchronizing signal data SY, address data AD, and address error detection code data AE (Fig. 2) enter the serial-parallel converter circuit 2 while the video signal VD is sequentially arriving. , the synchronization signal data SY is given to the synchronization signal detection circuit 3 as conversion data SIS, and it is detected that this matches the reference pattern built into the detection circuit 3, and the logic "
The synchronization signal coincidence detection output S2 of "H" is output from the output signal forming circuit 4.
sent to.

At the same time, the address error detection circuit 5 executes an error check based on the address data conversion data SIA and address error detection code data conversion data SIP, and if there is no error as a result, outputs an error detection signal S3 of logic rHJ. Send to circuit 4. Therefore, the output signal forming circuit 4 outputs the synchronous output signal VO at the same timing every time the synchronous signal data SY arrives at the synchronous signal extraction circuit 1.
will be sent.

This operation is executed every time the synchronizing signal data SY arrives, and thus the synchronizing signal extracting circuit 1 can send out the synchronizing output signal 0 which is synchronized with the synchronizing signal data SY.

Incidentally, address data AD is attached to each image data group DA of each video signal portion DP, and accordingly, address error detection code data AE for correcting this is also attached to each image data group DA. This relationship is the same as that the synchronization signal data SY is provided corresponding to each image data DA, and therefore, the timing at which the error check for the address data is obtained is when the synchronization signal data SY is provided to the synchronization signal extraction circuit l. It has the same meaning as expressing the timing of arrival.

On the other hand, the timing when the synchronizing signal data SY at the Nth address arrives at the synchronizing signal extraction circuit 1, and the timing at which the synchronizing signal data SY at the Nth address
For example, if there is a data part in the image data group DA with the same pattern as the signal data SY, this data part is between the timing when the synchronizing signal data sy of the address arrives and the synchronizing signal data converter 2S If it enters , the synchronization signal detection circuit 3 becomes logic. A match detection output S2 of "H" is sent out. However, at this time, address data A
D and the address error detection code data AE are not entered into the address data conversion section 2A and the address error detection code data conversion section 2P, so the error detection signal S3 of logic "H" is sent from the detection circuit 5. The probability is extremely small, and therefore, it can be said that there is virtually no possibility that the output signal forming circuit 4 will output the logic "H" output signal (2).

According to the configuration shown in FIG. 3, the synchronizing signal data SY
By obtaining the synchronization output signal vO based on the detection result of the address error detection operation in addition to the detection result of the synchronization signal coincidence detection operation for the synchronization signal data S
Even if a data portion having the same pattern as Y exists in the image data group DA, the probability of erroneously detecting synchronization signal data can be significantly reduced. Therefore, even if the data length of the synchronizing signal data SY is shortened, the synchronizing output signal 0 synchronized with the synchronizing signal data SY can be reliably obtained.

Although the present invention has been applied to the case of transmitting a digital video signal in the above description, it is not limited thereto, but can be broadly applied to digital signals obtained by inserting synchronization signal data.

〔Effect of the invention〕

As described above, according to the present invention, since the synchronization signal is extracted based on the detection result of the synchronization signal data and the error detection result of the address data, even if synchronization signal data with a short data length is used. A synchronization signal extraction circuit that can perform an extraction operation with extremely low probability of malfunction can be easily obtained.

[Brief explanation of the drawing]

Fig. 1 is a signal waveform diagram showing the structure of general digital data, Fig. 2 is a signal waveform diagram showing the structure of a data signal used in the synchronization signal extraction circuit according to the present invention, and Fig. 3 is a signal waveform diagram showing the structure of the data signal used in the synchronization signal extraction circuit according to the present invention. FIG. 2 is a block diagram showing an example of a circuit. DESCRIPTION OF SYMBOLS 1... Synchronous signal extraction circuit, 2... Series-parallel conversion circuit, 3... Synchronous signal detection circuit, 4... Output signal formation circuit, 5... Address error detection circuit. Agent Keiki Tanabe

Claims (1)

[Claims] A serial-to-parallel conversion circuit that converts a transmission signal into parallel data by sequentially inserting synchronization signal data, address data, and address error detection code data at predetermined time positions of a series of digital data, and the above-mentioned serial-to-parallel conversion circuit. Based on the first converted data obtained corresponding to the synchronization signal data, it is detected whether the pattern of the first converted data matches a predetermined reference pattern.
A synchronizing signal detection circuit that sends out a detection signal of
A parallel conversion circuit detects whether or not an error has occurred in the address data based on second and third conversion data obtained corresponding to the address data and address error detection code data, and generates a second detection signal. A synchronization signal extraction circuit comprising: an address error detection circuit that outputs a synchronization output signal; and an output signal formation circuit that outputs a synchronization output signal based on the logic levels of the first and second detection signals.