JPH0478076B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a synchronization signal extraction circuit, and is particularly applicable to extracting a synchronization signal from a digital data signal in which a synchronization signal is inserted at predetermined intervals. It is suitable for this purpose.

[Background technology and its problems]

An example of a digital signal obtained by inserting a synchronizing signal so as to maintain a predetermined time interval is a video signal as shown in FIG. 1, which is processed in a digital video tape recorder (digital VTR).

In other words, the video signal consists of one block of video signal portion DP, which is formed by adding address data AD representing the position information on the screen to the head position of the image data group DA representing the image signal in a predetermined range on the screen, in a time series manner. It has a signal format that is transmitted sequentially and continuously, and thus reproduces one frame worth of analog video signal based on the address data AD attached to each video signal portion DP. Then, the synchronization signal necessary to obtain a reproduced image is generated by inserting synchronization signal data SY as a part of the video signal portion DP in the front position of each address data AD, so that one video signal portion DP is generated.
The interval from the time when the synchronizing signal data SY of the next video signal portion DP arrives to the time when the synchronizing signal data SY of the next video signal portion DP arrives is reproduced as one cycle of the synchronizing signal.

In this kind of digital video signal, the address data AD of successive video signal parts DP
are assigned address numbers whose contents change sequentially according to a predetermined regularity. For example address number is for each video signal part DP
The address contents are incremented by one address for each image data group DA, thus making it easier for the reproducing side to determine the position information of each image data group DA.

Here, the synchronizing signal data SY has a data length of, for example, 16 bits (that is, 2 words), and a group of image data is formed as an array of logic "H" or "L" (this is called a pattern) within the data length.
A pattern that is unlikely to occur inside the DA is selected, thus preventing it from being mistakenly determined that the synchronization signal data SY has arrived while the image data group DA is actually being transmitted.

When a video signal reproducing device receives a video signal VD having such a configuration and reproduces a digital data signal including a synchronization signal, for example, a standard television signal, the synchronization signal data
As a method for extracting SY, data having the same pattern as the synchronization signal data SY is stored in advance on the video signal playback device side, and the sequentially arriving video signal VD is constantly compared with the reference synchronization signal pattern. A method can be considered in which, when a signal portion having the same pattern as the reference synchronization signal pattern arrives, the time of arrival is determined to be the time of arrival of the synchronization signal data SY.

However, when such a method is adopted, the synchronization signal data SY is used in order to sufficiently reduce the probability that a data array with the same pattern as the synchronization signal data SY will occur within the image data group DA, and to prevent misjudgment in practice. It is necessary to take a considerably long number of bits, which has the disadvantage of increasing the transmission time required to transmit the video signal VD.

[Purpose of the invention]

The present invention has been made in consideration of the above points, and
The present invention attempts to propose a synchronization signal extraction circuit that can reliably identify synchronization signal data SY and the data portion of image data group DA while minimizing the data amount of the entire video signal VD.

[Summary of the invention]

In order to achieve this purpose, the present invention includes:
A transmission signal obtained by sequentially inserting synchronization signal data, address data, and address error detection code data at predetermined time positions of a series of digital data is converted into parallel data by a serial-parallel conversion circuit, and the serial-parallel conversion circuit converts the transmission signal into parallel data. Based on the first converted data obtained in response to the synchronization signal data in the conversion circuit, it is detected whether or not the pattern of the first converted data matches a predetermined reference pattern;
At the same time, it is determined whether an error has occurred in the address data based on second and third converted data obtained corresponding to the address data and address error detection code data in the serial-parallel conversion circuit. detecting and obtaining a second detection signal;
A synchronous output signal is sent out based on the logic levels of the first and second detection signals.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings. In the case of the present invention, the video signal VD is as shown in FIG. 2 with the same reference numerals attached to the corresponding parts as in FIG.
Address data for each video signal part DP
Address error detection code data AE is inserted between AD and image data group DA. This address error detection code data AE consists of 16 bits, and the address data also consists of 16 bits.
For AD, error correction can be performed by parity check. Note that as this address error detection code data AE, one that is generally prepared for address data can be applied.

A video signal having such a configuration is input in time series to a serial-to-parallel conversion circuit 2 of a synchronization signal extraction circuit 1 shown in FIG. The serial-to-parallel converter circuit 2 has an address error detection code data converter 2P, an address data converter 2A, and a synchronization signal data converter 2S connected in series from the input end, thus converting the synchronization signal data SY of each video signal portion DP. is shifted into the synchronization signal data converter 2S, address data AD and address error detection code data
AE is input into converters 2A and 2P, respectively.

The data input to the converters 2S, 2A, and 2P are parallel bit conversion data S1S, S1, respectively.
A, S1P, synchronization signal data SY
The conversion data S1S for the synchronization signal detection circuit 3 is given to the synchronization signal detection circuit 3. This synchronization signal detection circuit 3 stores a predetermined pattern for the synchronization signal data SY, and compares this with sequentially arriving conversion data, and when they match, the synchronization signal coincidence detection output S2 rises to logic "H". is sent to the output signal forming circuit 4.

On the other hand, conversion data S1A for the address data AD and conversion data S1P for the address error detection code data AE are provided to the address error detection circuit 5. This address error detection circuit 5 executes a parity check operation using the converted data S1A and S1P, and becomes logic "H" if no error occurs in address data AD, and becomes logic "L" if an error occurs.
The signal forming circuit 4 outputs the error detection signal S3 as
Send to.

The output signal forming circuit 4 is composed of a two-input AND circuit, and when no error is detected in the address data AD and the error detection signal S3 is in the logic "H" state and the synchronization signal SY arrives, the synchronization signal coincidence detection output S2 is output. When it becomes a logic "H" state, it sends out a synchronous output signal VO which rises to logic "H".

In the above configuration, while the video signal VD is arriving sequentially, the synchronization signal data SY, address data AD, and address error detection code data AE are
(Fig. 2) enters the serial-to-parallel conversion circuit 2, the synchronization signal data SY is given to the synchronization signal detection circuit 3 as conversion data S1S, so that this becomes the reference pattern built in the detection circuit 3. When a match is detected, a synchronization signal match detection output S2 of logic "H" is sent to the output signal forming circuit 4.

At the same time, address data conversion data S1A
The address error detection circuit 5 performs an error check based on the address error detection code data conversion data S1P, and if there is no error as a result, sends an error detection signal S3 of logic "H" to the output signal formation circuit 4. Therefore, the output signal forming circuit 4
is the synchronous output signal VO every time the synchronous signal data SY arrives at the synchronous signal extraction circuit 1.
will be sent.

This operation is executed every time the synchronization signal data SY arrives, and thus the synchronization signal extraction circuit 1 can send out the synchronization output signal VO that is synchronized with the synchronization signal data SY.

Incidentally, the address data AD is for each video signal part.
It is attached to each image data group DA of DP,
Therefore, address error detection code data AE for correcting this is also attached to each image data group DA. This relationship is the same as that the synchronizing signal data SY is provided corresponding to each image data DA, and therefore, the timing at which an error check for address data is obtained is when the synchronizing signal extraction circuit 1 receives the synchronizing signal data SY. It has the same meaning as expressing the timing of the arrival of

On the other hand, the data portion between the timing when the Nth other synchronizing signal data SY arrives at the synchronizing signal extraction circuit 1 and the timing when the next (N+1)th address synchronizing signal data SY arrives, for example, the image If the data group DA contains a data part with the same pattern as the signal data SY, if this data part enters the synchronization signal data converter 2S, the synchronization signal detection circuit 3 outputs a coincidence detection output S of logic "H".
Send 2. However, at this time, address data AD and address error detection code data AE
is not entered into the address data converter 2A and the address error detection code data converter 2P, so the probability that the error detection signal S3 of logic "H" is sent out from the detection circuit 5 is extremely small.
Therefore, in practice, the logic "H" is output from the output signal forming circuit 4.
It can be said that there is no possibility that the output signal VO will be sent out.

As described above, according to the configuration shown in FIG. 3, the synchronization output signal VO is obtained based on the detection result of the address error detection operation in addition to the detection result of the synchronization signal coincidence detection operation for the synchronization signal data SY. Even if a data portion having the same pattern as the synchronizing signal data SY is present in the image data group DA, the probability of erroneously detecting the synchronizing signal data can be significantly reduced. Therefore, even if the data length of the synchronizing signal data SY is shortened, the synchronizing output signal VO synchronized with the synchronizing signal data SY can be reliably obtained.

In the above description, the present invention is applied to the case of transmitting a digital video signal, but the present invention is not limited to this.
In short, the present invention can be widely applied to digital signals obtained by inserting synchronization signal data.

〔Effect of the invention〕

As described above, according to the present invention, since the synchronization signal is extracted based on the detection result of the synchronization signal data and the error detection result of the address data, even if synchronization signal data with a short data length is used. A synchronization signal extraction circuit that can perform an extraction operation with extremely low probability of malfunction can be easily obtained.

[Brief explanation of the drawing]

Fig. 1 is a signal waveform diagram showing the structure of general digital data, Fig. 2 is a signal waveform diagram showing the structure of a data signal used in the synchronous signal extraction circuit according to the present invention, and Fig. 3 is a synchronous signal extraction according to the present invention. FIG. 2 is a block diagram showing one embodiment of the circuit. DESCRIPTION OF SYMBOLS 1...Synchronization signal extraction circuit, 2...Series-parallel conversion circuit, 3...Synchronization signal detection circuit, 4...Output signal formation circuit, 5...Address error detection circuit.

Claims (1)

[Claims] 1. A serial-to-parallel conversion circuit that converts a transmission signal into parallel data by sequentially inserting synchronization signal data, address data, and address error detection code data at predetermined time positions of a series of digital data, and the above-mentioned serial-to-parallel conversion circuit. The circuit detects whether or not the pattern of the first converted data matches a predetermined reference pattern based on the first converted data obtained corresponding to the synchronization signal data, and generates a first detection signal. A synchronization signal detection circuit to send out,
The serial-to-parallel conversion circuit detects whether or not an error has occurred in the address data based on the second and third conversion data obtained corresponding to the address data and the address error detection code data. A synchronous signal extraction circuit comprising: an address error detection circuit that sends out a detection signal; and an output signal formation circuit that sends out a synchronous output signal based on the logic levels of the first and second detection signals. .