JPS60213129A - Error correcting circuit - Google Patents

Abstract

PURPOSE:To shorten a time required for error correction by inputting serial data to an error correcting circuit and inputting its output to a serial/parallel conversion circuit. CONSTITUTION:The error correcting circuit is constituted of two systems and a syndrome register output switching circuit 40 for alternately switching signal input and output signal fetching to/from these error correcting circuits in a horizontal scanning period of a television signal and a majority circuit output switching circuit 41 are connected. In a period from the end of data of 272 bits in a data part of a character broadcasting signal following FC to the end of a Fleming's code, the syndrome registers 36, 37 is respective error correcting circuits are alternately cleared and respective error correcting circuits are alternately operated by a Fleming's code detecting signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an error correction circuit for a coded transmission type teletext receiver, and more particularly to an error correction circuit suitable for shortening error correction processing time.

[Background of the invention]

The encoded transmission system text broadcasting is a system in which encoded character 1 graphic information is transmitted during the vertical blanking period of the television signal and displayed on the television receiver a. This encoded transmission type teletext has a faster transmission speed than the multi-turn type teletext (which transmits text and graphic information by breaking it down into dot patterns), and can transmit a large amount of text and graphic information. However, bit errors that occur in the transmission path only cause dot interference in pattern-based teletext broadcasting, but in coded transmission-based teletext broadcasting, there is a risk of different characters or missing characters, making it impossible to transmit accurate information. . Therefore,
It is necessary to adopt an effective error correction method with good transmission efficiency. Therefore, regarding coded transmission system text broadcasting, the Technical Report of the Televising Society of Japan, IC, 561-5 (1985).

As described in ``Study of Character Code Broadcasting System'' written by Yanagimachi et al., an error correction method using a (272, 190) difference set majority code is adopted. This error correction method will be described below.

The unit of the teletext signal transmitted during one period of the television signal is called 1 packet, and the sum is (27
2, 190) The transmission structure of a packet signal using a difference set majority code consists of a synchronization section and a data section, as shown in Figure 1. The synchronization section is a clock run-in (hereinafter abbreviated as CR) and 7.
CR consists of rating codes (hereinafter abbreviated as FC).

A signal that synchronizes the phase of the sampling block for teletext signal extraction with the pit clock of the teletext signal.
is a signal for detecting the beginning of the data section. The data portion consists of 190 information bits and 82 calibration bits according to the (272°190) difference set majority code.

The number of characters transmitted and received by the encoding transmission method for receiving and processing the teletext signal having such a configuration will be described below. The block diagram of the conventional encoded transmission system character count transceiver M machine is shown in the second figure.
As shown in the figure. In the figure, 1 is a television and video detection circuit, and 2 is a character data extracting circuit for extracting a teletext signal.

3 is a CR signal detection circuit that extracts the CR multiplied signal and creates a reference signal for the phase of the sampling clock; 4 is a synchronization separation circuit that separates the horizontal synchronization signal and vertical synchronization signal from the video signal; and 5 is the burst in the interposed signal. A clock generation circuit generates each stray clock signal used in the receiver based on the signal, 6 is a multiple gate generation circuit that indicates the period in which the teletext signal in the vertical return period is multiplexed, and 7 is a multiplex gate generation circuit for generating the teletext signal. A sampling clock generation circuit for sampling, 8 is a serial clock generator for converting serial data to parallel data.
Parallel conversion circuit, 9 is an FC detection circuit, 1o is a clock control circuit controlled by the FCC detection circuit output pressure, 11 is an address counter, 12 is an address switching circuit, 13 is a buffer memo IJ, 14 is a micro combinator (hereinafter M
(abbreviated as PU), 15 is an error correction circuit, 16 is a random access memory, 17 is a read-only memory, and 18 is an interface circuit for external equipment such as a remote control, an LED 9 indicator, and a glitter.

19 is a display memory circuit; 20 is a television receiver circuit for receiving and processing television signals; 21 is a television character switching circuit for switching between television signals and teletext signals;
22 is a cathode ray tube. In this block diagram, the operation of the single character broadcast receiver will be described first. The teletext signal is multiplexed in the multiplex gate generation circuit 6 by the horizontal synchronization signal and vertical synchronization signal separated by the synchronization separation circuit 4 based on the combined video signal detected by the video detection circuit 1 and the video detection circuit 1. Generate a period gate signal. This gate signal causes the character data extraction circuit 2 to extract the teletext signal. In addition, the sampling clock generating circuit 7 obtains a sampling clock synchronized with the bit clock of the teletext signal by using the signal which is the reference phase of the sampling clock obtained by the CR signal detecting circuit 3 and using the clock generated by the a-tock generating circuit 5. By this sampling clock, the teletext signal from @2 is converted into parallel data by the serial-parallel conversion circuit M8, and this parallel data is compared with the FC bit by bit by the FC detection circuit 9. Since the parallel conversion is performed by a shift register, when the last bit of FC is input to the shift register, all 8 bits of FC match, and at that point, the FC detection circuit 9 is processed.
c generates a detection signal. The FC detection signal is a synchronization signal indicating the beginning of the data portion, and only the data portion of the teletext signal is temporarily stored in the buffer memory 13 via the address switching circuit 12 by the clock control circuit 10° address counter 11! ii Works as # signal. Since the data stored in the backup memory in this manner is the transmitted data itself, it contains transmission errors. Busy to correct this error, conventionally Mp U14
Parallel data is input to and output from the error correction circuit 15 via the error correction circuit 15, the data from the buffer memory 13 is aborted by the error correction circuit 15, and then the data is stored in the buffer memory 13 again. The error-corrected data obtained in this way is processed by the MPU 14, and characters corresponding to one character code I/C are searched out from among the character patterns stored in the read-only memory 17 and displayed in the display memory 19.
and display it on the cathode ray tube 22 via the television character switching circuit 21. The above is an overview of the operation of the teletext receiver. The details of the operation of the error correction circuit of such a receiver will be described below. A simple configuration diagram of the error correction circuit 15 in FIG. 2 is shown in FIG. In FIG. 3, 23 is a conversion circuit for converting parallel data into serial data, or converting serial data into parallel data;
24 is a data register consisting of a 272-bit shift register, and 25 is exclusive to an 82-bit shift register!
Syndrome register 26 consists of a circuit that feeds back the final stage output of the shift register by i#iih sum (hereinafter referred to as EOR) 27 is the EOR circuit 2 which obtains the output of
A majority decision circuit counts the number of high level outputs of 6 and determines whether the number is 8 or more, 28 is the majority next FN5
An EOR circuit 29 performs EOR between the output of 27 and the output of the data register 24 and performs error correction, and 29 performs an EOR between the serial data before error correction, the output of the final island shift lane star of the syndrome register 25, and the output of the majority circuit 27. An EOR circuit 30 is an error detection circuit that determines whether or not there is an error based on the contents of the shift register of the syndrome register 25.

31 is an output port for transmitting data and control f1 signal from MPU 1llllJ to the error prevention circuit; 32
3 is an input port for passing the corrected data from the error correction circuit and the output of the error detection circuit 30 to the MPU-;
Reference numeral 3 denotes a timing generation circuit which supplies a timing signal and a link signal to each block of the error correction circuit according to a control signal from an output port 31. In this configuration diagram, the error correction circuit operates by first setting all contents of the syndrome register 25 to LOW level by a clear signal output from the MpU side to the output port 31.

Next, the data before error correction stored in the buffer 7 memory is transferred to the output port 3 by the load signal of the output port 31.
1 to the conversion circuit 23 in units of 16 pits, which converts it into parallel serial data and sends it to the data register 2.
4 and is serially input to the syndrome register 25. At this time, since one packet of data is 272 bits, the MpU writes one packet of data to the data register 24 and the syndrome register 25 by using the Ω-code signal 17 times. The syndrome register 25 is a circuit that divides the serially input 272-bit data by the generating polynomial % ) QO + The 82 contents represent the remainder. When loading of one packet data is completed.

Only the syndrome register 25 is cyclically shifted by 1 bit by the a-end signal of the output port 31. This is because the code used for error correction is a shortened difference set cyclic majority code shortened by one bit. Next, M
The data register 24 and the hissindrome register 25 are activated by the collect signal output from the pU to the output port 31.
is shifted by 16 bits. At this time, the syndrome register 250 is set by the FOR circuit 26 for each 1-bit shift.
EO the contents of 82 shift registers in a certain combination
R is taken and the majority decision circuit 27 calculates the sum of the contents of the 17 outputs of the EOR circuit 26. If the value of the equation at that time exceeds 8, the output of the majority circuit 27 becomes high level, indicating that there is a busy error in the first bit of the data register 24.

Therefore, the output of the data register 24 and the majority circuit 2
The leading bit of the data register can be corrected by one bit by the EOR circuit 28 which performs an EOR with the output of the data register. After that, the data register 24 and syndrome register 25 are shifted by 1 bit and the following steps are performed.

By repeating the majority decision operation and EOR operation described above, it is possible to correct errors in the redata one pit at a time. Data after error correction is frt@i bit 190 in one packet.
Since it is a bit and inspection bit 82 pinto is not necessary,
Error correction of information bits in one packet is completed by outputting a collect signal 12@ from the MPU 14. Further, in response to the collect signals 1 and 9, the error-corrected serial data is converted into parallel data by the conversion circuit 26, read out onto the data bus via the input port 32, and loaded into the buffer memory 15. That is, error correction of one packet of data is performed by reading the teletext data stored in the buffer memory 15, transferring it to the error correction circuit 15, issuing an error correction command, and then correcting the data by the error correction circuit 15. This is achieved by performing the readout process again in five steps. Since the error correction circuit 15 performs serial processing in units of 16 bits per instruction, the fA correction circuit 15
The MPU 14 looks at the 272 bits of data for one packet in 17 times according to the load signal, and when reading the data, the 272 bits of data in one packet are not needed, so only 190 bits of information bits are input. will be read out in 12 times. The processing time in such conventional error correction processing is about 15 ml per batch because the MPU 140 program processing is required for inputting and outputting teletext data as described above. The superimposition period of the teletext signal is the same as that of the television signal. period 1
211 sections are considered, and if the teletext signal is added to all of these 12H sections, the time required for error correction is 1.5z
z X 12 == 18 m, p, which exceeds the 1 field period of the television signal, 16.5 ml,
Scales that cannot perform error correction processing during one field period 5
The drawback was that it was not possible to convert character codes into character patterns and display them. Furthermore, the conventional AF correction
It also has the disadvantage of a large circuit scale because it performs error correction and then converts serial data into parallel data again.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an error correction circuit which eliminates the drawbacks of the conventional error correction circuits described above and reduces the time required for error correction.

[Summary of the invention]

The present invention is characterized by providing two systems of error correction circuits, and providing means for alternately switching the signal input and output signal output to the error correction circuits in accordance with the horizontal positioning period of the television signal. , ) - 7 from the data end of one bit of the data part of the hand broadcast signal
The syndrome register of each error correction circuit is alternately cleared during the period until the end of the ramming code, and the respective error correction circuits are alternately operated by the seven ramming code detection signals. Therefore, error correction can be processed in time series, and the processing time required for error correction can be shortened.

[Embodiments of the invention]

The following is a hilarious example of the present invention using drawings! 12 dawn.

FIG. 4 is a diagram for showing an overview of this embodiment. In FIG. 4, numerals 1 to 22 are colleagues with those in FIG.
Reference numeral 54 denotes an error side stop circuit which has a different configuration from the error correction circuit #1515 in FIG.

In FIG. M4, the only difference from FIG. 2 showing the conventional example is the error correction circuit. That is, the fourth example shows one example.
In the figure, the serial data from the character data detection circuit 2 is input to the ridge correction circuit 64, and the output of the error correction circuit 34 is serial data and is input to the serial-parallel conversion circuit 8 at the next stage. There is a difference in that the input/output of parallel data to the blanking correction circuit 15, which was required in the conventional example by the MPU 14, is no longer necessary. An example of the configuration of the error correction circuit 64 shown in FIG. 4 is shown in FIG. In FIG. 5, reference numerals 26 and 27.

The parts indicated by 28 and 50 are the same parts as in Fig. 3, and 65
3 is a data register consisting of a 190-bit shift register, 56 and 57 are syndrome registers corresponding to 25 in FIG.
4, a gate signal generation circuit that generates the necessary gate signals;
3? 40 is a syndrome register output switching circuit which determines whether or not to connect the 82 outputs indicating the remainder 82 pins of which syndrome register among the two syndrome registers 56 and 57 to the next stage. ,
41 is the syndrome register 5 which outputs the majority circuit 27.
6 and 57, a majority circuit output switching circuit that determines which input is to be input, and 42 is an output data switching circuit that switches between outputting the data before error correction as is without stopping it, or outputting data after correction. Circuit, 43 to 48 are two-man logic product M, 49°50 is EOR@W in Fig. 3
This is an EOR circuit similar to &29. In addition, the fifth
The signal waveforms of each part in the figure are shown. In Figure 6, (
1) is ffi in the horizontal scanning period where the teletext signal is continuous.
The signal waveforms (2) and (7) when folded are the signals output from the gate signal @ generation circuit 38, respectively.

(2) the S1 clock gate that gates the clock signal to the syndrome register 36; (6) the S1 data gate that gates the input data to the syndrome register 66; and (14) the S2 clock gate that gates the clock signal to the syndrome register 67). , (51 is an S2 data gate that gates the input data to the syndrome register 37), +751 is a D gate that gates the input data and the input data to the data register 35. Also, (8th, H signal that has passed only the horizontal synchronization signal of the television signal, (91 is the FC detection signal indicating the output signal of the FC detection circuit 9, (10) is the timing of the FC detection signal (9) The 190 count signal indicates the timing when the data sampling clock has been counted 190 times from the timing of the FC detection signal +=j (9). This is a count signal.It will be explained below using FIGS. 5 and 6.First, the transmitted teletext signal is extracted in units of packets by the character data extraction circuit 2 shown in FIG. The data is input to the error correction circuit 34 as data before error correction.Therefore, the M5@ gate signal generation circuit 58 generates the St data gate (51) from the FCC detection signal sum.
, S2 data gate (5), generates D gate C61,
Due to the two manual AND circuits 44, 46 and 48, data is input only to the syndrome register 36 and data register 35 during the first horizontal scanning period, and data is input only to the syndrome register 57 and data register 55 during the next horizontal scanning period. At this time, S1 theta gate c31 and S
2 data goo) The period when the high level of (5) is F
The 272 count signal (11) shown in FIG. 6 (11) is obtained by counting 272 data sampling clocks from the C detection signal.
11), which corresponds to the 272 information bits and inspection bits of the teletext signal.
This period corresponds to the length of the pit. Also, during the period when the D gate (6) is at a high level, the data sampling clock is counted 190 from the FC detection gi as shown in Figure 6 (1o).
up to the timing determined by the 190 count signal (10) shown in (10), which is the information pin of the single character broadcasting signal).
This is a period corresponding to 190 bits. Furthermore, since the data register 65 and the syndrome registers 56 and 37 are composed of foot registers, they are circuits that shift 1 bit for every 1 Ω. Therefore, the syndrome registers 56, 57 and the data register 35 are connected to the S1 clock gate (2) shown in Fig. 846 (2).
S2 clock gate shown in (4) (4) D shown in word 6)
The period after data is input to the syndrome register 36 is controlled by the sl Ω gate (2).
) is at high level, the syndrome register 36
The data before error correction is sequentially shifted to the register 36, and all 272 bits are input to the syndrome register 36. On the other hand, while data is being input to the syndrome register 36, no data is input to the syndrome register 37, but while the S2 clock gate I4) is at a high level and the land C1-4 register 5611C data is being input. In this case, data is input to the data register 55 and the D gate (6) is at a high level, so the data before the error side is stopped is sequentially shifted by 190 bits, fxb, and data is input to the syndrome register 36 and the data is shifted by 272 bits. are shifted sequentially.

This is to calculate the remainder by the generator polynomial at the same time as filling the data in the syndrome register by the 17 load signals described in the conventional example. Also.

The 190-bit shift of the syndrome register 37 during the period when data is being input to the syndrome register 36 is an operation to obtain a remainder for sequential error correction one bit at a time. Furthermore, the data is shifted by 2, but in the conventional example
A data register consisting of a 72-bit shift register was shifted by 272 bits and then shifted by 190 bits to obtain 190 information bits as output, and the remaining 82 bits were unnecessary. Therefore, in this embodiment, the circuit configuration of the data register can be reduced to 190 bits. In order to shift the syndrome register output switching circuit 40 and the majority circuit output switching circuit 41 and to switch to the syndrome register which stores the remainder for sequentially performing error correction one bit at a time, the gate switching shown in tlL6 figure (7) is performed. This is done by signal (7). Furthermore, the syndrome registers 56 and 57 are cleared by the horizontal synchronization (H signal (8) set by 1). When the gate switching signal (7) is at low level, the syndrome register 36 is cleared, and when it is at high level, the syndrome register 57 is cleared. A rear signal like this is generated by the clear signal generation circuit 39.Furthermore, in FIG. The CR and FC of the single character broadcast signal are obtained via the serial-parallel converter circuit 8 and the FC detection circuit 9, but they are synchronization signals and are unnecessary for subsequent data, so the error correction circuit 23 is bypassed. Therefore, the output data switching circuit 42 is configured to output the uncorrected data as is to the next stage only during the low level period of the gate switching signal (C) shown in FIG. 6(7).
controls the output of the error correction circuit 34. Figure 7 shows the fifth
Gate signal generation circuit 38% clear signal generation circuit 39 in the figure. Syndrome register output switching circuit 40, majority circuit output switching circuit 41. Regarding the output data switching circuit 42, a specific circuit is shown, and it can be constructed with a simple circuit as shown in the figure. With the above-described error correction circuit, uncorrected data is loaded into one syndrome register during the first horizontal scanning period when teletext signals are multiplexed, and error correction is performed during the next horizontal scanning period. Therefore, the processing time required for error correction is twice the horizontal scanning period, that is, about 127 μS, which is faster than the conventional method.

When teletext signals are transmitted in consecutive horizontal scanning periods, error correction requires twice the horizontal scanning period, so two syndrome registers are provided and data setting and correction are switched in the horizontal scanning period.

Error correction processing for continuously transmitted teletext signals is also fully possible. According to this embodiment, error correction of data in the last multiplex horizontal scanning period of the multiplexed teletext signal is performed in the next horizontal scanning period, but since FC is not transmitted during this horizontal scanning period, , there is a problem that the FC detection signal is not obtained and error correction is not performed.
By giving the FC detection signal a flywheel effect for one horizontal scanning period and generating a pseudo FC detection signal, it is possible to operate without problems. FIG. 8 shows an example of a flywheel circuit for this FC detection signal, and FIG. 9 shows waveforms of various parts of the circuit of FIG. 8. In FIG. 8, 51.degree. 52 is a monostable multivibrator, 53 is a bistable multivibrator, and 54 is an OR circuit. If we consider the case in which the teletext transmission of ℃ 11 is multiplexed for two horizontal running* periods in Fig. 9, the teletext signal is shown as (12) in the same figure. In addition, the FC detection signal at that time is outputted with only two pulses as shown in (13) in the same figure, and the FC detection signal of the third pulse necessary to error correct the second teletext signal ((13) in the same figure) is output. ) The pulse shown by the dotted line) is not output. Therefore, the output pulse width of the monostable multivibrator 51 is set to be slightly wider than the horizontal scanning period, and the monostable multivibrator 52 is set to be slightly wider than the horizontal scanning period.
Set the busy setting so that it is output at the falling edge of the output of FC.
By using the output of the bistable multivibrator 56 controlled by the detection signal (13) and the horizontal synchronization signal (14) as the clear signal of the monostable multivibrator 52, the helmet 9
Monostable multivibrator 52 as shown in Figure (17)
The output becomes a pulse equal to the FC detection signal by one pulse only in the next horizontal scanning period when the teletext signal that has been multiplexed in consecutive horizontal scanning periods is no longer multiplexed. Therefore, by performing a logical sum with the original FC detection signal in the OR circuit 54, one pseudo FC detection signal can be added to one original FC detection signal, as shown in FIG. 9 (18) K. .

All transmitted teletext signals can be amended and corrected. Also, as shown in Figure 10.

After setting data to the syndrome register.

That is, if error correction is performed, there is no need to provide a flywheel circuit for the FC detection signal as shown in Figure s%8.

Further, in this embodiment, the syndrome register is cleared using the horizontal synchronizing signal, but the CR flaw signal may also be a signal obtained by delaying the horizontal synchronizing signal as long as it is a period from FC to the end of FC.

Furthermore, in this embodiment, the circuit was simplified and explained using only two systems of shift Ω and -m registers, but a circuit having two systems of the entire aR error correction circuit, a syndrome register and an E
The wI% syndrome register and EOR circuit 1- have two systems with only OR circuits.

A circuit configuration having only two systems of majority circuits is also possible.

In either case, the present invention is effective for clearing a plurality of syndrome registers.

Note that in this embodiment, the number of bits constituting the data register is 190 bits, and a seven-signal switching circuit is used together to simplify the circuit by reducing the number of shift registers. It is obvious that it is good. Furthermore, in order to obtain the FC detection signal, the present invention has been explained using an example in which a switching circuit is provided to bypass the FC signal to the error correction circuit, and one system of serial-to-parallel conversion circuit is used. The present invention is also effective in cases where a dedicated serial-to-parallel conversion circuit is provided to obtain the output of the error correction circuit, and another serial-to-parallel conversion circuit is provided to store the output of the error correction circuit in the buffer memory. Furthermore, the output data switching circuit 42 shown in FIGS. 5 and 7 can be deleted, resulting in an error correction circuit having a simpler circuit configuration. - [Effects of the Invention] According to the present invention, error correction of one packet data can be processed within twice the horizontal scanning period.

Approximately 4. High-speed error correction can be achieved with a processing time of .

[Brief explanation of drawings]

Fig. 1 is a transmission configuration diagram of a coded transmission teletext signal, and Fig. 2 is a block diagram of a conventional coded transmission teletext receiver. FIG. 6 is a configuration diagram of a conventional job correction circuit, and FIG. 4 is a block diagram showing a coded transmission type teletext receiver employing the present invention. Figure A5 is a configuration diagram showing one embodiment of the present invention, and Figure 6 is a diagram showing one embodiment of the present invention.
The waveform diagram of each part in the diagram, Figure 7 is a specific circuit diagram of the theory 5, Figure m8 is a circuit diagram to supplement the example, Figure @9 is the waveform diagram of each part in Figure 8, Figure 10 of the helmet FIG. 3 is a waveform diagram for explaining another embodiment. 38...Gate signal generation circuit 39...Clear signal generation circuit 40...Syndrome register output switching circuit Patent attorney Akio Ko. 1st Eye 3 Figure F4 Closed 5 Record 9 (te) :: 10 Figure 6 ■ L θ 〉 F i wealth procedure amendment (self-motivated) Indication of the case 1988 Patent Application No. Title of invention No. 67726 Relationship to the case of the person who amended the error correction circuit Patent applicant Name (5101 Hitachi Co., Ltd.) Agent Subject of amendment Contents of amendment in the detailed description of the invention in the specification (Inventor: Yama 1) EO of the contents of the 82 shift registers of the syndrome register as described.
By changing the combination of R, it is also possible to eliminate the need to cyclically shift only the syndrome register by 1 bit from K. Next K,"↓Mata"2

Claims (1)

[Scope of Claims] 1. A division circuit including a plurality of exclusive ORs and a plurality of storage elements, and a framing code detection circuit that detects 7 framing codes of a teletext signal and outputs a 7 framing code detection signal. , a storage control circuit that controls whether or not to store data in the plurality of storage elements of the division circuit according to the framing code detection signal; It consists of an initialization signal generation circuit that outputs a predetermined period of time until the end of the raming code. Initializing a plurality of memory cells of the dividing circuit by an initializing signal of the initializing signal generating circuit. Thereafter, the storage control circuit is controlled by the framing code detection signal obtained by the framing code detection circuit to start supplying the information data and test data of the teletext signal to the plurality of storage elements of the division circuit. An error correction circuit characterized by: