JP2982348B2 - Synchronous signal extraction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal extracting circuit, and more particularly to a synchronizing signal extracting circuit suitable for extracting a synchronizing signal from a digital data signal in which the synchronizing signal is inserted at predetermined time intervals. It is.

[0002]

2. Description of the Related Art For example, a video signal as shown in FIG. 2 which is processed in a digital video tape recorder (hereinafter referred to as a digital VTR) as a digital signal into which a synchronization signal is inserted so as to keep a predetermined time interval. There is.

That is, a video signal is formed by adding address data AD representing position information on a screen to the head of an image data group DD representing a predetermined range of image signals on the screen.
It has a signal format in which video signal portions BD for blocks are transmitted sequentially and sequentially in time series, and reproduces an analog video signal for one frame based on address data AD assigned to each video signal portion BD. It has been made to be. The synchronizing signal necessary to obtain a reproduced image is obtained by inserting the synchronizing signal data SD as a part of the video signal portion BD at the front position of each address data AD, for example, so that the synchronizing signal data of one video signal portion BD An interval TS from the time when SD arrives to the time when the synchronization signal data SD of the next video signal portion BD arrives is reproduced as one cycle of the synchronization signal.

In a digital video signal of this kind, address data AD of a video signal portion BD which follows sequentially
Are assigned with address numbers whose contents are sequentially changed in accordance with a predetermined regularity. For example, the address number has an address content that increases by one address for each video signal portion BD, thus making it easier for the reproduction side to determine the position information of each image data group DD. .

Here, the synchronization signal data SD has a data length of, for example, 16 bits (2 words), and image data is arranged as an array of logic "H" or "L" (hereinafter referred to as a pattern) within the data length. A pattern which is unlikely to be generated inside the county DD is selected, and thus the image data count DD is actually set.
Is not erroneously determined that the synchronization signal data SD has arrived during the transmission.

When the video signal VD having such a configuration is received by the video signal reproducing apparatus and a digital data signal including a synchronization signal, for example, a standard television signal is to be reproduced, a method of extracting the synchronization signal data SD. In the video signal reproducing apparatus, data having the same pattern as the synchronization signal data SD is stored in advance, and the video signal VD sequentially arriving is constantly compared with the reference synchronization signal pattern. When a signal portion having the same pattern arrives, a method is considered in which the arrival time is determined to be the time when the synchronization signal data SD arrives.

[0007]

However, in the above-mentioned conventional configuration, the probability that a data array having the same pattern as the synchronization signal data SD will occur in the image data group DD is sufficiently reduced to prevent erroneous determination in practical use. For this purpose, it is necessary to increase the number of bits of the synchronization signal data SD to a considerable length, and therefore, there is a problem that the probability of occurrence of errors in the synchronization signal data SD increases.

The present invention solves the above-mentioned conventional problems. The present invention is intended to reduce the data amount of the entire video signal VD as much as possible and to reliably identify the synchronization signal data SD and the data portion of the image data group DD. It is an object of the present invention to provide a synchronized signal extracting circuit.

[0009]

In order to achieve this object, a synchronous signal extracting circuit according to the present invention inserts synchronous signal data, address data and error detection code data at predetermined time positions in continuous digital data. A word synchronization circuit A for distinguishing one word at a time in serial data of a transmission signal configured as described above, and a first conversion based on first conversion data obtained corresponding to the synchronization signal data in the word synchronization circuit A. A synchronization signal detection circuit B for detecting whether or not a data pattern matches a predetermined reference pattern and transmitting a detection signal; and a word synchronization circuit A corresponding to the address data and the error detection code data in the word synchronization circuit A. An address for detecting whether an error has occurred in the address data based on the obtained second and third conversion data and transmitting a detection signal. An error detection circuit C and a synchronization signal error detection circuit for detecting whether an error has occurred in the synchronization signal data based on the first and third converted data in the word synchronization circuit A and transmitting a detection signal. D and
Relative relationship detection circuit E for detecting the relative relationship between the Nth address data and the (N + 1) th address data
And a detection signal for determining that a synchronization signal is present when the relative relationship detection circuit E detects that the relative relationship of the address data is maintained even when the synchronization signal detection circuit B detects an M-bit error. A generation circuit F, an address error detection circuit C, an synchronization signal error detection circuit D, and an error portion discrimination circuit G which takes in the detection signals of the detection signal generation circuit F and detects errors in the synchronization signal data and the address data. And an output signal forming circuit H for transmitting a synchronous output signal based on the logic levels of the discrimination signals of the N error point discrimination circuits.

[0010]

With this structure, the video signal VD is taken into the word synchronization circuit, and the address signal detection, the synchronization signal detection and the synchronization signal error detection are performed from the output signal data, and the N-th address data of the video signal portion BD is read. An error location is determined from the detection of the relative relationship with the (N + 1) th address data, and the synchronization signal data SD and the data portion of the image data group DD can be reliably identified.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a synchronous signal extracting circuit according to an embodiment of the present invention. In the case of the present invention, the video signal VD has the same reference numerals as those shown in FIG.
As shown in (1), error detection code data ED is inserted between the address data AD and the image data group DD for each video signal portion BD. This error detection code E
D is composed of 16 bits, and error correction by parity check can be performed on the synchronization signal data SD and the address data AD also composed of 16 bits. Note that, as the error detection code data ED, data generally prepared for the synchronization signal data SD and the address data AD can be applied.

FIG. 3 is a block diagram showing an embodiment of the present invention. In FIG. 3, reference numeral 1 denotes an input terminal of the video signal VD, and 2 denotes a signal of one block of the video signal VD input from the input terminal 1 (the signal of one block is synchronizing signal data SD, address data AD, and error detection code ED). , An image data group DD), a serial-parallel conversion circuit for taking in an output signal from the holding circuit 2 and converting serial data into parallel data;
The serial-to-parallel conversion circuit 3 is composed of an error detection code data conversion unit 3P, an address data conversion unit 3A, and a synchronization signal data conversion unit 3S cascaded from the input end, thus synchronizing the synchronization signal data SD of each video signal portion BD. When shifted into the signal data converter 3S, the address data AD and the error detection code data ED are converted into the converters 3A and 3D, respectively.
It is made to put in P. Reference numeral 4 denotes an address error detection circuit which takes in the conversion data from the error detection code data conversion unit 3P and the conversion data from the address data conversion unit 3A to detect an address error, and 5 denotes a conversion data from the synchronization signal data conversion unit 3S. A synchronization signal detection circuit 6 for comparing with a predetermined pattern, a synchronization signal error detecting a synchronization signal error by taking in the conversion data from the error detection code data conversion unit 3P and the conversion data from the synchronization signal data conversion unit 3S. A detection circuit 7 is an error portion discrimination circuit that fetches detection signals from the address error detection circuit 4, the synchronization signal error detection circuit 6 and the detection signal generation circuit 22 to detect errors in synchronization signal data and address data, and 8 is a video signal VD. A holding circuit 9 for holding the signal of one block of FIG. Serial converting the column data into parallel data - parallel converter, serial - parallel converter circuit 9 error detection address from the input terminal code data conversion unit 9P, the address data conversion unit 9A,
The synchronous signal data converter 9S is cascaded, and the circuit operation is the same as that of the serial-parallel converter 3. Reference numeral 10 denotes an address error detection circuit which takes in the conversion data from the error detection code data conversion unit 9P and the conversion data from the address data conversion unit 9A to detect an address error, and 11 denotes a conversion data from the synchronization signal data conversion unit 9S. A synchronization signal detection circuit 12 for comparing with a predetermined pattern, a synchronization signal error detecting a synchronization signal error by taking in the conversion data from the error detection code data conversion unit 9P and the conversion data from the synchronization signal data conversion unit 9S. Detection circuit, 1
Reference numeral 3 denotes an error location determination circuit which takes in the detection signals of the address error detection circuit 10, the synchronization signal error detection circuit 12 and the detection signal generation circuit 22 to detect errors in the synchronization signal data and the address data, and 14 denotes one block of the video signal VD. A serial-to-parallel conversion circuit which takes in the video signal VD and converts serial data into parallel data; and a serial-to-parallel conversion circuit 15 which converts an error detection code data conversion unit for an address from an input terminal. Fifteen
P, an address data converter 15A and a synchronization signal data converter 15S are connected in cascade, and the circuit operation is the same as that of the serial-parallel converter 3. Reference numeral 16 denotes the converted data from the error detection code data converter 15P and the address data converter 1
An address error detection circuit which takes in the conversion data from 5A and detects an address error, 17 is a synchronization signal detection circuit which compares the conversion data from the synchronization signal data conversion unit 15S with a predetermined pattern, and 18 is an error detection code A synchronizing signal error detecting circuit which takes in the converted data from the data converting section 15P and the converted data from the synchronizing signal data converting section 15S and detects an error of the synchronizing signal, 19 is an address error detecting circuit 16, 19 is a synchronizing signal error detecting circuit 1
8 and an error portion discriminating circuit which takes in the detection signals of the detection signal generating circuit 22 to detect errors in the synchronization signal data and the address data. The conversion data 20 from the address data conversion unit 3A and the conversion data from the address data conversion unit 9A Correlation detection circuit for detecting the correlation with
Is a correlation detection circuit for detecting a correlation between the conversion data from the address data conversion unit 9A and the conversion data from the address data conversion unit 15A, and 22 is a synchronization signal detection circuit 5, a synchronization signal detection circuit 11, and a synchronization signal detection circuit. Even if an M-bit error is detected by the detection signal of No. 17, if the relative signal is determined to be guaranteed by the detection signals output from the relative signal detection circuit 20 and the relative signal detection circuit 21, the synchronization signal is output. Is a detection signal generating circuit that recognizes that the output signal is the same, 23 is an output signal forming circuit, and 24 is an output terminal of a synchronous output signal. (The circuit from the serial-parallel conversion circuit 3 to the error point detection circuit 7 is an N-block circuit,
A circuit from the parallel conversion circuit 9 to the error location detection circuit 13 is an (N + 1) block, and a circuit from the serial-parallel conversion circuit 15 to the error location detection circuit 19 is an (N + 2) block circuit. The operation of the synchronization signal extracting circuit configured as described above will be described below with reference to FIGS. 1, 2 and 3.

In FIG. 2, a video signal VD is input in time series from an input terminal 1 and a holding circuit 2 holds one block of data. (2) output from the holding circuit 2
The video signal VD (delayed by a block) is input to the serial-parallel conversion circuit 3, and is sent out as conversion data of parallel bits by the conversion units 3S, 3A, 3P. Conversion data for the address data AD and error detection code data E
The conversion data for D is supplied to the address error detection circuit 4. The address error detection circuit 4 executes a parity check operation based on the conversion data for the address data AD and the conversion data for the error detection code data ED. If no error has occurred in the address data AD, the logic becomes "H" and the error becomes "H". Occurs, a detection signal S1 having a logic "L" is output.

The conversion data for the synchronization signal data SD is supplied to the synchronization signal detection circuit 5. The synchronization signal detection circuit 5 stores and stores a predetermined pattern for the synchronization signal data SD, compares this pattern with conversion data for the sequentially arriving synchronization signal data SD, and detects a rise to logic "H" when they match. The signal S2 is output.

The conversion data for the synchronization signal data SD and the conversion data for the error detection code data ED are given to the synchronization signal error detection circuit 6. The synchronization signal error detection circuit 6 performs a parity check operation on the basis of the conversion data for the synchronization signal data SD and the conversion data for the error detection code data.
If no error occurs in D, the logic becomes "H", and if an error occurs, the logic outputs "L" to output a detection signal S3.

The serial-to-parallel converter 9 to the synchronous signal error detector 12 and the serial-to-parallel converter 15 shown in FIG.
Therefore, the circuit operation of the synchronization signal error detection circuit 18 is the same as the circuit operation of the serial-parallel conversion circuit 3 to the synchronization signal error detection circuit 6.

The conversion data from the address data conversion unit 3A and the conversion data from the address data conversion unit 8A are given to the relative relationship detection circuit 20. When the relationship between the conversion data from the address data conversion unit 3A and the conversion data from the address data conversion unit 9A maintains a constant interval, the logic of the relative relationship detection circuit 20 becomes "H" and the interval is not maintained. The case logic outputs the detection signal S10 which becomes "L".

The conversion data from the address data conversion unit 9A and the conversion data from the address data conversion unit 15A are supplied to the relative relationship detection circuit 21. When the relationship between the conversion data from the address data conversion unit 9A and the conversion data from the address data conversion unit 15A maintains a constant interval, the logic of the relative relationship detection circuit 21 becomes "H" and the interval is not maintained. In this case, the logic outputs a detection signal S11 which becomes "L".

Next, the detection signal S is supplied to the detection signal generation circuit 22.
2, S5, S8, S10, and S11 are given, and even when it is determined that an M-bit error has occurred in the synchronization signal data in S2, S5, and S8 of the detection signal and the signal is not synchronization signal data, the relative relationship detection circuit 20 , 21 output a detection signal S12 whose logic is "H" when the relative relationship is maintained, and which is "L" when the relative relationship is not maintained.

Next, the detection signals S1, S3 and S12 are supplied to the error location determination circuit 7 of the Nth block, and when all of the data have a correct relative relationship, a logic "H" is output. Further, an error location determination circuit 13 for the (N + 1) block and an error location determination circuit 19 for the (N + 2) block
Circuit operation is the same as that of the N-block error location determination circuit 7.

The operation of the error location discriminating circuits 7, 13 and 19 includes N blocks, (N + 1) blocks or (N +
2) When the synchronization signal data SD of the block is not detected or is wrong, or when the synchronization signal data SD and the address data AD are wrong, the error detection code data E is used.
When D is detected, synchronous output signal data is transmitted as logic "L".

Next, when the synchronizing signal data SD and the address data AD are correct in the video signal portion of the N block and the error detection code data ED is detected as having no error, the address of the video signal portion BD of the (N + 1) block is determined. If it is detected that the error detection code data ED is incorrect, even though the data AD is correct and the correlation position between the address data AD of the N block and the (N + 1) block is correct, it is determined that there is no synchronization signal data SD, and the logic " L "
And sends out the synchronous output signal data.

Next, if the synchronizing signal data SD and the address data AD are correct in the video signal portion of the N block and the error detection code data ED is detected as having no error, the address of the video signal portion BD of the (N + 1) block is determined. If the data AD is correct, but there is no correlation between the address data AD of the N block and the (N + 1) block, and the error detection code data ED is detected in spite of the fact that the synchronization signal data SD is not detected, the pseudo synchronization signal is output. It determines that the data is data, and sends out synchronous output signal data as logic "L".

Next, even when the synchronization signal data SD has an M-bit error in the video signal portion of the N block, the (N + 1) block and the (N + 2) block, the relative relationship between the N block and the (N + 1) block and (N + 1) If the relative relationship between the block and the (N + 2) block is maintained, it is determined that the data is synchronous signal data, and is output as logic "H" to the error point detection circuits 7, 13, and 19, and the other detection signals are output. A signal is output to the output signal forming circuit based on the relationship.

The output signal forming circuit 23 is a synchronous output which rises to logic "H" when the logic of the output signal of the error location determination circuit 7, the error location determination circuit 12, and the error location determination circuit 19 becomes "H". The signal is output from the output terminal 24.

Therefore, the output signal forming circuit 23 sends out a synchronous output signal at the timing each time the synchronous signal data SD arrives at the synchronous signal extracting circuit.

This operation is executed at the timing each time the synchronization signal data SD arrives, and thus a synchronization output signal synchronized with the synchronization signal data SD can be transmitted from the synchronization signal extraction circuit.

Therefore, the address data AD and the synchronizing signal data SD are respectively attached to the image data groups DD of each video signal portion BD, and the error detection code data ED for correcting these are also attached to each image data group DD. I have.
Therefore, the synchronization signal data SD is added to the timing synchronization signal extraction circuit having obtained the error check for the address data.
Has a meaning equivalent to the timing at which it has arrived.

On the other hand, the synchronization signal data S at the N-th address
A data portion between the timing when D arrives at the synchronization signal extraction circuit and the timing when the next (N + 1) th synchronization signal data SD arrives, for example, the same pattern as the pattern of the synchronization signal data SD in the image data group DD. If the data portion is present, the synchronization signal detection circuit 5 outputs a coincidence detection output S2 of logic "H" if it enters the data portion synchronization signal data converter 3S. However, at this time, since the address data AD and the error detection code data ED are not included in the address data conversion section 3A and the address error detection code data conversion section 3P, the logic "H" error detection is performed by the address error detection circuit 5. It can be said that the probability that the signal S1 will be transmitted is extremely small, and therefore, there is no possibility that the output signal forming circuit 23 will actually transmit a logic "H" output signal.

As described above, according to the configuration of FIG. 1, in addition to the detection result of the synchronization signal coincidence detection operation for the synchronization signal data SD, the detection result of the address error detection operation, the detection result of the synchronization signal error detection operation, and the N block And (N + 1)
Since the synchronization output signal is obtained based on the detection result of the correlation between the address data of the blocks, even if the data portion having the same pattern as the synchronization signal data SD exists in the image data group DD, the synchronization is erroneously performed. The probability of detecting signal data can be significantly reduced. Therefore, even if the length of the synchronizing signal data SD is shortened, a synchronizing output signal synchronized with the synchronizing signal data SD can be reliably obtained. In the above description, the present invention is applied to the case of transmitting a digital video signal. The present invention is not limited to this, and can be widely applied to digital signals obtained by inserting synchronization signal data.

[0031]

As described above, according to the present invention, the synchronization signal is extracted based on the detection result of the synchronization signal data, the error detection result of the synchronization signal data, the error detection result of the address, and the correlation between the address data. With this configuration, it is possible to realize an excellent synchronization signal extraction circuit that can easily obtain an extraction operation with extremely low probability of malfunction even when using synchronization signal data having a short data length.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronization signal extracting circuit according to the present invention.

FIG. 2 is a signal waveform diagram showing a general digital data configuration of the synchronization signal extraction circuit.

FIG. 3 is a signal waveform diagram showing a configuration of a data signal used in the synchronization signal extracting circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Holding circuit 3 Serial-parallel conversion circuit 4 Address error detection circuit 5 Synchronization signal detection circuit 6 Synchronization signal error detection circuit 7 Error location discrimination circuit 8 Holding circuit 9 Serial-parallel conversion circuit 10 Address error detection circuit 11 Synchronization signal Detection circuit 12 Synchronization signal error detection circuit 13 Error location determination circuit 14 Holding circuit 15 Serial-parallel conversion circuit 16 Address error detection circuit 17 Synchronization signal detection circuit 18 Synchronization signal error detection circuit 19 Error location determination circuit 20 Relative relationship detection circuit 21 Relative Relationship detection circuit 22 Detection signal generation circuit 23 Output signal formation circuit 24 Output terminal

Claims (1)

(57) [Claims] 1. A word synchronization circuit A for distinguishing one word at a time in serial data of a transmission signal constituted by sequentially inserting synchronization signal data, address data and error detection code data at predetermined time positions of continuous digital data. And detecting whether or not the pattern of the first conversion data matches a predetermined reference pattern based on the first conversion data obtained in correspondence with the synchronization signal data in the word synchronization circuit A. An error occurs in the address data based on a synchronization signal detection circuit B for transmitting a signal and second and third conversion data obtained in the word synchronization circuit A in accordance with the address data and the error detection code data. An address error detection circuit C for detecting whether or not the first and third conversions are performed, and transmitting the detection signal to the word synchronization circuit A. A synchronization signal error detection circuit D for detecting whether an error has occurred in the synchronization signal data based on the data and transmitting a detection signal; an Nth address data and an (N + 1) th address data; And the relative signal detection circuit E detects the relative relationship between the address data even when the synchronization signal detection circuit B detects an M-bit error. A detection signal generation circuit F that determines that the signal is a synchronization signal when the address signal is detected, the address error detection circuit C, the synchronization signal error detection circuit D, and the detection signal generation circuit F
Error location discriminating circuit G which takes in the detection signal of
A synchronizing signal extracting circuit for transmitting a synchronizing output signal based on the logic levels of the discriminating signals of the N error point discriminating circuits.