JP2855651B2 - Continuous pattern detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention detects, for example, digital data communication, regardless of the positional relationship between a transmitted continuous pattern and a frame synchronization pulse. To a continuous pattern detection circuit.

[Conventional technology]

Normally, when it is necessary to transmit and receive monitoring data particularly accurately, for example, when monitoring a transmission line disconnection point due to a lightning strike, the same data pattern is repeatedly and continuously transmitted, and the receiving side transmits this data pattern. In many cases, a method of repeatedly detecting and judging by majority decision is used. in this case,
In a conventional pattern detection circuit, a pulse group having a specific pattern called a frame synchronization pulse is inserted into a data string to be transmitted, so that the receiving side detects this pattern and identifies a frame. Also, the transmitting side inserts a cue bit indicating the start position of transmission data at a specific position for each frame synchronization pulse, and the receiving side detects this cue bit after frame synchronization. Then, a continuous pattern following this is detected and target data is extracted by majority decision.

[Problems to be solved by the invention]

As described above, in the conventional pattern detection circuit, the positional relationship between the cue bit and the frame sync pulse needs to be constant, and when the positional relationship with the frame sync pulse is unspecified, the cue bit is determined. Could not be detected, and therefore the target data could not be extracted.

Also, when an error has occurred in the cueing bit, the cueing position cannot be detected, and therefore, a continuous pattern following this cannot be detected.

Therefore, an object of the present invention is to provide a continuous pattern detection circuit for reliably detecting a continuous pattern even when the positional relationship between a cue bit and a frame synchronization pulse is unspecified or an error has occurred in the cue bit. Is to provide.

[Means for solving the problem]

In the present invention, (i) separating means for separating the multiplexed received data for each channel, (ii) storing means for storing the received data separated by the separating means, and (ii)
i) monitoring means for monitoring a bit string before and after a continuous pattern in which a pattern consisting of a cue bit and a transmission bit appears continuously multiple times among the data bits stored in the storage means; and (iv) a continuous pattern. Cueing bit detection means for detecting a cueing bit indicating the data start position added to each of the constituent patterns by majority decision; and (v) a continuous pattern based on the detection result of this cueing bit detection means and the monitoring result of the monitoring means. The continuous pattern detection circuit is provided with a determination means for specifying the portion by majority decision.

Then, by comprehensively determining the results obtained from the monitoring means, the cueing detection means and the data detection means, the reception data corresponding to the original transmission data is reproduced and output.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to examples.

FIG. 1 shows a continuous pattern detection circuit according to an embodiment of the present invention.

In the continuous pattern detection circuit, a B / U (bipolar / unipolar) conversion unit 11 for converting incoming multiplex reception data 31 from bipolar to unipolar is provided at the preceding stage. A separation unit 12 is connected to the B / U conversion unit 11,
Multiplexed data is separated for each channel.

The pulse pattern generation unit 13 outputs a frame synchronization pulse signal
32 and a sampling clock pulse 33 (FIG. 2a).
It is supplied to. The sampling clock pulse 33 (FIG. 2a) is supplied to the B / U conversion unit 11, the separation unit 12, and each unit from the memory unit 14 to the data reproduction unit 29 described below.

The separation unit 12 is connected to the memory unit 14 and the subsequent bit string detection unit 15. The memory unit 14 is composed of five 8
Separated received data from the separation unit 12 consisting of bit memory
34 (FIG. 2b) are arranged serially in these memories.

All the bits at both ends of the fifth memory 14-5 are connected to the succeeding bit string detection unit 15, and both the bits at both ends of the first memory 14-1 are connected to the preceding bit string detection unit 16. Also,
The first two bits of each of the second to fourth memories 14-2 to 14-4 are connected to the cue bit detection units 17 to 19, respectively, and the remaining six bits are all connected to the data bit string determination unit 21. .

The latter bit string detecting section 15 passes through a counter section 22 and a succeeding bit string monitoring section 23, and the preceding bit string detecting section 16 passes through a counter section 24 and a preceding bit string monitoring section 25.
Connected to 26. Further, all of the above three cueing bit detection units 17 to 19 are connected to a comprehensive judgment unit 26 via a cueing bit judgment unit 27.

The data latch unit 28 is connected to the data bit string determining unit 21 via a data bus 51 having a width of 6 bits.
The data is fetched by a signal 52 from the controller and transmitted to the data reproducing unit 29. The data reproducing section 29 outputs reproduced data 54 (FIG. 2c) reproduced based on the data.

Next, the operation of the continuous pattern detection circuit having the above configuration will be described.

FIG. 2 shows timings for explaining the operation of this circuit.

When the multiplex reception data 31 arrives, the multiplex reception data 31 is first sent to the sampling clock pulse 33 (FIG. 2a) output from the pulse pattern generation unit 13 by the B / U conversion unit 11 shown in FIG.
Is converted to unipolar data at the timing shown in FIG. And a sampling clock pulse as shown in FIG. 2a.
At timings A to H of 33, the separating unit 12 separates the received data into a plurality of separated received data 35 shown in FIG. Here, one of the plurality of separated received data 35 will be described.

As an example, a total of 8 bit pattern “01011001” in which the start bit is “01” and the data to be transmitted is “011001”
Will be described three times in succession, and all other parts will be “1”.

In this case, the separated reception data 34 separated and output from the separation unit 12 is a bit string as shown in the following equation (1) (FIG. 2B).

The separated reception data 34 is stored in the first to fifth
Memory 14-1 to 14-5, the first memory 14-
Starting from Q8 of 1 as a head, a total of 40 bits of 8 bits each are stored.

The pre-stage bit string detection unit 16 constantly monitors the both-end bits of the first memory 14-1 so that the first memory 14-1
The count pulse corresponding to the number of “1” existing in −1 is sent to the counter unit 24.

The counter unit 24 counts this count pulse,
The count number is sent to the preceding bit string monitoring unit 25. As a result, the number of “1” existing in the first 8 bits of the 40-bit bit string is detected.

Similarly, the subsequent-stage bit string detection unit 15 outputs the fifth memory 14-
By constantly monitoring the 5 bits at both ends, a count pulse corresponding to the number of "1" s existing in the fifth memory 14-5 is sent to the counter section 22.

The counter unit 22 counts this count pulse,
The count number is sent to the subsequent bit string monitoring unit 23. As a result, the number of “1” existing in the last 8 bits of the 40-bit bit string is detected.

On the other hand, the cue bit detection units 17 to 19 determine whether or not the first two bits of each of the eight bits of the second to fourth memories 14-2 to 14-4 match the cue bit "01". Always monitor,
All of this information is sent to the cue bit determination unit 27. The cue bit determination unit 27 determines by majority decision whether or not the cue bit “01” has arrived based on these pieces of information.

The remaining six bits of the second to fourth memories 14-2 to 14-4 are all taken into the data bit string determination unit 21, and a majority decision is performed for each bit.

The determination signals 47 to 49 output from the preceding bit string monitoring unit 25, the subsequent bit string monitoring unit 23, and the cue bit determination unit 27 are all input to the overall determination unit 26.

By the way, in this example, as shown in the equation (1), all are "1" except for a total of 24 bits of three 8-bit continuous patterns. Therefore, at the time when this 24-bit pattern is exactly present in the second to fourth memories 14-2 to 14-4, the first and fifth memories 14-14
1 and 14-5 are all "1". At this time, the first two bits of each of the second to fourth memories 14-2 to 14-4 are all "01".

Thus, the first and fifth memories 14-1, 14-5
The number of "1" s in each of the eight and the second
When the leading two bits of each of the fourth to fourth memories 14-2 to 14-4 coincide with two or more "01" by majority decision, a data latch signal 52 is transmitted from the comprehensive determination unit 26 to the data latch unit. . As a result, the data latch unit 28 fetches in parallel the 6-bit data determined to be majority by the data bit string determination unit 21 at that time. And
The 6-bit data is serially output as reproduced data 54 by the data reproducing unit 29.

As described above, the continuous pattern is detected from the received data regardless of the positional relationship with the frame synchronization pulse, and regardless of the presence / absence of the error of the cue bit,
From this, the target data can be reproduced and output with high accuracy.

Further, in this embodiment, if the number of repetitions of the continuous pattern to be transmitted and received is further increased, there is an advantage that the accuracy of majority decision can be improved.

〔The invention's effect〕

As described above, according to the present invention, the frame synchronization is detected by detecting a bit sequence before and after a continuous pattern in which the pattern consisting of the cue bit and the transmission bit, in which the positional relationship with the frame synchronization pulse is uncertain, appears multiple times continuously. A continuous pattern can be detected from received data without being affected by the positional relationship with the pulse, and the detection is not restricted by the received data. In addition, since the cue bits added to each of the patterns constituting these continuous patterns are detected and not only the target data bit string but also the cue bits are determined by majority decision, there is no error in the cue bits. It has the advantage of being able to detect even

Furthermore, if the number of repetitions of the continuous pattern to be transmitted / received is further increased, the accuracy of the majority decision can be improved, and the data can be detected more accurately.

[Brief description of the drawings]

The drawings are for explaining one embodiment of the present invention, wherein FIG. 1 is a circuit diagram showing a continuous pattern detection circuit,
FIG. 2 is various timing charts for explaining the operation of the continuous pattern detection circuit. 11 B / U conversion unit, 12 separation unit, 13 pulse pattern generation unit, 14 memory unit, 15 bit sequence detection unit at the rear stage, 16 bit sequence detection unit at the front stage, 17 to 19 Cue bit detector, 21… Data bit string determiner, 22, 24… Counter, 23… Post-bit string monitor, 25… Previous bit string monitor, 26… Comprehensive determiner, 27… Cue Bit determination unit, 28 Data latch unit 29 Data reproduction unit

Claims (1)

(57) [Claims] 1. Separating means for separating multiplexed received data for each channel, storing means for storing the received data separated by the separating means, and among data bits stored in the storing means, Monitoring means for monitoring a bit string before and after a continuous pattern in which a pattern consisting of a cueing bit and a transmission bit appears multiple times continuously; cueing indicating a data start position added to each of the patterns constituting the continuous pattern Cueing bit detecting means for detecting bits by majority decision, and judging means for specifying a continuous pattern portion by majority decision based on the detection result of the cueing bit detecting means and the monitoring result of the monitoring means. Continuous pattern detection circuit.