JPS6212226A - Method of detecting dissidence of synchronization pattern - Google Patents

Method of detecting dissidence of synchronization pattern

Info

Publication number
JPS6212226A
JPS6212226A JP60150105A JP15010585A JPS6212226A JP S6212226 A JPS6212226 A JP S6212226A JP 60150105 A JP60150105 A JP 60150105A JP 15010585 A JP15010585 A JP 15010585A JP S6212226 A JPS6212226 A JP S6212226A
Authority
JP
Japan
Prior art keywords
synchronization
frame
circuit
dissident
dissidence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60150105A
Other languages
Japanese (ja)
Inventor
Toyohiko Watanabe
豊彦 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60150105A priority Critical patent/JPS6212226A/en
Publication of JPS6212226A publication Critical patent/JPS6212226A/en
Pending legal-status Critical Current

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  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To decrease the time for detecting out of synchronism without increasing the mis-frame rate by detecting the dissidence between a frame synchronizing pulse and a frame synchronization pattern in a communication system having plural frame synchronization pulses. CONSTITUTION:A synchronization pattern generating circuit 3 is reset by a head of the frame and outputs sequentially a synchronization bit at each sub frame. A dissidence detector 1 compares outputs of a synchronizing pulse extracting circuit 2 and the synchronizing pattern generating circuit 3, and when they are dissident, a dissident pulse is outputted. A dissident discrimination circuit 4 is reset at a counter by a head of the frame, the dissident pulse is counted and when the number of the dissident pulse exceeds a threshold value, it is informed to a synchronization protection circuit 5 as the frame dissidence. The synchronization protection circuit 5 counts the number of dissident frames and when the number exceeds a threshold value, it is discriminated as out of synchronism. Thus, the dissidence discrimination circuit 4 itself has a capability of synchronization protection, number of stages of the post stage of synchronization protection circuit 5 is reduced and the time for detecting out of synchronism is decreased.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、ＬＡＮ、ＩＮＳ等に利用するデジタルデータ
伝送装置のフレーム同期回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a frame synchronization circuit for a digital data transmission device used in LAN, INS, etc.

（従来の技術） 第３図は従来の同期保護装置の構成を示している。同図
において１１は同期パルス抽出回路で、同期パターン発
生回路１２と共に不一致検出回路１３につながり、１４
は前方の同期保護回路である。(Prior Art) FIG. 3 shows the configuration of a conventional synchronization protection device. In the figure, 11 is a synchronization pulse extraction circuit, which is connected to a mismatch detection circuit 13 together with a synchronization pattern generation circuit 12;
is the forward synchronization protection circuit.

不一致検出回路１３はコンパレータで、同期パルス抽出
回路１１からパラレルに抽出される同期パルス列と同期
パターン発生回路１２から出力される同期パターンとを
比較して、不一致、一致パルスとして出力する。同期保
護回路１４は不一致、一致パルスをそれぞれカウントし
て、不一致パルスの数がしきい値を越えると同期外れと
判断する。The mismatch detection circuit 13 is a comparator that compares the synchronization pulse train extracted in parallel from the synchronization pulse extraction circuit 11 with the synchronization pattern output from the synchronization pattern generation circuit 12, and outputs a mismatch or match pulse. The synchronization protection circuit 14 counts the number of mismatched pulses and the match pulses, and determines that the synchronization is out of synchronization when the number of mismatched pulses exceeds a threshold value.

このように、従来の同期保護装置でも、不一致パルスの
数がしきい値を越えない範囲でミスフレームから同期を
保護することができる。In this way, even with the conventional synchronization protection device, synchronization can be protected from misframes within a range in which the number of mismatched pulses does not exceed a threshold.

（発明が解決しようとする問題点） 上記従来の同期保護装置では、じよう乱によるミスフレ
ーム率を小さくするためには、同期保護段数を大きくし
なければならず、そのため、同期外れ検出時間が長大な
ものとなる欠点があった。(Problems to be Solved by the Invention) In the conventional synchronization protection device described above, in order to reduce the misframe rate due to disturbance, the number of synchronization protection stages must be increased. It had a major drawback.

本発明の目的は、従来の欠゛点を解消し、ミスフレーム
率を上げることなく、同期外れ検出時間を短かくするこ
とのできる同期保護装置を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization protection device that eliminates the conventional drawbacks and can shorten the out-of-synchronization detection time without increasing the misframe rate.

（問題点を解決するための手段） 本発明の同期パターン不一致検出方法は、フレ−ム同期
方式を用い、複数のフレーム同期パルスを有する通信方
式において、そのフレーム同期パルスとフレーム同期パ
ターンとの不一致を検出するものである。(Means for Solving the Problems) The synchronization pattern mismatch detection method of the present invention uses a frame synchronization method, and in a communication system having a plurality of frame synchronization pulses, a mismatch between the frame synchronization pulse and the frame synchronization pattern is detected. This is to detect.

（作　用） 本発明によれば、同期パターンに冗長性を与えることに
よって、同期保護段数をふやすことなくミスフレーム率
を小さくすることができ、同期外れ検出時間を短縮する
ことができる。(Function) According to the present invention, by providing redundancy to the synchronization pattern, the misframe rate can be reduced without increasing the number of synchronization protection stages, and the out-of-synchronization detection time can be shortened.

（実施例） 本発明の一実施例を第１図ないし第２図に基づいて説明
する。(Example) An example of the present invention will be described based on FIGS. 1 and 2.

第１図は本発明の同期パターン不一致検出方法の構成を
示すものである。FIG. 1 shows the configuration of the synchronization pattern mismatch detection method of the present invention.

同図において、１は不一致検出器で同期パルス抽出回路
２と同期パターン発生回路３の出力を入力とする。４は
不一致判定回路で、不一致検出器１の出力を入力とし、
同期保護回路５に接続されている。In the figure, reference numeral 1 denotes a mismatch detector which receives the outputs of the synchronization pulse extraction circuit 2 and the synchronization pattern generation circuit 3 as inputs. 4 is a discrepancy judgment circuit which receives the output of discrepancy detector 1 as input;
It is connected to the synchronization protection circuit 5.

次に、実施例の動作について説明する。Next, the operation of the embodiment will be explained.

第２図に示すようなフレーム構成において、同期パター
ン発生回路３は、フレーム頭でリセットされて、サブフ
レームごとに同期ビットを順次出力する。不一致検出器
１は、同期パルス抽出回路２と、同期パターン発生回路
３との出力を比較して、不一致ならば不一致パルスを出
力する。In the frame configuration shown in FIG. 2, the synchronization pattern generation circuit 3 is reset at the beginning of the frame and sequentially outputs synchronization bits for each subframe. The mismatch detector 1 compares the outputs of the synchronization pulse extraction circuit 2 and the synchronization pattern generation circuit 3, and if they do not match, outputs a mismatch pulse.

不一致判定回路４はカウンタでフレームの頭でリセット
され、不一致パルスをカウントする。不一致パルスの数
がしきい値を越えるとフレーム不一致として、同期保護
回路５に知らせる。The mismatch determination circuit 4 is a counter that is reset at the beginning of a frame and counts mismatch pulses. When the number of mismatched pulses exceeds a threshold value, it is notified to the synchronization protection circuit 5 as a frame mismatch.

同期保護回路５はフレーム不一致の数をカウントして、
その数がしきい値を越えたら、同期外れと判断する。The synchronization protection circuit 5 counts the number of frame mismatches and
If the number exceeds the threshold, it is determined that the synchronization is out of synchronization.

たとえば、同期パターンを（０１１１０００１）とした
とき、同期パルスが（０１０１０００１）ならば、フレ
ーム不一致とはせず、（０１０１１００１）ならば、フ
レーム不一致とする。For example, when the synchronization pattern is (01110001), if the synchronization pulse is (01010001), it will not be considered a frame mismatch, but if it is (01011001), it will be considered a frame mismatch.

このように、上記実施例によれば、不一致判定回路４自
体も同期保護の能力を持つことになり、後段の同期保護
回路５の段数をへらすことができ、したがって、同期外
れ検出時間を短かくすることができる。In this way, according to the above embodiment, the mismatch determination circuit 4 itself has the capability of synchronization protection, and the number of stages of the synchronization protection circuit 5 in the subsequent stage can be reduced. Therefore, the out-of-synchronization detection time can be shortened. can do.

（発明の効果） 本発明によれば、不一致判定回路に同期保護の特性を持
たせたものであり、保護特性の選択の自由度を拡げる利
点がある。(Effects of the Invention) According to the present invention, the inconsistency determination circuit is provided with synchronization protection characteristics, which has the advantage of increasing the degree of freedom in selecting protection characteristics.

さらに、同じミスフレーム率ならば、従来の方法より同
期外れ検出時間を短縮することができる効果がある。Furthermore, if the misframe rate is the same, the out-of-sync detection time can be reduced compared to the conventional method.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例における同期保護装置のブロ
ック図、第２図は同フレーム構成図、第３図は従来の同
期保護装置のブロック図である。 １　・・・不一致検出器、　２，１１・・・同期パルス
抽出回路、　３，１２・・・同期パターン発生回路。 ４　・・・不一致判定回路、　５，１４・・・同期保護
回路、１３・・・不一致検出回路。 特許出願人　松下電器産業株式会社 第１図 第２図FIG. 1 is a block diagram of a synchronization protection device according to an embodiment of the present invention, FIG. 2 is a frame configuration diagram of the same, and FIG. 3 is a block diagram of a conventional synchronization protection device. 1... Discrepancy detector, 2, 11... Synchronization pulse extraction circuit, 3, 12... Synchronization pattern generation circuit. 4... Mismatch determination circuit, 5, 14... Synchronization protection circuit, 13... Mismatch detection circuit. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] フレーム同期方式を用い、複数のフレーム同期パルスを
有する通信方式において、該フレーム同期パルスとフレ
ーム同期パターンとの不一致を検出することを特徴とす
る同期パターン不一致検出方法。1. A synchronization pattern mismatch detection method comprising detecting mismatch between a frame synchronization pulse and a frame synchronization pattern in a communication system using a frame synchronization method and having a plurality of frame synchronization pulses.
JP60150105A 1985-07-10 1985-07-10 Method of detecting dissidence of synchronization pattern Pending JPS6212226A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60150105A JPS6212226A (en) 1985-07-10 1985-07-10 Method of detecting dissidence of synchronization pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60150105A JPS6212226A (en) 1985-07-10 1985-07-10 Method of detecting dissidence of synchronization pattern

Publications (1)

Publication Number Publication Date
JPS6212226A true JPS6212226A (en) 1987-01-21

Family

ID=15489608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60150105A Pending JPS6212226A (en) 1985-07-10 1985-07-10 Method of detecting dissidence of synchronization pattern

Country Status (1)

Country Link
JP (1) JPS6212226A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02211729A (en) * 1989-02-10 1990-08-23 Fujitsu Ltd Synchronization detecting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02211729A (en) * 1989-02-10 1990-08-23 Fujitsu Ltd Synchronization detecting circuit

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