JPH02211729A - Synchronization detecting circuit - Google Patents

Abstract

PURPOSE:To prevent a correct frame pattern from being judged to be erroneous even at the time of the occurrence of error in a frame pulse by resetting a collation pulse generating part for frame pattern collation by the reset pulse which is inputted once per several frames. CONSTITUTION:Frame bits are extracted from an inputted data string by a frame bit extracting means 10 and are collated with a pulse generated from a collation pulse generating means 20 by a collating means 30' to discriminate synchronization or asynchronization. A reset means 40 is operated by the reset pulse, which is inputted once per several frames, to reset the collation pulse generating means 20. Thus, a correct frame pattern is not erroneously discriminated as error.

Description

[Detailed Description of the Invention] [Summary] Synchronization (t
Regarding the synchronization detection circuit whose frame pattern is 110 alternating pulses, an error occurred in the frame pulse by resetting the verification pulse generator for frame pattern verification with a reset pulse that is input once every few frames. The purpose is to provide a synchronization detection circuit that does not judge a correct frame pattern as an error even when the frame pattern is correct. A verification pulse is generated by a verification pulse generation means, a verification means for verifying the frame bit extracted by the frame bit extracting means, and a pulse generated by the verification pulse generation means, and a reset pulse inputted once every few frames. 1. A synchronization detection circuit comprising: reset means for resetting the generation means.

[Industrial application field]

The present invention relates to a synchronization detection circuit in which the frame pattern of a synchronization signal for establishing frame synchronization in digital communication is 170 alternating pulses.

In digital multiplex communication, the transmitting side arranges the signals of each channel to be multiplexed in order and synchronously, adds and inserts a synchronization pulse with a specific pattern for each period, and transmits the signals, and the receiving side uses the frame periodicity. The time slot of each channel is identified by checking the pulse train every time and detecting the frame synchronization pulse.

In such a frame synchronization system, due to a one-bit error in a frame pulse, other normal data may be determined to be an error, and the data in between becomes invalid data.

Therefore, a synchronization detection circuit that does not invalidate normal data is required.

[Prior Art] FIG. 4 is a block diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating a time chart of the conventional example.

In the conventional example shown in FIG. 4, a frame bit extraction unit 11 consisting of a 10-stage shift register extracts frame bits from an input data string, and a clock signal and the output of an inverter llb that inverts frame pulses are input.
A negative OR circuit (hereinafter referred to as a NOR circuit) lla whose output is input to the clock terminal of the frame bit extraction unit 11
, a D flip-flop circuit (hereinafter referred to as DFF) which uses a frame pulse as a clock input and generates an I10 alternating pulse by inverting its state every time a frame pulse is input.
circuit) 21, 10 exclusive NOR circuits B (hereinafter referred to as E
(referred to as X-NOR circuit) 30 to 39, two five-man power AND circuits (hereinafter referred to as AND circuit) 51 and 52 for synchronization protection, and OR circuit (hereinafter referred to as OR circuit) 53, synchronization , two DFFs that output asynchronous information
It is equipped with circuits 61 and 62.

In the above configuration, the frame bit extraction unit 11 extracts frame bits from the data string, and the I10 alternating pulse generated from the frame pulse and the 10 EX-NOR circuits 30 to 39 extract the frame bits as 10 parallel data.
Verify pulses simultaneously.

The collated results are input to a five-person AND circuit 51,52. Here, in any of the 5-man power AND circuits 51.
When an error of more than one bit is input, two-person OR
By setting the output of the circuit 53 to "0", synchronization is protected.

The DFFIli62 generates a pulse that is a frame pulse delayed by half the clock frequency, and this pulse is
It is input as a clock to the FF circuit 61, and outputs the output of the OR circuit 53, that is, whether it is in a synchronous state or an asynchronous state.

FIG. 5 is a time chart of the operation of this circuit.

3 indicates the state of the frame pulse, and it is assumed that one bit is missing as shown in the figure.

■ is a frame bit in the data, and the 110 alternation is performed correctly.

■ is the state of the frame bits extracted by the frame bit extraction unit 11. Even if the frame bits in the data are 110 alternating correctly, "1" for two frames is left due to missing frame pulses. The process continues for a certain period of time, and from then on, frame bits are correctly extracted in accordance with the frame pulse.

■ is a 110-alternating pulse for verification generated by the DFF circuit 21, and it is 110-alternating due to the frame pulse, so if one bit of the frame pulse is missing, the state of 110 will not be reversed at the time of the missing bit, and the next frame Since there is a 110th alternation with a deviation of 1 pulse from
When the outputs of the D circuits 51 and 52 become "0", it is output as out of synchronization.

[Problem to be solved by the invention]

As shown in the time chart of the conventional example mentioned above, when a frame pulse is missing, even if the frame bits in the data are in the correct 110 alternation, the 110 alternation of the DFF circuit 21 that generates the verification pulse is shifted, resulting in an error. , and it is detected as out of synchronization.

The present invention provides synchronization that does not determine that a correct frame pattern is an error even when an error occurs in a frame pulse by resetting the verification pulse generator for verifying frame patterns with a reset pulse that is input once every few frames. The purpose is to provide a detection circuit.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

In the block diagram of the principle of the present invention shown in FIG. 1, 10 is a frame bit extracting means for extracting frame bits from an input data string, and 20 is a collation unit that generates 110 alternating pulses for collating frame patterns. A pulse generating means; 30' is a collation means for collating the frame bits extracted by the frame bit extracting means 10 with the pulses generated by the collation pulse generating means 20; 40 is a reset pulse inputted once every few frames; The verification pulse generating means 20
This is a reset means for resetting, and by providing such a means, it is a means to solve this problem.

[For production]

Frame bit extraction means 10 from the input data string
By extracting frame bits and comparing them with the pulses generated by the checking pulse generating means 20 and the checking means 30', it is determined whether the bits are synchronized or not.

During this operation, if a frame pulse is missing, the 110 alternation of the reference pulse generating means 20 will shift, so even if the frame bits in the data string are correctly 110 alternating,
It will be incorrectly determined as asynchronous.

By activating the reset means 40 and resetting the verification pulse generation means 20 with a reset pulse inputted once every several frames, it is possible to prevent incorrect determination of a correct frame pattern as an error.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating the present invention in detail, and FIG. 3 is a diagram illustrating a time chart of an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG. 2 uses a frame bit extraction unit 11 having the same contents as explained in FIG. 4 as the frame bit extraction means 10 explained in FIG. 1, a NOR circuit 11a1, an inverter 1! b1 An OFF circuit 21 having the same contents as explained in FIG. 4 as the verification pulse generation means 20, EX-NOR circuits 30 to 39 having the same contents as explained in FIG. 4 as the verification means 30', and a reset circuit. As the means 40, a multi-frame pulse is input.
FF circuit 41, negative logic output of DFF circuit 41, and DF
An AND circuit 42 which receives the output of the F circuit 61 and resets the DFF circuit 21 with its output, and an AND circuit 51 and 52 having the same contents as explained in FIG. 4 and an OR circuit as a synchronization protection circuit. This is an example in which the circuit 53 and the output circuit are composed of DFF circuits 61 and 62 having the same contents as explained in FIG. 4.

Frame bits are extracted by the frame bit extraction unit 11 of the above-mentioned circuit, and compared with the 110 alternating pulses generated by the DFF circuit 21 by the EX-NOR circuits 30 to 39.
The operation of outputting with synchronization protection applied by the D circuits 51 and 52 and the OR circuit 53 is the same as that explained in FIG. The DFF circuit 21 is reset.

That is, the inverted output obtained by delaying the multi-frame pulse by one crotch and the output of the DFF circuit 61 are input to the AND circuit 42, and each time the multi-frame pulse arrives, the DFF circuit 2I
By setting the clear terminal CR to "O" level, it is reset and the correct I10 alternating pulse is generated from the next frame pulse, so normal data is not wasted and all data can be used effectively. It becomes possible.

FIG. 3 shows the above operation in a time chart.

(a) is a multi-frame pulse. In this example, the multi-frame pulse is used as a reset pulse, and the multi-frame pulse arrives once every 6 frame pulses.

(b) shows the state of a frame pulse, with one bit missing.

(C) is a frame bit in the data, and 11a alternation is performed correctly.

(d) is a frame bit extracted by the frame bit extraction unit 11. Since one bit of the frame pulse is missing, "1" continues for two frames at that position.

(e) is a 110 alternating pulse generated by the DFF circuit 21, and since the values of (d) and (e) are different, it is an error.#) The outputs of the EX-NOR circuits 30 to 39 are "0" However, the DFF circuit 21 is reset by the next multi-frame pulse, and since the number of synchronization protection stages is less than the number of synchronization protection stages of the AND circuits 51 and 52, it is not output as an out-of-synchronization signal.

That is, even if one bit is missing in the frame pulse, if the frame bit in the data is normal, the data is considered correct and can be used effectively.

〔Effect of the invention〕

According to the present invention as described above, in a synchronization detection circuit that uses 110 alternating pulses as frame pattern pulses, by resetting the verification pulse generator with a reset pulse that is input once every several frames, the frame pulse Even if a 1-bit error occurs, all normal data can be used effectively.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a time chart of an embodiment of the present invention, and FIG. 4 is a conventional block diagram. A block diagram illustrating an example, and FIG. 5 a diagram illustrating a time chart of a conventional example are shown, respectively. In the figure, 0 is a frame bit extraction means, 11 is a frame bit extraction section, 11a is a NOR circuit, 11b is an inverter, 20 is a verification pulse generation means, 21.41.61.62 is a DFF circuit, and 30' is a verification means , 30 to 39 are EX-NOR circuits, 40 is a reset means, 42, 51, and 52 are AND circuits, and 53 is an OR circuit, respectively. Block diagram for explaining the present invention in detail 1 Block diagram for explaining the present invention in detail Figure 4 Block diagram for explaining the conventional example

Claims (1)

[Claims] In a synchronization detection circuit in which a synchronization signal for frame synchronization in digital communication has a frame pattern of 1/0 alternation, frame bit extraction means ( 10), a verification pulse generation means (20) that generates a 1/0 alternating pulse for verifying frame patterns, and a verification pulse generation means (20) that generates a frame bit extracted by the frame bit extraction means (10) and the verification pulse generation means (20). ), and a reset means (40) for resetting the verification pulse generating means (20) with a reset pulse inputted once every several frames. A synchronization detection circuit featuring: