JPH04354421A - Error parity recovery circuit - Google Patents

Abstract

PURPOSE:To attain accurate data communication at all times by recovering a parity added to a data having an error and sending the resulting data with respect to the error parity recovery circuit in a multiplexer of the digital communication system. CONSTITUTION:The system is provided with a parity check means detecting a parity added to a received data, a parity arithmetic means 101 applying arithmetic operation to the parity of the received data, an error parity recovery means 102 comparing an output from the parity check means with an output from the parity arithmetic means and outputting an error parity when they are dissident, and a parity addition means 103 adding the error parity outputted from the error parity recovery means to the received data and outputting the result to implement accurate data communication at all times.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a parity check and parity generation circuit in a multiplexing device of a digital communication system, and more particularly to an error parity regeneration circuit that adds error parity to received data and outputs it when error parity is detected. Regarding.

0002

[Prior Art] In conventional digital communication systems,
As shown in FIG. 4, the TDM device 20 of the A station may add parity to transmission data and transmit the data to the C station via the B station and the B station. As shown in FIG. 5, the parity check circuit 22 of the TDM device 21 in the B station includes a parity check section 22a that detects parity added to received data and displays an alarm when error parity is detected; The parity calculation unit 22b includes a parity calculation unit 22b that calculates the parity of received data, and a parity MUX unit 22c that adds the calculated parity to the received data.

0003

[Problem to be Solved by the Invention] By the way, in the system shown in FIG. 4, when data is sent from station A to station C via station B, a failure occurs on the line from station A to station B, and the data is lost. Suppose an error occurs. In this case, the B station performs a parity check and calculates the parity of the data in which the error occurred. Then, the calculated parity is added to the data in which the error has occurred, and the data is transmitted.

[0004] Since the C station receives the data in which the error has occurred and the parity obtained by calculating the data,
This means that the C station has received data to which parity indicating normality has been added. In other words, although the data received by the C station is different from the data transmitted by the A station, by passing through the B station, the data has normal parity.

SUMMARY OF THE INVENTION An object of the present invention is to provide an error parity regeneration circuit that adds parity to data so that accurate data communication can always be performed by regenerating the parity added to data in which an error has occurred. .

[0006]

[Means for Solving the Problems] As shown in FIG. 1, the error parity recovery circuit of the present invention includes a parity check means 100 for detecting parity added to received data, and a parity check means 100 for calculating the parity of the received data. a parity calculation means 101 that compares the output from the parity check means 100 and the output from the parity calculation means 101, and an error parity reproduction means 102 that outputs error parity if the results do not match; It is characterized by comprising a parity addition means 103 which adds error parity outputted from the parity reproduction means 102 and outputs the result.

[0007]

[Operation] The error parity detected by the parity check means 100 and the parity calculated by the parity calculation means 101 are compared by the error parity reproduction means 102. As a result of the comparison, if the error parity and the calculated parity do not match, the error parity reproducing means 102 outputs the error parity to the parity adding means 103. Since the parity adding means 103 adds error parity to the received data and outputs it, it is possible to accurately transmit data error information.

[0008]

[Examples] Examples of the present invention will be described in detail below with reference to the drawings.
The present invention is not limited to the following examples.

FIG. 2 is an electrical circuit diagram of an embodiment of the present invention. In the figure, 1 is a parity check section, which includes a JK flip-flop 1a, a D flip-flop 1b, and an EX-O
It is composed of an R gate 1c. JK flip flop 1
Received data is input to the J and K terminals of a. This input received data is sent to the check counter 2.
The output is counted by a signal latched by the D flip-flop 3 at the timing of the internal clock CLK. The signal output from the JK flip-flop 1a is latched by the D flip-flop 1b at the timing of the synchronization clock SCK for data communication, and compared with the received parity by the EX-OR gate 1c. If they match, it is determined that the parity is correct, and if they do not match, it is determined that the parity is an error parity.

Reference numeral 4 denotes a parity calculation section, which is composed of a JK flip-flop 4a and a D flip-flop 4b. J
Received data output from the parity MUX section 5, which is parity adding means, is input to the J and K terminals of the K flip-flop 4a. The received data is processed by the calculation counter 6.
After inverting the output of C with NOT gate 7, internal clock C
Latch it with D flip-flop 8 at the timing of LK,
The count is performed by a signal obtained by calculating the internal clock CLK inverted by the NOT gate 9 and the output signal of the D flip-flop 8 by the NAND gate 10. The output signal of the JK flip-flop 4a is latched by the D flip-flop 4b at the timing of the synchronous clock SCK, and is output to the EX-OR gate 11, which is error parity reproducing means.

The EX-OR gate 11 compares the parity detected by the parity check section 1 with the parity obtained by actually calculating the received data. If the results do not match, that is, if a parity error alarm occurs, a signal corresponding to the error parity is input to the parity MUX unit 5. Parity MUX
The unit 5 inverts the input signal, adds it to the received data, and outputs it to the line.

FIG. 3 is a timing chart showing the operation of the electric circuit of the embodiment. Parity checking is performed in the order of frames of multi-frame data. In the figure, parity bit P1 of multiframe 1 is latched by a parity bit latch clock. This latched parity bit P1 becomes the reception parity S1 input to the circuit of FIG. Signal S2 is the output signal of D flip-flop 3. According to the timing of this signal S2, the data of multi-frame 1 is calculated by the parity check section 1, and the signal S3 which is the calculation result is outputted from the D flip-flop 1b. As mentioned above, the signal S
3 are compared by EX-OR gate 1c to check parity.

Signal S4 is the output of parity calculation section 4. The signal S4 is compared with the output signal from the parity check unit 1 at the EX-OR gate 11, and when a parity error occurs, the error parity is reproduced and the parity M
Output to the UX section 5. Note that a D flip-flop may be used instead of the JK flip-flop used in the above embodiment.

[0014]

[Effects of the Invention] As explained above, according to the present invention,
This has the effect of preventing data in which an error has occurred from being erroneously received as normal data by a receiving station that receives the data next time. Therefore, accurate data communication can be performed, which greatly contributes to improving the performance of parity check and its arithmetic circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention.

FIG. 2 is an electrical circuit diagram of an embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the electric circuit of the embodiment.

FIG. 4 is a block diagram showing a usage pattern in a conventional digital communication system.

FIG. 5 is a block diagram of a conventional electric circuit.

[Explanation of symbols]

100 Parity check means 101 Parity calculation means 102 Error parity regeneration means 103 Parity addition means

Claims (1)

[Claims] 1. A parity check means (100) for detecting parity added to received data, and a parity calculation means (100) for calculating parity of the received data.
1), error parity reproducing means (102) for comparing the output from the parity checking means (100) and the output from the parity calculation means (101) and outputting error parity if the results do not match; Parity adding means (103) for adding and outputting error parity output from the error parity reproducing means (102) to data
An error parity regeneration circuit consisting of.