JPH0399540A - Synchronizing clock circuit - Google Patents

Abstract

PURPOSE:To detect the step out, the frequency deviation, the pulse stop, the pulse trouble, or the like between master and slave clock pulses by comparing master and slave clock pulses with each other to detect the phase difference and performing a prescribed processing. CONSTITUTION:In a phase difference detecting means 1, a D-FF circuit 3 from which the master clock pulse is inputted to a terminal CP has the output terminal the inverse of Q directly connected to an input terminal D, and the clock pulse obtained by frequency division of the master clock pulse is outputted from a terminal Q. The output pulse of the terminal Q and the slave clock pulse are inputted to an exclusive OR circuit 4 and are operated, and the operation result is inputted to a shift register SFR 6. An inverter 5 of a phase difference output holding means 2 inverts the master clock pulse to input the negative-logic clock to the SFR 6, and the SFR 6 temporarily holds the output of the circuit 4. The SFR 6 sets all of outputs to code '1' if the slave clock pulse is deviated from the master clock pulse by a 1/2 period or longer, and the SFR 6 sets all of outputs to code '0' if it is deviated by an extent shorter than the 1/2 period, thus detecting the step out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock circuit for synchronizing communication lines using multiplexed communication channels.

[Conventional technology]

Conventionally, synchronization clock circuits do not detect failures such as a two-phase shift in the frequency and pulse width of synchronization clock pulses, and extract the synchronization clock pulses sent from the communication partner from the communication line and directly use their own clock pulses. It was incorporated into the circuit.

[Problem to be solved by the invention]

The conventional synchronization clock circuit described above is configured to take in the clock pulses extracted from the communication line directly into its own circuit, so when a lock pulse is received and a failure occurs due to the influence of the communication line, the circuit There is a problem in that when an abnormality occurs due to an internal failure, it becomes a major failure and the communication system may become paralyzed.

An object of the present invention is to provide a synchronization clock circuit that solves the above problems.

[Means to solve the problem]

The synchronization clock circuit according to the present invention includes a phase difference detection means for inputting a main clock pulse and a slave clock pulse, detecting and outputting a mutual phase difference, and a phase difference output holding means for temporarily suspending the output of the phase difference detection means. means and have.

[Effect]

The synchronization clock circuit having the above means maintains the phase difference output when inputting the main clock pulse and the slave clock pulse to be sent to the phase difference detection means and outputting predetermined phase difference information to the phase difference output holding means. By extracting the information held by the means and performing predetermined processing, it is possible to detect out-of-synchronization between the main clock pulse and slave clock pulse, frequency shift, pulse stop, and pulse width disturbance.

〔Example〕

Next, the present invention will be explained with reference to FIGS. 1 and 2.

FIG. 1 is a circuit diagram showing an embodiment of the main part of the present invention, and FIG. 2 is a time chart showing an example of waveforms in the main part of FIG.

FIG. 1 is a circuit diagram showing an example of a clock pulse failure detection circuit that detects a failure by comparing a slave clock pulse with a main clock pulse, and includes a phase difference detection means 1 and a phase difference output holding means 2. The phase difference detection means l is a D-type flip 7
The 0-tub (hereinafter referred to as -FF) circuit 3 and the exclusive OR circuit 4, and the phase difference output holding means 2 are connected to an inverter (INV).
) 5 and a send register (SFR) 6, respectively.

In the phase difference detection means 1, a D-FF circuit 3 which inputs the main clock pulse shown in FIG.
A clock pulse indicating the country is output from terminal Q. Terminal Q
The output pulses of are at the same frequency as the slave clock pulses. The exclusive OR circuit 4 inputs the frequency-divided output pulse of the terminal Q and the dependent clock pulse, performs an operation, and connects the operation result to the terminal SIN of the send register (SFR) 6.

The inverter (INV) 5 of the phase difference output holding means 2 inverts the main clock pulse, forms it into a negative logic clock, and connects it to the terminal CP of the sending register (SFR) 6. The send register (SFR) 6 temporarily holds the output data of the exclusive OR circuit 4 using the negative logic clock of the inverter (INV) 5.

As shown in Figure 2, if the slave clock pulse deviates from the main clock pulse by 1/2 period or more, the send register (SFR>6 sets all outputs to code 1.Similarly, 1/2 period When the difference is within the range, the send register (SFR) 6 sets all outputs to code 0, so that synchronization deviation can be detected by the output of code 1.

The sending register (SFR) 6 compares the slave clock pulse with the main clock pulse and detects frequency deviation, clock pulse interruption, pulse ratio failure, etc. by holding code 0/1 or code 1/0.

Therefore, a hold in the send register (SFR) 6 other than code O means a clock pulse failure, which can be detected.

〔Effect of the invention〕

As explained above, the present invention detects abnormalities and failures in clock pulses by comparing the main clock pulse and slave clock pulse, detecting the phase difference, and performing predetermined processing. There are effects that can be prevented as much as possible.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the main part of the present invention, and FIG.
The figure is a time chart showing an example of the waveform of the main part of FIG. 1. DESCRIPTION OF SYMBOLS 1... Phase difference detection means, 3... Phase difference output holding means, 3... D-type flip-flop (D-FF) circuit, 4
...Exclusive OR circuit, 5...Inverter (INV
)6... Send register (SFR).

Claims (1)

[Claims] In a clock circuit for synchronizing a communication line using a multiplexed communication path, there is a phase difference detection means that inputs a main clock pulse and a slave clock pulse, detects and outputs a mutual phase difference, and temporarily suspends the output of this phase difference detection means. 1. A synchronization clock circuit comprising phase difference output holding means.