JP3411197B2 - Line termination equipment - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line terminating device, and more particularly to a line terminating device for establishing frame synchronization by using a time division multiplex transmission system.

A line terminating device for terminating a subscriber line carries out data transmission with an upper station using a highway which is a serial data bus. The data on the serial data bus constitutes a multi-frame composed of a plurality of frames time-divided for each channel.

Since the line terminating device inputs and outputs only the data of the channel corresponding to its own station from the multi-frame,
It is necessary to monitor the continuity of the frame by the frame synchronization circuit based on the channel clock sent to the own station and establish the multi-frame synchronization at the same time as the frame synchronization.

FIG. 9 shows line terminators 20-1 to 20-32 connected to respective subscriber lines (not shown). Of these, the line terminators 20-1 to 20-16 are Serial data IN via serial data bus SDB1
Bus connection so that 1 and OUT1 are commonly input and output,
Similarly, the line terminators 20-17 to 20-32 transmit the serial data IN2, O through the serial data bus SDB2.
It is connected to the bus so that the UT2 is commonly input and output.

Further, the line terminators 20-1 and 20-17.
The channel clock CHCK1 extracted from the serial data OUT1 and OUT2 at the upper station is input to the line terminal devices 20-2 and 20-1 in the same manner.
Channel clocks CHCK2 to 16 are input to the line termination devices 20 to 16 and 20 to 32, respectively.

FIG. 10 shows a frame configuration example on the serial data bus SDB and a timing example of the channel clock CHCK. FIG. 10A shows serial data IN1, OUT1, IN2, OUT2 on the bus SDB. It is shown that one frame is composed of data of channels CH1-1 to CH16-1.

FIG. 2B shows a channel clock CHCK.
1 is serial data IN1, OUT1, IN2, OUT
The data of the channel CH1-1 of the second channel is output at the timing of the beginning of the data.
6 is output at the timing of the data of the serial data channels CH2-1 to 16-1.

Then, as an example, the line terminating device 20
-1 is CH1- in the frame of the serial data OUT1, IN1 at the timing of the channel clock CHCK1.
Only one data is input or output, respectively.

FIG. 11 shows a multi-frame configuration example in which the six frames shown in FIG. 10 (1) are collected, and the data input to the line terminating device 20-1 (see FIG. 9) is a multi-frame. The data 1 to 6 of the channels CH1-1 to CH1-6 are sequentially input / output from each of the frames 1 to 6 at the timing of the channel clock CHCK1 (see FIG. 10B).

In such a line terminating device, it is necessary to monitor the continuity of frames and establish frame synchronization for the entire multiframe.

[0010]

2. Description of the Related Art FIG. 12 shows each line termination device 20- of FIG.
1 to 20-32 are included in the line terminator (hereinafter, indicated by reference numeral "20"). This line terminator 2
0 indicates serial data OUT1 (or OUT2: hereinafter, O
Called UT. ) Is input, a frame pattern is extracted to establish frame synchronization, data addressed to the local station is extracted and output as received data.

The line terminating device 20 includes a received data capture circuit 1, a received data latch circuit 2, a received data register circuit 3, an internal clock generation circuit 8, a channel clock detection circuit 10, a timer counter 11, and a frame synchronization circuit 4. (Broken line part).

The received data latch circuit 1 receives the serial data OUT and the channel clock CHCK, outputs the data D1 for one channel, and receives the received data latch circuit 2.
Inputs the data D1, the channel clock CHCK, and the frame number N from the frame synchronization circuit 4, and outputs the data D2.

The reception data register circuit 3 receives the data D2.
And the internal clock CK from the internal clock detection circuit 10,
The frame number N and the frame determination result J from the frame synchronization circuit 4 are input and the received data is output.

The frame synchronization circuit 4 comprises a frame counter circuit 5, a multi-frame determination circuit 6 and a multi-frame synchronization detection / protection circuit 7.

The multiframe determination circuit 6 and the multiframe synchronization detection / protection circuit 7 constitute a multiframe synchronization circuit 12.

The channel clock CHCK is commonly input to the frame counter circuit 5, the internal clock generation circuit 8 and the channel clock loss detection circuit 10.

The frame counter circuit 5 has a frame number N.
And the internal clock generation circuit 8 outputs the internal clock CK
, The channel clock loss detection circuit 10 outputs a channel clock loss detection signal, and the timer counter 11 outputs the reset signal R in response to the detection signal. The reset signal R is a reset signal for the entire frame synchronization circuit 4.

The multi-frame judgment circuit 6 receives the frame identification number (signal), the frame number N and the internal clock CK from the reception data latch circuit 2 and outputs the judgment result J.

The multi-frame sync detection / protection circuit 7 is
The determination result J of establishment of multiframe synchronization, the frame number N, and the internal clock CK are input, and the synchronization state S is output. This synchronization state S is given to the frame counter circuit 5 as an initialization signal.

FIG. 13 shows an operation example of the line terminating device 20 including the frame synchronization circuit 4 of FIG. 12, and in this example, the channel clock CHCK is always input in a normal cycle.

The multi-frames have frame numbers 1 to
It is composed of 6 consecutive 6 frames.

The reception data acquisition circuit 1 receives the channel clock CHCK from the serial data OUT ((2) in the figure).
Data of one channel and a frame identification number are extracted at the timing of ((1) in FIG. 13), the serial data is converted into parallel data and output as data D1 ((4) in FIG. 13).

The frame counter circuit 5 sequentially outputs the frame number N ((3) in the figure) having the same value as the frame identification number as the count values "1" to "6".

The reception data latch circuit 2 sequentially latches in parallel the data D1 (CH1-1 to CH1-6) and the frame identification number which the reception data capturing circuit 1 outputs at the timing of the channel clock CHCK, and 6 The data is output as frame data D2 ((5) in the figure). The received data latch circuit 2 extracts only the frame identification number portion of the data D1 from the frame identification number and outputs it to the multi-frame determination circuit 6.

In the multi-frame synchronization circuit 12, the frame number N is the final frame number "6" and the frame identification numbers 1 to 6 are continuous at the timing of the internal clock CK (the frame identification number of the data latch circuit 2). When the output corresponding to is a predetermined continuous multi-frame pattern), it is determined that the multi-frames are "continuous" and the determination result J of "0/1" is output.

That is, the phase of the multi-frame input from the serial data bus SDB (frame identification number)
And the phase of the frame counter circuit 5 (frame number N)
To determine the continuity of frames.

Further, the multi-frame synchronization circuit 12 establishes multi-frame synchronization continuously several times or more based on the judgment result J and the frame number N in order to eliminate the case where synchronization seems to be established by chance. After performing the front or rear protection for detecting, the synchronization state S indicating whether or not the synchronization is being established is output.

That is, a predetermined pattern is output to the output terminal corresponding to the frame identification number of the received data latch circuit 2.
The case where the output is continuously performed a predetermined number of times or more in a predetermined cycle (determined by the frame number indicated by the frame counter circuit) is regarded as “establishing synchronization”.

Then, the frame counter circuit 5 inputs the synchronization state S indicating that synchronization is being established, and continues the counting operation.

The internal clock CK may be regarded as having the same period as the channel clock CHCK as long as the channel clock CHCK is input to the internal clock generating circuit 8 at a normal period as described later.

The reception data register circuit 3 also outputs the normal data D2 for one multiframe at the timing of the internal clock CK based on the judgment result J and the frame number N when the multiframe synchronization is being established. It is stored and output as received data ((8) in the figure).

The establishment of multi-frame synchronization can be monitored by the above series of operations, but if the continuity is lost, the frame synchronization is re-acquired and the continuity is monitored again.

In the above operation example, the channel clock CH
Although the period of CK has made an example of variation, Ji Yanerukurokku CHCK a description will be given of the operation when it becomes off.

In the above operation example, is the channel clock C
The example in which the HCK is input in the normal cycle has been described, but the operation when the channel clock CHCK is disconnected will be described.

When the channel clock loss detection circuit 10, the timer counter 11, and the internal clock generation circuit 8 are not provided, the reception data acquisition circuit 1, the reception data latch circuit 2,
And the frame counter 5 uses the channel clock CHCK.
Is stopped, the operation is stopped, and the data D1,
D2 and the frame number N are maintained.

Further, since the internal clock CK of FIG. 12 becomes the channel clock CHCK, the frame synchronization circuit 4 cannot detect the loss of synchronization and outputs the erroneous state signal S indicating "synchronization is being established". Then, until the channel clock CHCK is input, the line cannot be taken in and the data cannot be taken in.

In the worst case, since the line is disconnected for a long time, it is necessary to detect this disconnection.

Therefore, the channel clock loss detection circuit 10 and the timer counter 11 shown in FIG. 12 are provided, and the channel clock loss detection circuit 10 outputs to the timer counter 11 that the channel clock CHCK is disconnected. To do.

The timer / counter 11 has an internal clock C.
K is counted, a reset signal R is output when a predetermined count value is reached, and the frame counter circuit 5 and the multi-frame synchronization circuit 12 are returned to the initial state.

Further, in order to prevent the operation of the line terminator from being interrupted due to the disconnection of the channel clock CHCK, the internal clock C is used as a substitute clock for the channel clock CHCK.
With K, the reception data acquisition circuit 1, the reception data latch circuit 2,
Also, the frame counter circuit 5 is supplied and operated.

FIG. 14 shows the internal clock generating circuit 8 in FIG. 12, which is composed of an OR circuit 8a, a counter 8b and a decoder 8c.

The counter 8b counts the master clock MCLK input to the input terminal CLK and outputs it at the output terminal Q.
Outputs the count value from the decoder 8c, and the decoder 8c
When the count value of b becomes a value corresponding to the cycle of the channel clock CHCK, the load signal L is output.

The OR circuit 8a outputs a load instruction LD to the counter 8b when the load signal L or the channel clock CHCK is input. The counter 8b is set to an initial value (“0” when the counter 8b counts up) in response to the load instruction LD, and the master clock MC
Count LK.

As a result, the counter 8b is normally initialized by the channel clock CHCK. When the channel clock CHCK is cut off, the counter 8b
Will be initialized by the load signal L output from the decoder 8c at the timing when the count value becomes a value corresponding to the cycle of the channel clock CHCK.

Therefore, even when the channel clock CHCK is disconnected, the internal clock CK can be taken out from the output terminal Q of the counter 8b as a substitute clock for the channel clock CHCK.

FIG. 15 shows the internal clock generation circuit 8 described above.
3 shows the phases of the channel clock CHCK input to the internal clock CK and the created internal clock CK.

FIG. 1A shows the channel clock CHCK.
Is input in a normal cycle, and the pulse p1 of the internal clock CK corresponding to the pulse P1 of the channel clock CHCK is output at the same timing as the next pulse P2. Thereafter, similarly, the pulses p2 to p6 corresponding to the pulses P2 to P6 are output with a delay of one cycle of the channel clock CHCK.

FIG. 2B shows the case where the channel clock CHCK is input in a cycle shorter than the normal cycle, and when the pulse P4 next to the pulse P3 of the channel clock CHCK is input in a short cycle, the counter 8b. Is initially set to "0" by the pulse P4, the internal clock pulse p3 (shown by the broken line) is not output, and the pulse p4 is output after a normal cycle from the timing of the pulse P4.

Further, the pulse P6 is followed by the pulses P7 and P8.
Is input continuously in a short cycle, pulses p6 and p7
Is not output, and the pulse p8 is output after a normal period from the timing of the pulse P8.

FIG. 3C shows the case where the channel clock CHCK is input with a period longer than the normal period and shorter than twice the normal period, which is the pulse P3 next to the pulse P2.
Is input in a long cycle, the pulse p2 next to the pulse p1 is output in a normal cycle.

Further, since the counter 8b is initialized to "0" by the pulse P3, the pulse p3 changes to the pulse P3.
Is output after the normal cycle has passed.

Similarly, when pulses P5 and P6 having a long period are generated consecutively after the pulse P4, the pulses p4 and p4 are generated.
5 and p6 are output in the normal cycle from the pulses P4, P5 and P6, respectively.

FIG. 4D shows the case where the channel clock CHCK is input at a cycle longer than twice the normal cycle. This corresponds to, for example, the case where the pulses P3 to P6 between the pulses P2 and P7 of the channel clock CHCK are missing.

The counter 8b is an LD for the pulses P3 to P6 of the channel clock CHCK via the OR circuit 8a.
Instead of an instruction, the load signal L output from the decoder 8c in a normal cycle is sequentially initialized to "0" to be in a free-run state, and pulses p2 to p6 are sequentially generated in a normal cycle from the pulse p1 of the internal clock. To do.

As described above, when the cycle of the channel clock CHCK is normal, the phases of the channel clock CHCK and the internal clock CK match, and when the cycle is not normal, the internal clock CK of the internal clock CK is located at a position corresponding to the channel clock CHCK. A dropout or a phase shift between the channel clock CHCK and the internal clock CK occurs.

On the other hand, when the channel clock CHCK is cut off, the internal clock CK is the channel clock CHCK.
It can be seen that it can be used as a substitute clock for the channel clock CHCK, which is generated at the position where is missing.

[0057]

[Problems to be Solved by the Invention]

(1) In the above-mentioned conventional example, there is a problem that the channel clock loss detection circuit 10 and the timer / counter 11 are required on the assumption that the channel clock is in a disconnected state.

(2) Further, in the above-mentioned conventional example, the case where the channel clock has a normal cycle and the case where the channel clock is disconnected have been described. However, a case where the cycle of the channel clock CHCK fluctuates into long / short cycles is also conceivable. .

This will be described with reference to FIGS. 16 to 20. Note that (1) to (4b) in each figure correspond to each other.

FIG. 16 shows an operation example (1) of the frame counter circuit 5 when the channel clock CHCK is generated in a short cycle, corresponding to FIG. 15 (2).

FIG. 2B shows the frame identification number included in the serial data, and FIG. 3C shows the internal clock CK output from the frame counter circuit 5 to which the channel clock CHCK of FIG. 1A is input. Is shown.

FIG. 4A shows the frame counter circuit 5.
Shows the count value when the channel clock SCK of FIG. 1A is counted, and FIG. 4B shows the count value when the internal clock CK is provisionally counted in place of the channel clock CHCK.

In this operation example, the count value of the frame counter circuit 5 ((4) in the figure) is the frame identification number of the serial data ((4a) in the figure) only when the channel clock CHCK is counted ((4a) in the figure). It turns out that it becomes the same as (2)).

FIG. 17 corresponds to FIG. 15 (3) and shows an operation example (2) of the frame counter circuit 5 when the channel clock CHCK is generated in a cycle longer than the normal cycle and less than two cycles. Is shown.

In this operation example, the frame counter circuit 5
The count value ((4) in the figure) is the channel clock CH
It can be seen that no matter which of the CK and the internal clock CK is counted ((4a), (4b) in the figure), the frame identification number of the serial data ((2) in the figure) is the same.

FIG. 18 corresponds to FIG. 15 (4) and shows an operation example of the frame counter circuit 5 when the channel clock CHCK is generated in a cycle (long cycle) having a length twice or more the normal cycle (long cycle). 3) is shown.

In this operation example, the frame counter circuit 5
It can be seen that the count value ((4) in the figure) becomes the same as the frame identification number ((2) in the figure) of the serial data only when the internal clock CK is counted ((4b) in the figure).

FIG. 19 shows an operation example (4) of the frame counter circuit 5 when the channel clock CHCK changes from a short cycle to a long cycle.

In this operation example, the frame counter circuit 5
The count value ((4) in the figure) is the channel clock CH
It can be seen that only when the CK is counted ((4a) in the figure), the frame identification number of the serial data ((2) in the figure) is the same.

FIG. 20 shows an operation example (5) of the frame counter circuit 5 when the channel clock CHCK changes from a long cycle to a short cycle.

In this operation example, the frame counter circuit 5
The count value ((4) in the figure) is the channel clock CH
It can be seen that only when the CK is counted ((4a) in the figure), the frame identification number of the serial data ((2) in the figure) is the same.

The above is summarized as follows on the premise that the frame identification number of the serial data is incremented in the cycle of the channel clock CHCK.

When the frame counter circuit 5 counts with the channel clock CHCK and the cycle is a long cycle (pulse break) of two cycles or more as shown in FIG. 18, the count value ((4a) in the figure) indicates the frame identification. It does not match the number ((2) in the figure).

On the other hand, when the frame counter circuit 5 counts with the internal clock CK, the count value ((4b) in the figure) is the frame identification number (see the same figure) as shown in FIGS. 16, 19 and 20. Does not match (2)).

Therefore, the frame counter circuit does not show a normal count value (frame number N), and even if normal data comes, it is erroneously recognized as an abnormal frame.

Therefore, according to the present invention, a reception data fetch circuit for fetching one frame of channel data and a frame identification number from serial data constituting a multi-frame with a channel clock, and the channel data and the frame identification number are sequentially latched. A multi-frame data for one multi-frame and a reception data latch circuit for holding the frame identification number, an internal clock generation circuit for generating an internal clock having the same period as the normal period of the channel clock, and the channel clock or A line provided with a frame counter circuit that counts the internal clock and outputs a frame number, and a multiframe synchronization circuit that determines the synchronization state of the multiframe based on the frame identification number for one multiframe and the frame number. Channel at the terminating device Locks without requiring any special reset circuit corresponding to the case where the cross-sectional and frame counter circuit even if the cycle of the channel clock is changed to an object to ensure that show the same count value as the frame identification number.

[0077]

[Means for Solving the Problems]

[1] In order to solve the above problems, in the line terminating device according to the present invention, when the reception data latch circuit holds the multiframe data for one multiframe and the frame identification number by the internal clock and the synchronization state is lost. The multi-frame synchronization circuit can initialize the frame counter circuit.

That is, the received data fetch circuit fetches the channel data and the frame identification number at the timing of the channel clock, and the received data latch circuit fetches the channel data and the frame identification number fetched by the received data fetch circuit at the timing of the internal clock. Latch and hold serially.

When the channel clock is cut off, the reception data fetch circuit stops fetching the serial data and the frame identification number and keeps the data.

However, the reception data latch circuit is
The same data held at the timing of the internal clock is repeatedly latched for the number of frames of the multi-frame and held in parallel.

Therefore, the multi-frame synchronization circuit determines that there is a discrepancy between the two based on the frame identification number of one multi-frame held by the reception data latch circuit and the frame number from the frame counter circuit, that is, there is no continuity and loss of synchronization. The judgment is made and the frame counter circuit is initialized.

As a result, the line terminating device does not require a circuit for detecting the disconnection state of the channel clock CHCK.

The frame counter circuit 5 may count the frame number with either the channel clock or the internal clock.

[0084] Then, providing the mask circuit for fetching the received data acquisition circuit only channel data and the frame identification number when the channel clock and the internal clock is input at the same time.

That is, the channel clock and the internal clock have the same phase only when the channel clock is input in a normal cycle. Therefore, the received data acquisition circuit
Channel data and a frame identification number are fetched from serial data only in the case of normal in-phase.

On the other hand, the reception data capturing circuit does not capture serial data when the channel clock has an abnormal period such as a short period or a long period or is interrupted.

Then, the reception data latch circuit sequentially latches and holds the data and the frame identification number from the reception data receiving circuit at the timing of the internal clock.

[0088] Hereinafter, in the same way, since the frame counter circuit is initialized, the line terminal devices, the channel clock C
Therefore, a circuit for specifically detecting the break of HCK is not required.

[0089]

[0090] The [2], the line terminal devices according to the present invention, Oite the above invention (1), the frame counter circuit, said on the basis of the determination circuit and the determination result the cycle of the channel clock The operation of counting the frame counter can be performed by the channel clock or the internal clock.

That is, the decision circuit decides the length of the cycle of the channel clock and, based on the decision result, increments the frame counter by the channel clock or the internal clock, so that the frame counter circuit selects an appropriate clock. It becomes possible.

[ 3 ] Furthermore, in the line terminator according to the present invention, in the above-mentioned present invention [ 2 ], the determination circuit has a cycle of the channel clock that is a normal cycle, a short cycle, or less than or twice the normal cycle. It is also possible to provide a table for determining the above cycle and selecting the channel clock or the internal clock.

That is, the cycle of the channel clock is
In the case of a normal cycle, if it is shorter than the normal cycle, it is divided into a long cycle of less than 2 cycles than the normal cycle and a long cycle of 2 cycles or more.

Then, the frame counter circuit counts with the channel clock or the internal clock in the case of, based on the table, counts with the channel clock in the case of, and performs the internal clock clock in the case of.
In this case, the internal clock can be selected.

A case where the frame counter circuit selects the clock to be counted from the channel clock or the internal clock as described above will be described with reference to FIGS. 16 to 20.

FIG. 16 shows a case where the channel clock CHCK ((1) in the same figure) has a short cycle. When the frame counter circuit 5 counts the channel clock ((4a) in the figure), the frame number as the count value ((4a) in the figure) becomes the same as the frame identification number ((2) in the figure).

FIG. 17 shows a case where the channel clock CHCK ((1) in the same figure) has a period of less than two normal periods. The frame counter circuit 5 first counts the internal clock CK ((3) in the figure), and if it does not count the channel clock CHCK ((1) in the figure) generated next, the frame identification number ((2) in the figure). ) And the frame number ((4b) in the figure) are the same.

FIG. 18 shows a case where the channel clock CHCK ((1) in the figure) has a normal cycle of two or more cycles. The frame counter circuit 5 has an internal clock C.
Regardless of whether K ((3) in the figure) or CHCK ((1) in the figure) is counted, the frame number and the frame identification number (same as (4a) and (4b) in the figure) are counted values. It becomes the same as the figure (2)).

FIG. 19 shows a case where the channel clock CHCK ((1) in the same figure) changes from a short cycle to a long cycle. The frame counter circuit 5 uses the channel clock C
When HCK ((1) in the figure) is counted, the frame number as the count value ((4a) in the figure) and the frame identification number ((2) in the figure) become the same.

FIG. 20 shows a case in which the channel clock CHCK ((1) in the figure) changes from a long cycle to a short cycle. The frame counter circuit 5 uses the channel clock C
When counting with HCK ((1) in the figure), the frame number as the count value ((4a) in the figure) and the frame identification number ((2) in the figure) become the same.

By thus selecting the clocks to be counted according to the cycle of the channel clock, the frame counter circuit can count the frame number having the same value as the frame identification number of the serial data.

Therefore, after the channel clock recovers from the temporary abnormal cycle to the normal cycle, the frame counter circuit shows the frame number corresponding to the frame identification number, so that the synchronization is not lost.

[0103] [4] Further, in the present invention, Oite the above invention (1), the multi-frame synchronization circuit are respectively synchronized until the predetermined time has elapsed from the time of establishment or synchronous when it becomes out of synchronization When the state of being out of sync or establishing synchronization continues, it is preferable to determine that the synchronization is out of synchronization or being in synchronization.

That is, when the synchronization is lost due to the fluctuation of the cycle of the channel clock or the clock loss, or when the synchronization is returned to the normal period and the synchronization is established, it is determined that the synchronization is not temporarily lost or not established. For confirmation, it is possible to determine whether or not the synchronization is lost or the synchronization established state continues for a predetermined time.

Therefore, a temporary abnormal period or clock loss is not regarded as a loss of synchronization, and a temporary synchronization establishment state is not regarded as a synchronization establishment state.

[0106]

FIG. 1 shows a configuration embodiment (1) of a line terminating device according to the present invention. The difference from the conventional configuration shown in FIG. That is, the internal clock CK is input to the input terminal CLK instead of the channel clock CHCK.

Also, the channel clock loss detection circuit 10 and the timer / counter 11 are removed, and the reset signal R is not applied to the frame counter circuit 5 and the multi-frame synchronization circuit 12, which is another difference.

Further, it is different that the channel clock CHCK and the internal clock CK are input to the frame counter circuit 5. It should be noted that any of these clocks may be used in this embodiment.

In operation, the channel clock CHCK
Is input to the line terminating device 20, the reception data capturing circuit 1 captures serial data at the timing of the channel clock CHCK.

Then, the reception data latch circuit 2 receives the data D1 from the reception data receiving circuit 1 with the internal clock CK having the same phase as the channel clock CHCK, and the data corresponding to the frame numbers 1 to 6 and the continuous multi-frame. The patterns of the frame identification numbers 1 to 6 indicating the sex are output.

Thereafter, by the same operation as that of the conventional line terminating device 20 shown in FIG. 12, multiframe determination and detection protection are carried out to detect the establishment state of multiframe synchronization.

On the other hand, when the channel clock CHCK is cut off, the reception data receiving circuit 1 outputs the serial data OU.
Data cannot be fetched from T, and the previously fetched data for one frame is retained. Therefore, the reception data latch circuit 2 can detect the loss of frame synchronization without latching the pattern indicating the continuous frame identification number with the internal clock CK.

After that, the multi-frame determination circuit 6 and the multi-frame synchronization detection / protection circuit 7 detect "out-of-synchronization of multi-frames" in a normal operation.

Therefore, unlike the conventional line terminator 20 shown in FIG. 12, the channel clock loss detection circuit 10 and the timer / counter 11 are not particularly required.

FIG. 2 shows a configuration embodiment (2) of the line terminating device according to the present invention. The difference from the embodiment (1) shown in FIG. 1 is that the clock of the reception data receiving circuit 1 is different. That is, a clock obtained by masking the channel clock CHCK with the internal clock CK is input to the input terminal CLK by using the AND circuit 9 as a mask circuit.

In operation, the point different from the embodiment (1) of FIG. 1 is that the channel clock CHCK and the internal clock CK have the same phase only when the channel clock CHCK having a normal cycle is input, so that the received data Capture circuit 1
Means that the serial data OUT can be taken in.

Thereafter, the same operation as that of the embodiment (1) is performed to detect the establishment state of multiframe synchronization. When the channel clock CHCK is cut off, the synchronization state S indicating “out of synchronization” is output as in the embodiment (1).

Therefore, the channel clock loss detection circuit 10 and the timer / counter 11 are not particularly required as in the case of FIG.

FIG. 3 shows the frame counter circuit 5 (see FIG. 1) according to the present invention. The selection signal generating circuit 5 is shown in FIG.
a, a selection circuit 5b, and a frame counter 5c.

The channel clock CHCK and the internal clock CK are commonly input to the selection signal generation circuit 5a and the selection circuit 5b, respectively, and the master clock MCLK is further input to the selection signal generation circuit 5a to output the selection signal QSET. .

The selection circuit 5b receives the selection signal QSET at the input terminal S and outputs the increment pulse P from the terminal OUT. The frame counter 5c receives the increment pulse P and the master clock MCLK at the input terminals EN and MCLK, respectively, and outputs the frame number N from the terminal Q.

The selection signal generation circuit 5a operates in the operation table T
Based on 1, the selection signal QSET is output. This selection signal QSET is generated when only the internal clock CK is generated.
It is set to "0" and is set to "1" when the channel clock CHCK or the internal clock CK is generated.

The selection circuit 5b outputs the increment pulse P according to the logical value of the selection signal QSET input to the input terminal S based on the operation table T2. When the input increment pulse P is "1", the frame counter 5c increments in synchronization with the rising edge of the master clock MCLK.

The frame counter 5c has a cycle of the number of frames included in the multi-frame (for example, when the number of frames is 6,
The counting operation is repeated in 1 to 6). However, a circuit for performing this repetitive counting operation is not shown in FIG.

The logical values of the operation tables T1 and T2 are shown in positive logic, and the selection signal Q of the table T1 is used.
SET = Q0 means “hold the previous state”.

The channel clock CHCK and the internal clock CK are clocks synchronized with the falling edge of the master clock MCLK, and their pulse width is one cycle of the master clock.

4 to 8 are time charts showing operation examples (1) to (5) in the frame counter circuit 5 of the present invention shown in FIG. This time chart diagram is
Tables T1 and T2 are shown in more detail.

In particular, FIG. 5 (ii) is different from the figures of other operation examples in order to show the timing operation in more detail, the selection signal Q
A time chart diagram of SET, master clock MCLK, and count value of the frame counter 5c is added.

In the figure, the channel clock CHCK
Are displayed in negative logic, and the internal clock CK and the selection signal Q
SET and increment pulse P are displayed in positive logic.

The numbers attached to the respective pulses of the channel clock CHCK, the internal clock CK and the increment pulse P are the frame identification number of the serial data OUT corresponding to the channel clock CHCK and the frame number to which the internal clock CK should correspond. , And the frame number N, which is the count value of the counter 5c.

The increment pal P indicates the position where the frame counter 5c is incremented.

The increment pulse I1 shown in FIG. 5 (ii) and the increment pulse I shown in FIG. 6 (i).
2, I3 are the pulses generated in the circuit design, and
i) frame counter 5 as shown at timing t5
The timing when c is incremented is the master clock M
It is ignored because it is the rising edge of CLK.

The increment operation of the frame counter circuit 5 is summarized as follows. : When both the channel clock CHCK and the internal clock CK are not present (see timings t2 and t2 ′ in FIG. 5 (ii)), no increment is performed.

When there is only the internal clock CK (see the same timing t4), the increment is made. After the case of :, if only the channel clock CHCK is generated (see the same timing t5) (condition 4 of table T2), the increment is not performed.

After the case other than (: ,,,): When only the channel clock CK is generated (see the same timing t3), the increment is performed. : When both the channel clock CHCK and the internal clock are present (see the same timings t1, t1 ', t6), increment.

After :, the channel clock CH
When only CK occurs (part 2) (see timing t4 in FIG. 8 (i)), the increment is performed.

The time chart operations of FIGS. 4 to 8 will be described below in association with the above cases 1 to.

FIG. 4 (i) shows the channel clock CHCK.
Shows a case where occurs at timing t3 once in a long cycle. The frame counter circuit 5 has a timing t
Since 1 corresponds to the case of, it is incremented, and timing t2 corresponds to the case of, so it is incremented.

Then, the frame counter circuit 5 does not increment because the timing t3 after the case is corresponding to the case of, and increments because the timing t4 corresponds to the case.

That is, the frame counter 5c has the timing t corresponding to the internal clock CK at the timing t2.
Since it is not known at what timing the channel clock CHCK of 3 will occur at the timing t2, the internal clock CK at the timing t2 is first counted.

Then, the channel clock CHCK generated independently at the next timing t3 is set in advance at the timing t2.
Since the substitute internal clock CK is counted in, it is not counted.

Therefore, at the timing t4 when the cycle of the channel clock CHCK returns to normal, the frame counter 5c indicated by the frame identification number "4" and the increment pulse corresponding to the channel clock CHCK.
It can be seen that they match the frame number “4”, which is the count value of.

[0143] The figure (ii) shows the channel clock CHCK.
Shows a case where the error occurs once at a timing t2 in a short cycle. The frame counter circuit 5 increments because it corresponds to the timing t1 and increments because it corresponds to the timing t2, and increments because it corresponds to the timing t3.

That is, at timing t2, the channel clock CHCK is counted. Then, the internal clock CK corresponding to this channel clock CHCK is not generated. Therefore, the timing t4 when the normal cycle is restored
In, it can be seen that the frame identification number “4” corresponding to the channel clock CHCK and the frame number “4” indicated by the increment pulse P match.

FIG. 5 (i) shows the channel clock CHCK.
Shows a case where occurs at a long cycle once at timing t3 and then once at a short cycle at timing t4. The internal clock at the timing t2 and the channel clock at the timing t3 are processed at timings t2 and t3 in FIG.
The same as the case of, and the timing t3 corresponds to the case of.

Since the frame counter circuit 5 corresponds to the case of timing t4 after the case of, the frame counter circuit 5 is incremented, and since it corresponds to the case of timing t5, it is incremented.

The frame identification number "5" and the ink frame number "5" at the timing t5 when returning to the normal cycle.
It can be seen that is consistent with.

FIG. 5 (ii) shows the channel clock CHCK.
Shows a case where occurs in a short cycle at timing t3 and then occurs in a long cycle at timing t5.

Timing t1, t2, t1 ', t3, t
4, t2 ′, t5, and t6 are respectively,
,,,, are shown. Therefore, the frame counter 5c causes the timings t1, t1 ′, t3, and
Incremented at t4, t6, timing t2, t
You can see that it is not incremented by 2 '.

Also in this operation example, the frame number and the frame identification number, which are the counting results of the frame counter circuit 5, match at the timing t6 when the normal cycle is returned.

FIG. 6I shows the channel clock CHCK.
Shows the case where the long cycle occurs twice consecutively at the timings t3 and t5.

The frame counter circuit 5 receives the timing t.
5 (i) at 2, t3 and timings t4, t5.
The same counting operation as the timings t2 and t3 is repeated twice. Then, since the timings t1 and t6 are the case of, the increment is made.

As a result, it can be seen that the frame identification number "5" and the frame number "5" at the timing t6 when returning to the normal cycle match.

FIG. 6 (ii) shows the channel clock CHCK.
Indicates that a short cycle occurs three times consecutively at timings t2 and t3.

The frame counter circuit 5 performs the increment operation at the timing t2 similarly to the operation at the timing t2 in FIG. 4 (ii), and then performs the increment because it corresponds to the case of the timing t3, and when the timing t4 is. Since it corresponds, increment is performed.

As a result, it can be seen that the frame identification number "5" and the frame number "5" at the timing t4 when returning to the normal cycle match.

FIGS. 7 (i) to 8 (ii) show an operation example in the case where the channel clock CHCK is continuously omitted at the timings t2 and t3, and FIG. 7 (i) shows that the channel clock CHCK is At timing t4, a case is shown in which the occurrence is three times as long as the normal cycle.

The frame counter circuit 5 receives the timing t.
1, t2, t3, t4, t5 are respectively ...
, So that the increment is made at each timing t1 to t5.

Channel clock CHCK is timing t
Despite the omission at 2 and t3, the timing t5 when the serial data OUT returns to the normal cycle provided that the frame identification number is normally sent.
Frame identification number "6" and frame number "6"
It can be seen that is consistent with.

FIG. 7 (ii) shows the channel clock CHCK.
However, the channel clock CH that should be generated at the timing t4
This is the case where CK occurs at timing t5.

The frame counter circuit 5 has a timing t.
1 to t6 are after ,,,, respectively. Therefore, it is incremented except at the timing t5.

As a result, the frame identification number "6" and the frame number "6" at the timing t6 when the normal cycle is returned are provided under the condition that the frame identification number is sent as in the case of FIG. 7 (i). You can see that they match.

FIG. 8 (i) shows the channel clock CHCK.
Shows the case where the channel clock CHCK of timing t4 of a short cycle is generated from timing t3.

The frame counter circuit 5 receives the timing t.
Since 1 to t5 are after each of ,,,, respectively, they are incremented except at the timing t5.

As a result, similar to FIG. 7 (i), the frame identification number "6" and the frame number "6" at the timing t5 when returning to the normal cycle match with each other under the condition of the frame identification number. I understand.

The difference between the channel pulse P1 shown in FIG. 7 (ii) and the channel pulse P2 shown in FIG. 8 (i) is that the pulse P1 is closer to the timing t4 than the timing t6 and the pulse P2 is the timing. That is far from t3.

FIG. 8 (ii) shows a case where the same clock and pulse are generated at the same timings t1 to t5 as in the case of FIG. 7 (i).
The frame identification number corresponding to the channel clock SCH of 5 is the frame identification number “5” shown in FIG.
Unlike "6", they are "3" and "4", respectively.

Therefore, at the timing t5 when the channel clock CHCK returns to the normal cycle, the channel clock C
The frame identification number "4" corresponding to HCK and the frame number "6" corresponding to the increment pulse are different. At this timing t5, the continuity of multiframe synchronization is not established, and it is determined that synchronization is lost.

According to the above operation example, the frame counter circuit 5 divides the cycle of the channel clock SCH into a normal cycle, a short cycle, a long cycle, and an interruption, and selects the channel clock SCH or the internal clock corresponding to each. As a result, the frame identification number and the frame number N which is the count value of the frame counter circuit can be matched as long as the frame identification number corresponding to the channel clock on the serial data OUT is not shifted.

Therefore, in any of the cases of FIGS. 4 (i) to 8 (i), the cycle of the channel clock CHCK is short,
After returning from the long period and the normal state from the disconnected state, the frame identification number and the frame number match, so that the synchronization is not lost at the time of restoration.

On the other hand, in the case of FIG. 8 (ii), when the normal cycle is restored, there is a possibility that the frame identification number and the frame number do not match and the synchronization is lost.

Thereafter, when the frame counter circuit 5 of the line terminating device 20 of FIG. 2 has the circuit configuration shown in FIG. 3,
The operation of the line terminating device 20 will be described by classifying it according to the cycle in which the channel clock CHCK is generated.

When the channel clock CHCK is generated in a cycle shorter than the normal cycle. The counter 8b (see FIG. 14) that creates the internal clock CK is
Since the initial value is loaded by the channel clock CHCK before the pulse is output, it is not output.

Therefore, the channel clock CHCK is masked by the internal clock CK and the received data fetch circuit 1 (see FIG. 1) cannot fetch frame data. On the other hand, the frame counter 5c (see FIG. 3) has a channel clock C
Only HCK counts the continuity of frames as a frame number.

When the states of the received data fetching circuit 1 and the frame counter 5c are continuous, the received data latch circuit 2 sequentially stores the fixed data of the received data fetching circuit 1, so that the continuity of frames is increased. Cannot hold the data indicating that the line terminator is out of synchronization due to the operation of the multi-frame synchronization circuit 12.

When the channel clock CHCK is generated with a longer period than the normal period and less than two periods.

First, when the channel clock CHCK occurs after the timing when the internal clock CK is generated and before the timing when the free-running internal clock CK is generated, the frame counter 5c that counts the continuity of the frame is The counting operation is performed by the internal clock CK (see Tables 1 and 2 in FIG. 3). At this time, since the channel clock CHCK is not generated,
The reception data capturing circuit cannot capture data. After that,
Out-of-sync is detected as in the operation of.

On the other hand, at the timing when the channel clock CHCK is input after the internal clock CK, the frame counter 5c does not perform the counting operation, and the reception data capturing circuit 1 does not capture the data.

Then, at the timing when the channel clock CHCK is input, the state of waiting for the initial channel clock CHCK and the internal clock CK is restored. Therefore, if this state continues, loss of synchronism is detected by the operation of the multi-frame synchronizing circuit 12 as in the case.

When the channel clock CHCK is generated in a long cycle of two or more normal cycles. That is, when the channel clock SCH is "disconnected".

If the channel clock CHCK is not input even if the internal clock CK is output twice, the operation is the same as when the channel pulse comes in a long cycle of less than 2 cycles than the normal cycle of. The difference is the channel clock C
Since HCK is not input, the internal clock CK is continuously input.

The received data fetching circuit 1 does not fetch data, but the frame counter 5c for counting the continuity of frames increments by the internal clock CK. In the same manner as in the above case, the out-of-sync is detected by the operation of the multi-frame synchronization circuit 12.

In any of the cases, after the channel clock CHCK returns to the normal cycle, the pattern (frame identification number) indicating the continuity of the frames in the captured multi-frame data is the continuation of the frames of the line termination circuit. If the count value matches the count value (frame number N) of the frame counter 5c that counts the sex, the normal state is restored and the "out of sync" does not continue.

[0184]

As described in the foregoing, according to the line termination device according to the present invention takes only channel data and the frame identification number when the channel clock and the internal clock is input at the same time the received data acquisition circuit, receiving The signal data latch circuit holds the multiframe data for one multiframe and the frame identification number by the internal clock and synchronizes them.
Since the clock count is initialized when the clock is deviated, it is possible to reduce the circuit scale without the need for a special reset circuit corresponding to the case where the channel clock is cut off.

[0185] The frame counter circuit includes a circuit which Ru is counting the frame counter in the channel clock or an internal clock based on the determination circuit and the determination result the cycle of the channel clock, more preferably multi-frame synchronization circuit However, when the synchronization is lost or when a predetermined time has elapsed from the time when the synchronization is established, it is configured to determine that the synchronization is lost or the synchronization state is being established, so the cycle of the channel clock fluctuates. Also in this case, the frame counter circuit can be made to show the same count value as the frame identification number, and it is possible to eliminate the occurrence of loss of synchronism when returning to a normal cycle.

[Brief description of drawings]

FIG. 1 is a configuration example (1) of a line terminating device according to the present invention.
It is a block diagram showing.

FIG. 2 is a configuration example (2) of a line terminal device according to the present invention.
It is a block diagram showing.

FIG. 3 is a block diagram showing a configuration example of a frame counter circuit included in the line termination device according to the present invention.

FIG. 4 is a time chart diagram showing an operation embodiment (1) of the frame counter circuit in the present invention.

FIG. 5 is a time chart (2) showing an operation embodiment (2) of the frame counter circuit in the present invention.

FIG. 6 is a time chart diagram (3) showing an operation embodiment (3) of the frame counter circuit according to the present invention.

FIG. 7 is a time chart (4) showing an operation embodiment (4) of the frame counter circuit according to the present invention.

FIG. 8 is a time chart (5) showing an operation embodiment (5) of the frame counter circuit in the present invention.

FIG. 9 is a block diagram showing a connection between a general line terminator and a serial data bus.

FIG. 10 is a frame configuration diagram showing a frame on a serial data bus connected to a general line termination device and a time chart diagram showing a channel clock.

FIG. 11 is a frame configuration diagram showing a multi-frame on a serial data bus connected to a general line termination device.

FIG. 12 is a block diagram showing a configuration of a conventional frame synchronization circuit.

FIG. 13 is a time chart showing the operation of a conventional frame synchronization circuit.

FIG. 14 is a block diagram showing a configuration of a general internal clock generation circuit.

FIG. 15 is a time chart diagram showing an operation of the internal clock generation circuit.

FIG. 16 is an operation example (1) of a conventional frame counter circuit.
It is a time chart figure which shows.

FIG. 17 is an operation example (2) of the conventional frame counter circuit.
It is a time chart figure which shows.

FIG. 18 is an operation example (3) of the conventional frame counter circuit.
It is a time chart figure which shows.

FIG. 19 is an operation example (4) of the conventional frame counter circuit.
It is a time chart figure which shows.

FIG. 20 is an operation example (5) of the conventional frame counter circuit.
It is a time chart figure which shows.

[Explanation of symbols]

1 Received Data Capture Circuit 2 Received Data Latch Circuit 3 Received Data Register Circuit 4 Frame Synchronization Circuit 5 Frame Counter Circuit 5a Selection Signal Generation Circuit 5b Selection Circuit 5c Frame Counter 6 Multiframe Judgment Circuit 7 Multiframe Synchronization Detection / Sync Protection Circuit 8 Internal clock generation circuit 8a OR circuit 8b Counter 8c Decoder 9 AND circuit 10 Channel clock loss detection circuit 11 Timer / counter circuit 12 Multi-frame synchronization circuits 20-1 to 20-32 Line termination device CK Internal clock MCLK Master clock IN1, IN2 OUT, OUT1, OUT2 Serial data J Judgment result N Frame number P Increment pulse QSET selection signal R Reset signal S Synchronous state CHCK, CHCK1 to CHCK32 Channel clock SDB Serial Bus are placed in T1 selection signal generating circuit operation table T2 selection circuit operation table diagram, the same reference numerals denote the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of front page (73) Patent holder 000000295 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Takuo Gotoda 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. Fujitsu Limited (72) Inventor Kazukatsu Maruyama 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Fujitsu Digital Technology Co., Ltd. (72) Inventor Seiichi Yamano 3-19 Nishishinjuku, Shinjuku-ku, Tokyo No. 2 Nihon Telegraph and Telephone Corporation (72) Inventor Shoji Okamura 3-chome Nishishinjuku, Shinjuku-ku, Tokyo No. 19-2 Nihon Telegraph and Telephone Corporation (72) Inventor Toshiyuki Kudo Five-chome Shiba, Minato-ku, Tokyo No. 7-1 Inside NEC Corporation (72) Inventor Toshiaki Yoshino 499-1 Nobotsubo, Nakahara-ku, Kawasaki-shi, Kanagawa NEC Engineering Co., Ltd. (72) Inventor Kazutoshi Komatsu 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Akihiro Takahashi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Noburou Tajimi 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Information & Communication Division (56) Reference JP-A-4-142823 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) H04J 3/06 H04L 7/08

Claims (4)

(57) [Claims] 1. A reception data fetch circuit for fetching one frame of channel data and a frame identification number from serial data constituting a multi-frame with a channel clock, and one channel by sequentially latching the channel data and the frame identification number. A reception data latch circuit that holds multi-frame data for frames and the frame identification number, an internal clock generation circuit that generates an internal clock having the same cycle as the normal cycle of the channel clock, the channel clock or the internal clock A line counter that counts the number of frames and outputs a frame number; and a multiframe synchronization circuit that determines the synchronization state of the multiframe based on the frame identification number for one multiframe and the frame number. At the received data latch Co the road holds one said multiframe data and the frame identification number of the multi-frame in the internal clock, the multi-frame synchronization circuit initializes the frame counter circuit when the synchronization state is out
, The channel clock and the internal clock are input simultaneously
The channel data and the frame identification number only when
Circuit for capturing the signal into the received data capturing circuit
Line termination apparatus, wherein further provided with things. Wherein Oite to claim 1, the frame counter circuit, circuit for counting the frame counter in the channel clock or internal clock based on said determination circuit for determining the period of the channel clock and the determination result A line terminating device characterized by including. 3. The determination circuit according to claim 2 , wherein the determination circuit includes a table for determining that the cycle of the channel clock is a normal cycle, a short cycle, or a cycle less than twice or more than twice the normal cycle. Line terminating device characterized by. 4. Oite to claim 1, wherein the multi-frame synchronization circuit, the state of each out-of-sync or synchronization establishment during the time or the synchronization time becomes the Kihazure is established until a predetermined time has elapsed A line terminating device comprising a circuit for determining that the synchronization state is lost or is being established when it continues.