JP4441648B2 - Frame synchronization circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a frame synchronization circuit, and in particular, on the receiving side of a digital multiplex transmission apparatus or the like that is assigned a signal by multi-frame, shortens the time until frame synchronization and multi-frame synchronization are once lost and synchronization is established again. It relates to a possible frame synchronization circuit.
[0002]
[Prior art]
Conventionally, in a digital multiplexing transmission apparatus or the like, it is necessary to establish frame synchronization by detecting a frame synchronization bit of a specific pattern configuration arranged at a specific position of a frame from received input data. The synchronization protection design is made in consideration of the return characteristics of frame synchronization or the holding characteristics.
In addition, when a unique time slot is provided in a frame and data is transmitted by forming a multi-frame in this time slot, it is necessary to establish this multi-frame synchronization.
[0003]
As an example of a specific frame structure, a transmission apparatus having a transmission rate of the secondary group of 6.3 Mbit / sec will be described.
FIG. 5 is a diagram showing a configuration of a 6.3M frame. In this case, the 6.3M frame is composed of 98 time slots (TS) in which one channel (1ch = 1 time slot) is composed of 8 bits. One frame is composed of 789 bits (125 μs) of 5 bits (F) bits. Of these, 1 to 96 TS are used as information fields for mounting data, and 97 and 98 TS are used as signal fields for mounting status (ST). In addition, 97 and 98 TS are called ST frames, and these ST frames have a 64-multiframe configuration to be described later. In the figure, # 1 to # 4 indicate primary group 1.5 Mb / s logical paths for four lines multiplexed in a 6M frame.
[0004]
FIG. 6 shows a 1.5M logical path frame configuration. In this figure, one line (# 1) is extracted from four 1.5M logical path frames multiplexed on the 6.3M interface constituting the secondary group. That is, a 1.5M frame is composed of 24 channels from TS1 to TS24 consisting of 8-bit time slots and 4-bit ST bits. Here, the ST bit has a 64 multi-frame configuration, the FS bit assigned to the ST bit is a frame synchronization bit, and other control bits (abnormality detection bits and test bits) and undefined There are bits etc.
In this example, the ST bit consisting of 4 bits per frame has the FS bit inserted at every 8 frames (position of S1 # 1), and in order to construct a frame synchronization pattern consisting of 8 bits, 64 frames of 8 frames × 8 bits are required, and this is called 64 multiframes.
[0005]
FIG. 7 is a diagram illustrating a first configuration example of a conventional frame synchronization circuit.
The frame synchronization circuit shown in this figure inputs a received signal (6.3 M data) from a transmission line and extracts a clock (transmission path clock), and also converts a bipolar (bipolar) transmission line code into a unipolar (single polarity) ) Based on the clock signal from the B / U converter 1 for converting into the in-device code and the B / U converter 1, frame synchronization is established for the 6.3M input data after being converted to unipolar and the frame The 6.3M frame termination unit 2 that performs synchronization monitoring, the clock conversion unit 3 that converts the 6.3M input data from the transmission path clock to the in-device clock, and the 6.3M input data output from the clock conversion unit 3 On the other hand, it comprises 64 multiframe termination unit 4 that establishes synchronization of 64 multiframes and monitors multiframe synchronization.
[0006]
The operation of FIG. 7 will be explained. The 6.3M data input from the transmission line is converted by the B / U converter 1 into a unipolar signal, which is an in-device signal, and a pulse repetition component is extracted. To generate a clock signal. The 6.3M frame termination unit 2 establishes frame synchronization of 6.3M input data using the generated clock signal, monitors the loss of frame synchronization, and alerts an ALM I / O (alarm processing unit) (not shown). (Alarm) is output. The clock converter 3 uses the elastic store memory to write data based on the transmission path clock signal extracted from the transmission path, and to read out the data based on the in-apparatus clock signal. Convert to clock signal. At this time, fluctuations in data characteristics due to jitter, wander, etc. occurring on the transmission path are absorbed. Next, the 64 multi-frame termination unit 4 operates in accordance with the in-device clock signal, and the multi-data of 64 multi-frames provided in the time slots 97 and 98 (ST frames) constituting the frame of the 6.3M input data. While establishing frame synchronization, it monitors the loss of multi-frame synchronization and outputs an alarm to ALM I / O.
[0007]
However, in the frame synchronization circuit described above, when the clock supply function on the opposite transmission device side fails and enters a free-running state, the accuracy (stability) of the clock signal extracted from the transmission path decreases, The slip occurs in the elastic store provided in the clock conversion unit, and the frame synchronization of the 6.3M frame end unit 2 is normally established, but the 64 multi-frame end unit 4 has passed the number of forward protection steps. Loss of synchronization will be detected. At that time, the 64 multi-frame termination unit 4 again performs a synchronization pull-in operation (referred to as hunting), so that there is a problem that data corresponding to the number of front and rear synchronization protection stages is lost.
[0008]
Therefore, a configuration shown in FIG. 8 is provided as an example of a frame synchronization circuit that solves this problem.
FIG. 8 is a diagram illustrating a second configuration example of a conventional frame synchronization circuit.
The frame synchronization circuit shown in this figure is a functional block similar to that of the first embodiment described above. The B / U conversion unit 1 inputs 6.3M data and performs clock extraction, and 6.3M input data. 6.3M frame termination unit 2 for establishing frame synchronization and monitoring frame synchronization, 64 multiframe termination unit 5 for establishing synchronization of 64 multiframes and monitoring multiframe synchronization, and 6.3M input data And a clock conversion unit 3 that converts the signal to operate with the in-device clock signal. That is, the connection configuration of the 64 multiframe termination unit 5 is different from that of the first embodiment described above. Here, the 64 multiframe termination unit 5 is based on the transmission path clock signal from the B / U conversion unit 1. Thus, multi-frame synchronization is achieved with respect to the 6.3M input data before clock conversion by the clock conversion unit 3.
[0009]
Explaining the operation of FIG. 8, the B / U converter 1 converts a bipolar signal, which is 6.3M data input from the transmission path, into a unipolar signal, which is an in-device signal, and extracts a pulse repetition component. Thus, a clock signal (transmission path clock) is generated. The 6.3M frame termination unit 2 establishes frame synchronization of 6.3M input data using the generated clock signal, monitors the loss of frame synchronization, and outputs an alarm to an ALM I / O (not shown). The 64 multiframe termination unit 4 establishes synchronization of data composed of 64 multiframes provided in the time slots 97 and 98 (ST frames) constituting the 6.3M input data frame by using the generated clock signal. At the same time, a loss of multi-frame synchronization is monitored, and an alarm is output to ALM I / O.
The clock conversion unit 3 converts the clock signal to be operated into the in-device clock signal by writing data with the clock signal extracted from the transmission path using the elastic store memory and further reading out with the in-device clock signal. In addition, the elastic store memory absorbs data fluctuations caused by jitter, wander, etc. generated on the transmission path.
[0010]
As described above, in the frame synchronization circuit of FIG. 8, it is possible to avoid the influence due to the slip of the elastic store memory provided in the clock conversion unit 3.
[0011]
[Problems to be solved by the invention]
However, in the conventional frame synchronization circuit, when a 6.3M input data (received signal) is momentarily interrupted and the transmission path clock signal extracted from the transmission path is interrupted, even if the clock signal is missing one clock. However, data bit shift occurs, and both 6.3M frame synchronization and 64 multiframe synchronization are out of synchronization, and frame synchronization is established again. Also, the bit shift occurs in the same manner when the transmission data is switched and the frame phase of the input data changes, resulting in loss of synchronization. When detecting this loss of synchronization, the number of forward protection steps M required for forward protection is taken, and when the establishment of synchronization is detected, the number of backward protection steps N required for backward protection is taken, so data bit shift occurs. Then, there is a problem that time data required for the number of protection stages is lost until frame synchronization is established. This lack of data has 64 frames × (M + N) stages in 64 multi-frame synchronization, and has a great influence.
[0012]
For example, the 6.3M frame termination unit 2 counts the number of synchronization protection steps every frame in units of one frame, and the 64 multiframe termination unit 5 counts the number of synchronization protection steps every 64 frames in units of 64 frames. Assuming that the number of stages of forward protection and backward protection in the 6.3M frame termination unit 2 and the 64 multiframe termination unit 5 is three, the time until the above-described synchronization recovery is 6.3M frame termination unit. 2, 1 frame (125 μs) × (front 3 + back 3) stage takes 750 μs, and 64 multiframe termination unit 5 takes 64 frames (8 ms) × (front 3 + back 3) stage to 48 ms. It will take a long time.
[0013]
The present invention was made in order to solve the problem in the conventional frame synchronization monitoring method as described above, and even when a momentary interruption of the received signal occurs and the frame synchronization is lost, An object of the present invention is to provide a frame synchronization circuit capable of performing a recovery time until frame synchronization re-establishment in a short time.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, a frame synchronization circuit according to the present invention has the following configuration.
A frame termination unit that manages frame synchronization and protects synchronization state transitions for received signals composed of frames, and a multi-frame that consists of a plurality of predetermined frames and that controls synchronization state transitions and protects synchronization states. A frame synchronization circuit including a termination unit, wherein an input abnormality monitoring unit that monitors the received signal is provided, and when the input abnormality monitoring unit detects disconnection of the input signal, an output from the input abnormality monitoring unit The frame termination unit and the multiframe termination unit are immediately shifted to the hunting state by forcibly setting the forward protection of the frame termination unit and the multiframe termination unit to the out-of-synchronization state.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on illustrated embodiments. The description here takes the frame configuration shown in FIGS. 5 and 6 as an example.
[0016]
FIG. 1 is a block diagram showing an embodiment of a frame synchronization circuit according to the present invention. In addition, about the functional block similar to what was shown in FIG. 7 or FIG. 8, the same code | symbol is attached | subjected and the description is abbreviate | omitted.
In the figure, a clock is extracted from 6.3 Mb / s data inputted as a received signal to generate a transmission path clock, and a bipolar (bipolar) transmission path code is converted to a unipolar (unipolar) in-device code. Based on the clock signal from the / U conversion unit 6 and the B / U conversion unit 1, the frame synchronization is established and the frame synchronization is monitored for the 6.3M input data after being converted to unipolar. Based on the clock signal from the termination unit 7 and the B / U conversion unit 1, 64 multi-frame synchronization is established for the 6.3M input data after being converted to unipolar, and multi-frame synchronization monitoring is performed. A multi-frame end 8 and a clock conversion unit 3 for converting 6.3M input data from a transmission line clock to an in-device clock; The conversion unit 6, an input abnormality monitoring unit 9 for outputting a set signal indicative 6.3M input data interruption, or the effect of the detected input error of disconnection is incorporated.
[0017]
The operation of FIG. 1 will be described. The 6.3M frame termination unit 7 and the 64 multiframe termination unit 8 operate according to the transmission path clock signal extracted by the B / U conversion unit 6, and the 6.3M frame termination unit 7 establishes frame synchronization and frame synchronization. The 64 multiframe termination unit 8 establishes multiframe synchronization and monitors multiframe synchronization. Further, the input abnormality monitoring unit 9 provided in the B / U conversion unit 6 detects, for example, that the received signal has been interrupted by monitoring the phase of the transmission path clock extracted by the B / U conversion unit 6, A set signal for setting the forward protection circuit (described later with reference to FIG. 2) of the frame synchronization circuit included in the 6.3M frame termination unit 7 and the 64 multiframe termination unit 8 to the out-of-sync detection state is output.
[0018]
In other words, this frame synchronization circuit uses the set signal from the input abnormality monitoring unit 9 to forcibly shift the forward protection circuit to the out-of-synchronization detection state, and immediately shifts to the hunting state without the forward protection function. However, the recovery time is attempted to be shortened by setting the recovery time to be only the time required for backward protection related to frame synchronization.
On the other hand, when a bit error occurs in the received input data, the input abnormality detection unit 9 does not detect an input abnormality unless the transmission path clock is interrupted. Therefore, in this case, the 6.3M frame termination unit 7 and the 64 multiframe termination unit 8 are matched with the frame synchronization pattern, and a normal frame synchronization operation is performed in consideration of a predetermined number of protection stages. Become.
[0019]
Next, the schematic configuration of the 6.3M frame termination unit 7 and the 64 multiframe termination unit 8 will be described with reference to the drawings.
FIG. 2 shows an embodiment of a frame synchronization monitoring circuit provided in a frame termination unit (6.3M frame termination unit 7 and 64 multiframe termination unit 8) according to the present invention.
The figure shows a frame pattern detection circuit 10 that repeatedly compares a bit string of input data specified by a frame position pulse from a hunting circuit 11 described later with a preset frame synchronization pattern and outputs a comparison result of coincidence / mismatch. Based on the input clock signal and the comparison result from the frame pattern detection circuit 10, and based on the output from the frame pattern detection circuit 10 and the hunting circuit 11 comprising a frame counter that shift-controls the frame position pulse. A forward protection circuit 12 that counts the number of forward protection stages when shifting from the synchronization established state to the out of synchronization state, and a backward protection stage number when shifting from the out of synchronization state to the synchronization established state based on the output from the frame pattern detection circuit 10 A rear protection circuit 13 for counting Constituted by a flip-flop 14 for holding the synchronization determination result by the output from the protection circuit 12 and the backward protection circuit 13.
A set signal from the input abnormality detection unit 9 is connected to the front protection circuit 12.
[0020]
The operation of FIG. 2 will be described. Input data is input to the frame pattern detection circuit 10 and compared with a predetermined frame synchronization pattern. The frame pattern detection circuit 10 outputs a mismatch if a match with the frame synchronization pattern is not obtained, and outputs a match if a match is obtained. The hunting circuit 11 shifts the bit string of the input data of the frame pattern detection circuit 10 bit by bit by the frame position pulse when the coincidence is not obtained as a result of the comparison of the frame pattern detection circuit 10, and the frame pattern detection circuit 10 again Compare and repeat until they match. When a match is obtained in this way, the hunting circuit 11 gives the frame position pulse shifted to the next frame synchronization bit position to the frame pattern detection circuit 10, and the frame pattern detection circuit 10 compares it with the frame synchronization pattern based on this. To do. That is, the frame pattern detection circuit 10 and the hunting circuit 11 operate to capture the frame period.
[0021]
Next, the comparison result of the frame pattern detection circuit 10 is input to the front protection circuit 12 and the rear protection circuit 13 in the next stage.
Even if the frame pattern detection circuit 10 detects a mismatch when the frame protection circuit 12 is in a synchronized state, the forward protection circuit 12 does not immediately determine that the synchronization has been lost, but recognizes that the synchronization has been lost when a predetermined number of mismatches occur. Therefore, the number of mismatches is counted. Therefore, when a mismatch is detected in the frame pattern detection circuit 10, a signal is input to the count input terminal of the forward protection circuit 12 and counted up. On the other hand, when a match is detected, a signal is input to the reset terminal and the count value is calculated. Return to the initial state and repeat counting again. Then, when the forward protection circuit 12 counts the predetermined number of inconsistencies and recognizes out-of-synchronization, the recognition signal is input to the S terminal of the flip-flop 14, and the flip-flop 14 holds the out-of-synchronization signal, and then synchronizes. Moves to hunting operation for pull-in.
[0022]
The backward protection circuit 13 does not immediately determine that synchronization is established even if the frame pattern detection circuit 10 detects a match when it is out of synchronization, and recognizes that synchronization has been established when a predetermined number of matches occur. In order to do this, the number of matches is counted. Therefore, when the frame pattern detection circuit 10 detects a match, it inputs a signal to the count input terminal of the rear protection circuit 13 and counts up. On the other hand, when a mismatch is detected, it inputs a signal to the reset terminal and sets the count value. Return to the initial state and repeat counting again. Then, when the backward protection circuit 13 recognizes the establishment of synchronization by counting the predetermined number of matches, the recognition signal is input to the R terminal of the flip-flop 14, and the flip-flop 14 holds the establishment signal of synchronization.
[0023]
That is, in the configuration of the present embodiment shown in FIGS. 1 and 2, when the input abnormality monitoring unit 9 detects a disconnection of a received signal (input data) that causes a loss of synchronization (transmission path clock phase jump), an input is performed. A set signal is output from the abnormality monitoring unit 9 to the front protection circuit 12 of the frame synchronization monitoring circuit constituting the 6.3M frame termination unit 7 and the 64 multiframe termination unit 8 to forcibly set the front protection circuit 12 in a set state (predetermined In this state, the frame synchronization monitoring circuit is immediately set to the out of synchronization recognition state and the hunting operation is started.
In this way, when a momentary interruption or the like of input data occurs, the forward protection function is omitted and operation is performed so that synchronization can be established in a short time.
[0024]
FIG. 3 is a flowchart showing an operation flow of the frame synchronization circuit according to the present invention. Here, the synchronization monitoring operation by the 6.3M frame termination unit 7 and the 64 multiframe termination unit 8 will be described together. While the frame synchronization is established (step 1), the input abnormality monitoring unit monitors and determines the input (step 2). If no input abnormality is detected (No), the frame synchronization state is confirmed and determined (step 3). Is detected (Yes), it is counted how many frames the frame synchronization loss has continued to determine whether or not the predetermined number of forward protection steps has been exceeded (step 4). When the number of forward protection steps has been exceeded (Yes) Recognizes that frame synchronization has been lost (step 5).
[0025]
On the other hand, if the number of front protection steps is not exceeded in step 5 (No), the process returns to step 2. If no out-of-frame synchronization is detected in step 3 (No), the process returns to step 2.
If it is recognized that the frame synchronization has been lost, then the hunting state is entered (step 6), and the comparison of the bit string of the input data with the determined frame synchronization pattern is repeated to determine the synchronization pull-in detection (step 7). When the coincidence detection is detected as a result of the synchronous pull-in detection (Yes), it is determined whether or not the number of coincidence exceeds a predetermined number of backward protection steps (Step 8). If the number of backward protection steps is exceeded (Yes), After recognizing that the frame synchronization has been restored (step 9), the frame synchronization is now being established (step 10).
On the other hand, if the number of rear protection stages is not exceeded in step 8 (No), the process returns to step 7. On the other hand, if the result of the synchronous pull-in detection is inconsistent in step 7 (No), the process returns to step 7.
When the disconnection of the input signal is detected in Step 2 (Yes), the forward protection circuit 12 provided in the frame synchronization monitoring circuit is set to the out-of-synchronization state (Step 11), and the synchronization is lost in Step 5. Is recognized and the hunting state of step 6 is entered. Thereafter, steps up to step 10 are performed.
[0026]
Therefore, as described above, when the frame synchronization circuit according to the present invention detects an input abnormality such as a momentary interruption of input data, it always goes out of synchronization regardless of the forward protection function. Thus, the frame synchronization processing time (return time) can be shortened.
That is, for example, the 6.3M frame termination unit 7 counts the number of synchronization protection steps for each frame in units of one frame, and the 64 multiframe termination unit 8 sets the number of synchronization protection steps for every 64 frames in units of 64 frames. If the number of stages of forward protection and backward protection in the 6.3M frame termination unit 7 and the 64 multiframe termination unit 8 are both three, an input abnormality such as the instantaneous interruption of the input data described above is detected. The recovery time from the start to the synchronization recovery is 375 μs by 1 frame (125 μs) × 3 stages after the 6.3M frame termination unit 7, and 64 frames (8 ms) in the 64 multiframe termination unit 8. ) × 3 stages later, the time is 24 ms. In this case, the time can be reduced to half of the conventional time.
[0027]
Further, as another embodiment of the frame synchronization circuit according to the present invention, it may be configured as shown in FIG. That is, FIG. 4 further includes an OR gate 15 in addition to the configuration of FIG. 1, and this OR gate 15 includes a set signal from the input abnormality monitoring unit 9 and an out-of-sync pulse from the 6.3M frame termination unit 7. An output signal obtained by taking a logical sum is applied to the set input terminal of the front protection circuit 12 of the 64 multiframe termination unit 8.
As a result, when an out-of-synchronization factor other than when the input abnormality detection unit 9 detects an input abnormality occurs, for example, when a bit shift occurs because one bit of input data is lost without disconnection of the transmission path clock. Both the 6.3M frame termination unit 7 and the 64 multiframe termination unit 8 are out of synchronization after normal forward protection, but the 6.3M frame has a shorter frame synchronization processing time than the 64 multiframe termination unit 8. As soon as the termination unit 7 is out of frame synchronization, the forward protection circuit 12 of the 64 multiframe termination unit 8 is forced to be out of synchronization and is in a hunting state. Can be shortened.
[0028]
In the above example, an example of application to 64 multiframes provided in a 6.3M frame has been described. However, even if the frame configuration is other than the 6.3M frame configuration, signal allocation is configured in multiframes. Needless to say, the present invention is applicable to data transmission.
[0029]
【The invention's effect】
The frame synchronization circuit according to the present invention is configured as described above, and forcibly causes the forward protection circuit provided in the frame synchronization monitoring circuit to be out of synchronization when an out-of-synchronization factor occurs due to an instantaneous interruption of received input data. By setting, the time from loss of frame synchronization to establishment of frame synchronization is shortened. Therefore, a unique time slot is provided in the frame, and when data is transmitted by configuring a multiframe in this time slot, transmission is performed. It is possible to exert a great effect in improving the function of the apparatus.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a frame synchronization circuit according to the present invention.
FIG. 2 is a diagram illustrating a configuration example of a frame synchronization monitoring circuit used in a frame termination unit of a frame synchronization circuit according to the present invention.
FIG. 3 is a flowchart showing an example of the operation flow of the frame synchronization circuit according to the present invention.
FIG. 4 shows an embodiment of a frame synchronization circuit provided in a 64 multiframe termination unit according to the present invention.
FIG. 5 is a diagram illustrating a configuration of a 6.3M frame as a frame configuration example.
FIG. 6 is a diagram illustrating a 1.5M logical path frame configuration for explaining a multi-frame configuration.
FIG. 7 is a diagram illustrating a first configuration example of a conventional frame synchronization circuit.
FIG. 8 is a diagram illustrating a second configuration example of a conventional frame synchronization circuit.
[Explanation of symbols]
1 ... B / U converter,
2 .... 6.3M frame end,
3. Clock converter,
4 ·· 64 multiframe termination,
5 ·· 64 multiframe termination,
6. B / U converter,
7..6.3M frame end,
8 ·· 64 multiframe termination,
9. Input abnormality monitoring part,
10. Frame pattern detection circuit,
11. Hunting circuit,
12. ・ Front protection circuit,
13. Back protection circuit,
14. ・ Flip-flop 15 ・ ・ OR gate (logical OR)

Claims (1)

A frame termination unit that manages frame synchronization and protects synchronization state transitions for received signals composed of frames, and a multi-frame that consists of a plurality of predetermined frames and that controls synchronization state transitions and protects synchronization states. A frame synchronization circuit having a termination portion,
An input abnormality monitoring unit for monitoring the received signal is provided,
When the input abnormality monitoring unit detects the disconnection of the input signal,
By forcing the forward protection of the frame termination unit and the multiframe termination unit to be out of synchronization based on the output from the input abnormality monitoring unit,
A frame synchronization circuit characterized in that the frame end portion and the multiframe end portion are immediately shifted to a hunting state.

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