KR910005495B1 - Method and apparatus for deciding synchronizing/asynchronizing mode of data transmission - Google Patents

Abstract

The method is for deciding the inframe or the out-of-frame mode to operate a reframe circuit with improved synchronizing capacity. The method includes steps; (A) holding the normal synchronized state (S0) when the input (Y) is zero and transiting to the semi- alarm state (S1) when the input (Y) is "1"; (B) transiting from the first semiatarm state to the normal state when the second input is "0" and repeating the first step, and transiting to a second semi-alarm state (S2) when the second input (Y) is "1" and repeating the same process to reach the l-1 semi-alarm state; (C) transiting from a l-1 semi-alarm state (S1-1) to the normal synchronized mode when the second input (Y) is "0" and repeating the first step, and transiting to a search state (P0) of asynchronous mode when the second input is "1" and transmitting output value of "1".

Description

Synchronous / Asynchronous Mode Decision Method and Synchronous / Asynchronous Mode Decision Circuit

1 is a flow chart of a synchronous / asynchronous mode decision process.

2 is a block diagram showing an outline configuration of the present invention.

3 is a detailed configuration of the present invention using the JK flip-flop.

4 is a detailed circuit diagram of the present invention using the JK flip-flop.

5 is a detailed block diagram of the present invention using a D flip-flop.

* Explanation of symbols for main parts of the drawings

1: Asynchronous state 11-26: AND circuit

2: Synchronous state 31-38: OR circuit

3: order logic circuit 41,42: inverter

4: Combination logic circuit

The present invention relates to a method of determining a synchronous / asynchronous mode of a synchronous multiplexing device and a synchronous / asynchronous mode determining circuit. In particular, the operation in the reframe circuit is determined by different inputs in the asynchronous mode of the synchronous mode. The present invention relates to a synchronous / asynchronous mode decision method and a synchronous / asynchronous decision circuit which have significantly improved the efficiency of the circuit.

In the frame synchronization circuit of the synchronous multiplexer, the frame synchronization performance can generally be expressed by the average synchronization holding time and the average synchronization detection time in the inframe mode, and the maximum average in the out-of-frame mode. It can be expressed as a synchronous recovery time.

In other words, the average synchronous holding time is a parameter that determines whether the synchronous circuit maintains the synchronous state for as long as possible despite the extremely high line error rate. The longer the average synchronous holding time is, the better the synchronizing performance is. However, the average synchronization loss detection time is not caused by a line error or temporary interruption on the line, but when the phase shift of the sync signal actually occurs, or when the data is accidentally matched to the sync signal sequence and judged to be a sync recovery, the phase of the sync signal is incorrect. The shorter the average synchronous detection period, the better the synchronous performance.The maximum average synchronous recovery time is the new synchronous phase found by the synchronous circuit starting to find the phase of the new synchronous signal sequence in asynchronous mode. Information is reliable If it is determined that the signal has a performance, the time from the start of the phase search of the new synchronization signal sequence to the synchronization recovery is a parameter indicating the performance until the synchronization recovery is declared. The faster the maximum average startup recovery time, the better the performance of the synchronization circuit.

However, these three parameters are exclusively related to each other, so if one parameter is improved, the other performance decreases. Therefore, by combining these three measures properly, the synchronous / asynchronous mode decision method and the synchronous / asynchronous mode have the best overall synchronization performance. Decision circuit is required.

Also, in order for the performance of the synchronization circuit to be excellent, its configuration must be simple and the overall bandwidth that the interface can provide must be small.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous / asynchronous mode determining circuit in which a synchronous / asynchronous mode determining method which suitably combines the above three parameters in order to achieve excellent synchronous performance can be easily implemented by the method.

It is another object of the present invention to implement a similar method to the transmission speed and frame structure of a data link, which is a synchronous multiplexing matching device between a space split switch and a time multiplexed switch of a TDX-10 switch. Not only does it apply to interface devices, it also makes it widely available, from speeds of several Mb / s to hundreds of Mb / s.

Accordingly, the present invention is a method for achieving the above object, if the second input is '0' in the normal synchronization state of the synchronous mode, the output is maintained at '0' to maintain the normal synchronization state, and the second input is '1'. The first process of transitioning to the first quasi-alarm state to make the output '0', and if the second input is '0' in the first quasi-alarm state transitioned from the first process, the output transitions to '0' and then outputs to '0'. If the second input is '1', the second transition to the second quasi-alarm state, the output is '0' and the second process repeats the above process until the ι-1 quasi-alarm state, If the second input is '0' in the ι-1 quasi-alarm state, the output transitions to '0' and the output is '0' if the second input is '1'. If the first input is '1' in the search state transitioned from the third process to '3', the search state is maintained; if the first input is '0', the first check is performed. Transition to In state to transition output to Transition to '1' and output to '1' A fourth process, after the first confirmation state If the first input is' 1 ', the search state is maintained and the first input is' 0 ', transition to the next confirmation state, and the process of repeating the output to' 1 'to k-1 confirmation state; and 5th, if the first input is' 1' in k-1 confirmation state, transition to search state Therefore, when the output is '1' and the first input is '0', the present invention provides a synchronous / asynchronous mode determination method comprising a sixth process of transitioning to the normal synchronous state of the synchronous mode and setting the output to '0'.

In addition, in the synchronous / asynchronous mode determination method, seven confirmation states are set to seventh confirmation state, and the quasi-alarm state is one of the first confirmation states, and the allowable error value is 2, thereby improving the performance of the three parameters described above. A method of minimizing losses has been realized.

In addition, the method is that the first input is a signal that is '0' or '1' if the received data stream has a prescribed synchronization pattern in asynchronous mode, and the second input is a bit error value of the synchronization pann detected in the synchronous mode. If the allowable error value is exceeded, it is characterized by being implemented as a signal indicating '1' or '0'.

In addition, the present invention constitutes an ordered logic circuit composed of a plurality of flip-flops and a combined logic circuit composed of respective logic means as a means for achieving the above object, wherein the ordered logic circuit comprises each combinational input and each flip-flop state. Outputs a result of determining the synchronous / asynchronous mode at each state and an arbitrary time point in the synchronous / asynchronous determination process transitioning according to the first transition, and the combinational logic circuit detects whether a synchronous signal is detected in an asynchronous state. Input a second input for detecting whether the bit error of the synchronization pattern detected in the over-synchronization state exceeds the allowable error value, and combine it with the output of the sequential logic circuit and connect it to each input terminal of each flip-flop of the sequential logic circuit. It is characterized by providing the configured synchronous / asynchronous decision circuit.

In addition, the sequential logic circuit of the synchronous / asynchronous decision circuit can easily implement a circuit using four JK flip flops or four D flip flops.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a flowchart illustrating a synchronous / asynchronous determination method. In the drawing, (1) is asynchronous mode, (2) is synchronous mode, S ₀ is a normal synchronous state, S ₁ to S _1-1 is a semi-alarm state, P ₀ is a search state, and P ₁ to P _k is In each confirmation state, X is the first input which is '0' otherwise '1' when the synchronized signal is detected in the asynchronous mode, and Y is when the bit error of the synchronization pattern detected in the synchronous mode exceeds the allowable error value. '1' otherwise represents a second input that is '0'.

이 된다. 이와 같은 프레임 구조를 갖는 데이터 링크에서의 동기/비동기 결정방법을 설명하면 다음과 같다.When one frame is composed of L bits and m bits of L bits are used for synchronizing signals, and the error threshold is n in the synchronous state, the information capacity is Lm bits, and the efficiency is

Becomes A synchronization / asynchronous determination method for a data link having such a frame structure will be described below.

The state transition in the asynchronous state (1) is determined according to the state of the first input (X), and the state transition in the synchronous state (2) is determined in accordance with the state of the second input (Y). Time is a frame time.

When the synchronous circuit is in the asynchronous state (1), if there is no error in the synchronous signal string of m bits consecutively for K times, that is, if the first input (X) is '0', it is determined that the synchronous has been restored (6), and at this time, the output Set to 0 to indicate synchronous mode.

In other words, in the asynchronous state (1), the error is not allowed by a single bit in the m-bit synchronizing signal sequence, and if the correct synchronizing signal sequence is detected continuously for K frames, it is determined as the synchronizing recovery (6).

When the synchronous circuit is in the synchronous state (2), if an error is detected in the synchronous signal sequence of m bits in succession of the frame and exceeds the allowable error value n bits, i.e., the second input (Y) is continued for ι times. It is determined by the loss of synchronization (5). Therefore, the synchronous and asynchronous decision circuits determine the synchronous recovery state 6 through the K states (P ₀ to P _k-1 ) in the asynchronous state (1), and the ι states (S ₀ to) in the synchronous state (2). Since the loss of synchronization state (5) is determined through S _1-1 ), the overall state becomes ι + k states. In the asynchronous state (1), one synchronization signal sequence search state (P ₀ ) and (k-1) confirmation states are obtained. (P ₀ to P _k-1 ), and in the synchronous state 2, one normal synchronous state S ₀ and (ι-1) semi-alarm states S ₀ to S _1-1 . All of these states are asynchronous mode (1), so the output is set to '1' to indicate asynchronous mode (1).

When three parameters are obtained, the average synchronous recovery time is the average time taken from the search state (P ₀ ) to the normal synchronous state (S ₀ ), and the average synchronous detection time is the search state (P ₀ ) from the normal synchronous state (S ₀ ). ) Is the average time taken, and the average synchronization time is the average time taken from the normal synchronous state (S ₀ ) to the ι-1th quasi-alarm state.

As a specific embodiment, the synchronous / asynchronous determination method in the TDX-10 exchange data link will be described as follows.

In the TDX-10 switch, the frame repetition period is the same as 8KHZ (125μs), which is the sampling rate for PCM encoding of voice data. Since the subscriber's data consists of 8 bits, the minimum unit of one time slot is 8 bits. to be. In the TDX-10 data link, 1024 8-bit timeslots form one frame, so the data link has a transmission rate of 8 [KHz] × 8 [bit] × 1024 [piece] = 65.536 Mb / s, and 1024 8 Two timeslots of the bit timeslot use the frame synchronization signal sequence.

=0.998047=99.8[%]가 된다.Therefore, the total number of bits L constituting one frame is 8192 bits, and since the frame synchronization signal sequence m is 16 bits, the data capacity is 8176 bits and the efficiency of the data link is

= 0.998047 = 99.8 [%].

In the asynchronous state, if the correct frame synchronization signal sequence is detected eight times, the synchronous recovery (5) is judged. Since the allowable error value is two, in the synchronous state, if two or more errors are detected in the 16-bit frame synchronization signal sequence, the synchronization is lost. Judging by. Thus, the synchronous / asynchronous mode decision circuit requires at least ten states and configures the hardware for this method.

Now, the synchronous / asynchronous mode determining circuit is constructed in accordance with the method of the present invention.

The state flow diagram of FIG. 1 is shown in the state table, where Z is the output.

In the case of XY-01, this does not occur unless there is an error in the circuit. Therefore, it was classified as don't care. Adjacent states in the state table are as follows.

In order to construct a combinational logic circuit, states are applied so that states having high correlation with each other are adjacent to each other. The criteria in this process are as follows.

a) State P ₀ applies P ₁ adjacently.

b) States P ₀ and S ₀ do not have a direct correlation with each other, so they do not have to be adjacent.

c) States P ₀ and states P ₇ , P ₂ , P ₃ , P ₄ , P ₅ , P ₆ and S ₁ are correlated and placed as close as possible.

d) P ₁ -P ₂ , P ₂ -P ₃ , P ₃ -P ₄ , P ₄ -P ₅ , P ₅ -P ₆ , P ₆ -P ₇ , P ₇ -S ₀ , S ₀ -S ₁ If possible, place them as adjacent.

Considering the above criteria, the actual circuit operation is based on the state transition between states S ₀ -S ₁ , and states P ₀ -P ₁ -P ₂ -P ₃ or P ₀ -P ₁ , P ₁ -P ₂ -P ₃ , P There is a high probability of state transitions such as ₁ -P ₀ , P ₂ -P ₀ , P ₃ -P ₀ , and so on.

Therefore, in order to increase the reliability of the circuit, the states P ₀ -P ₁ , P ₁ -P ₂ , P ₂ -P ₃ , P ₂ -P ₀ , P ₃ -P ₀ , S ₀ -S ₁ , are placed adjacent to each other. It was.

This is shown in the table as follows.

In this table, the number of states is all ten, so at least four flip-flops are needed to implement these states.

When the outputs of these four flip-flops are Q ₀ , Q ₁ , Q ₂ , Q ₃ , respectively, if the search state P ₀ is applied to Q ₃ Q ₂ Q ₁ Q ₀ as 0000, the first confirmation state ( P ₁ ) may be represented as 0001, and the second confirmation state (P ₂ ) may be represented as 0010 or the like.

From the state authorization table and the state flow chart of FIG. 1, the following state transition table can be obtained.

In the state transition table, XY = 01 cannot occur, so states 9, 10, 11, 13, 14, and 15, which are money care to simplify the combinational logic and are not applied, are initial states when power is applied. Since XY = 00, the frame synchronization signal is detected once, and immediately transitions to the state P ₁ (0001). When XY = 11 or XY = 10, the state transitions to the state P ₀ (0000).

Since the state table indicates an operation state of each flip-flop, hardware implementing the state table is now as follows.

The overall configuration of hardware to be implemented first will be described with reference to the accompanying drawings. 2 is a block diagram showing the general configuration of the present invention.

In the drawing, reference numeral 3 denotes an ordered logic circuit, reference numeral 4 denotes a combinational logic circuit, X denotes a first input, Y denotes a second input, and W denotes the first and second inputs and the cyclic logic circuit 3. The outputs of the combination inputs, and Z represents the output indicating the synchronous / asynchronous mode, respectively.

The present invention consists of a sequence logic circuit (3) and a combinational logic circuit (4). The sequence logic circuit is composed of JD or D flip-flops to input a combination input (10) and a clock pulse to determine a synchronous / asynchronous mode decision process. Each state is indicated and the result is output. The combinational logic circuit 4 inputs the first input X and the second input Y to the outputs of the sequential logic circuit 3 and combines them according to the operating method of the present invention. To output to the sequential logic circuit 3, and outputs a combination of the outputs Z representing the synchronous / asynchronous mode.

As a specific embodiment, the case where the order logic circuit 3 uses the JK flip-flop will be described.

3 is a detailed block diagram of the present invention constructed using a JK flip flop. In the drawing, U ₁ , U ₂ , U ₃ , U ₀ are the first to fourth JK flip flops, and A ₀ , B ₀ , A ₁ , B ₁ , A ₂ , B ₂ , A ₃ , B ₃ are combinational logic circuits. In Fig. 4, the combined inputs input to each input terminal of the JK flip-flops U ₁ , U ₂ , U ₃ and U ₀ are shown.

The Boolean formula of each combination input that satisfies the previous state transition table is:

J terminal input of 1st JK flip-flop (U ₀ ) is A ₀ , K terminal input is B ₀ , J terminal input of 2nd JK flip-flop (U ₁ ) is A ₁ , K terminal input is B ₁ , 3JK flip-flop If the J terminal input of (U ₂ ) is A ₂ , the K terminal input is B ₂ , and the J terminal input of the fourth JK flip-flop (U ₂ ) is A ₃ and the K terminal input is A ₃ ,

를 통해 조합논리 회로(4)를 출력시킨다.Each JK flip-flop (U ₁ , U ₂ , U ₃ , U ₀ ) is synchronized with a common clock pulse, and each combination input is A ₀ , B ₀ , A ₁ , B ₁ , A ₂ , B ₂ , A ₃ , to enter the in B _3, and an operation based on the previous state transition table to output the output terminals

Through the combinational logic circuit 4 is outputted.

을 조합하여 제1JK플립플롭(U₀)의 입력단(J₀,K₀)에 연결하고, 각 AND회로(16,25)와 OR회로 (33)과 인버터(41)로 제1입력(X)과 각 JK플립플롭의 출력

을 조합하여 제2JK플립플롭(U₁)의 입력단에 연결하고, 각 AND회로(17,18,19,20)과 각 OR회로(34)(35)과 인버터(41)(42)로 제1 및 제2입력(X,Y)과 각 JK플립플롭의 출력

를 조합하여 제3JK플립플롭(U₂)의 입력단(J₂,K₂)에 연결하고, 각 AND회로(21,26)와 각 OR회로(36,37)와 인버터(41)로 제1 및 제2입력(X,Y)과 각 JK플립플롭의 출력

을 조합하여 제4JK플립플롭(U₃)의 입력단(J₃,K₃)에 연결하고 각 AND회로(22,23,24)와 각 OR회로(37,38)로 제1 및 제2입력(X,Y)과 각 JK플립플롭의 출력

을 조합하여 최종출력(Z)에 연결하여 구성하였다.In the combined logic circuit 4, the outputs of the first input (X), the second input (Y), and the sequential logic circuit (3) are combined by using an OR circuit, an inverter, and an AND circuit according to the Boolean equation. Flip-flop output

Are connected to the input terminals J ₀ , K _{0 of} the first JK flip-flop U ₀ , and the first input X is input to each of the AND circuits 16 and 25, the OR circuit 33, and the inverter 41. And output of each JK flip-flop

Is coupled to the input terminal of the second JK flip-flop (U ₁ ), and each of the AND circuit (17, 18, 19, 20), the OR circuit 34, 35 and the inverter (41) (42) And the second input (X, Y) and the output of each JK flip flop

Is connected to the input terminals J ₂ and K _{2 of} the third JK flip-flop U ₂ , and the _first and _second circuits are connected to the AND circuits 21 and 26, the OR circuits 36 and 37, and the inverter 41. Second input (X, Y) and output of each JK flip flop

Are connected to the input terminals J ₃ and K _{3 of} the fourth JK flip-flop U ₃ , and the first and second inputs are input to each of the AND circuits ₂₂ , ₂₃ and 24 and the OR circuits 37 and 38. X, Y) and output of each JK flip flop

Combination was made by connecting to the final output (Z).

5 is a detailed configuration diagram of the present invention using a D flip flop as another configuration example.

In the drawing, U ₅ , U ₆ , U ₇ , and U ₈ are combined in the first to fourth D flip-flops, and C ₀ , C ₁ , C ₂ , and C ₃ are combined in the combinational logic circuit 4 so that each input terminal of the D flip-flop ( D ₀ , D ₁ , D ₂ , and D ₃ ) indicate a combinational input respectively.

The Boolean formula of each combination input of D flip-flop that satisfies the previous state transition table is as follows.

를 통해 조합논리회로(8)로 출력시킨다.Each D flip-flop (U ₅ , U ₆ , U ₇ , U ₈ ) is synchronized with a common clock pulse, and each combination input is inputted as C ₀ , C ₁ , C ₂ , C ₃ to the previous state transition table. The output according to each output terminal

Through the combined logic circuit (8).

The combined logic circuit 8 combines the outputs of the first input (X), the second input (Y), and the sequential logic circuit (7) according to the Boolean equation, to form each D flip-flop (U ₅ , U ₆ , U). ₇ , U ₈ ) to output a combined output (Z) indicating a synchronous / asynchronous mode.

The characteristics and advantages of the synchronous / asynchronous mode determination method described above and the synchronous / asynchronous mode determination circuit implementing the method will be described by comparing three parameters.

Considering the case where the bit error rate on the line is 10 ^-3 , three parameters are calculated. This bit error rate is regarded as the worst case network condition in a general transmission line device.

First, when the maximum average synchronous recovery time is calculated, it becomes about 9,72 frame intervals, that is, 9,72 × 125 [μs] = 1.125 [ms]. Actually, until the synchronized data is obtained, the number of confirmed states is reduced to 9.72 -8 = 1.72 frame section, 1.72 x 125 [μs] = 215 [μs]. Comparing this value with the maximum average synchronous recovery time of AT &T's No. 5 Ess switch, which is widely used, the No. 5 Ess is about 5 ms when the line error rate is 10 ^-3. The time is much faster, so we can see that the performance is superior.

Second, when calculating the synchronization detection time, the synchronization signal string is 16 bits, the allowable error value is 2, and the quasi alarm state is 1, so that about 2,0063 frames, that is, 2,0063 × 125 [μs] = 250.8 [μs] Becomes

In the case of No. 5 Ess, it is about 375 μs, which indicates that the synchronization loss detection time according to the present invention is faster, and thus, it has excellent performance.

Third, the average synchronization holding time is calculated to be 3.25 × 10 ^{z 2} frames, that is, 3,25 × 10 ¹² × 125 [μs] = 12.01 [year].

In the case of No.5Ess, when the line error rate is 10 ^-3 , it is about 1.3556 years, and almost no motivation is lost due to the line error, and almost no permanent synchronization occurs when the line error rate is 10 ^-4 . .

The present invention configured and operated as described above has the following distinctive operational effects.

First, the average synchronous maintenance time is extended almost permanently at the track error rate of 10 ^-3 at the track error rate of 10 ^{-3 so} that almost no motivation is lost by the track error. Second, the maximum average recovery time is shortened from the line error rate 10 ³ to 215μs to quickly switch from asynchronous to synchronous mode.

Third, the synchronization loss detection time is shortened from the line error rate 10 ⁻³ to 250.8 μs to quickly detect the synchronization loss in the synchronization mode.

Fourth, because it is designed for the data link of TDX-10 switch which will be widely used in the future, it can be applied to the interface device similar to the data link of this TDX-10 switch, and can be widely used up to a transmission rate of several hundred Mb / s. Do.

As described above, the present invention operates in a new way, and is simpler than a conventional synchronous circuit, greatly improving the synchronous holding function, the synchronous loss detection function, and the synchronous recovery function. This can be called.

Claims (6)

If the second input (Y) is "0" in the normal synchronization state (S ₀₎ of the synchronous mode (2) maintained a normal synchronous state (Sa) and the outputs (2) to "0" and a second input (Y ) in this '1', the first semi-alert state (S ₁₎ a first process, said first process, the first semi-alert state (S ₁₎ a transition from a transition of the output (Z) to "0" in When the second input (Y) is '0', the transition to the normal synchronous state (S ₀ ) is repeated, and the first process is repeated, and the output (Z) is '0', and when the second input (Y) is '1', A second process of transitioning to the second semi-alarm state (S ₂ ) to make the output Z '0', and then repeating the same process as described above until the ι-1 semi-alarm state (S _1-1 ). If the second input (Y) is '0' in the ι-1 quasi-alarm state (S _1-1 ) of the second process, the process transitions to the normal synchronous state (S ₀ ), repeats the first process, and outputs (Z). Is '0' and if the second input (Y) is '1', the third process transitions to the search state P ₀ of the asynchronous mode (1) and the output Z is '1'. on In the transition search conditions (P ₀₎ a first input (X) is '1', the search conditions (P ₀₎ is to continue the search conditions (P ₀₎ and the output (Z) to '1', a first input (X) is first in the "0", the first check state the fourth process, the first acknowledgment state (P ₁₎ transitions from the fourth process transits to (P ₁₎ to the output (Z) to '1' If the first input X is '1', the process transitions to the search state P ₀ and repeats the fourth process, and the output is '1', and if the first input X is '0', the second confirmation state ( P ₅ ) is a fifth process of repeating the same process as the above process until the output Z is '1' and then k-1 confirmed state (P _k-1 ), k- of the fifth process 1 If the first input (X) is '1' in the confirmation state (P _k-1 ), the state transitions to the search state (P ₀ ) to make the output (Z) '1' and the first input (X) is '0'. If the brake mode (2) of the normal synchronous state (S ₀₎ to the output (Z) to a synchronous / non a sixth step of "0" to minimize the loss of data, characterized in that transitions are configured How to determine the standby mode 2. The first input (X) of claim 1, wherein the first input (X) is a signal that becomes '0' or '1' if the received data stream has a prescribed synchronization packet in the asynchronous mode (1), and the second input (Y). Is a signal indicating '1' if the bit error value of the synchronization pattern detected in the synchronization mode 2 exceeds the allowable error value, otherwise '0', and the final output Z is '0' otherwise. A method of determining a synchronous / asynchronous mode with minimal data loss, characterized in that the signal indicates '1'. According to claim 1, wherein the π-1 quasi-alarm state is to be set to 2, the allowable error value is 2, so that the quasi-alarm state has only one first quasi-alarm state, P _k-1 confirmation states are 8, the confirmation state includes first to seventh confirmation states. A sequence logic circuit (3) for inputting a clock pulse and a combined input to output a signal indicating each transition state in the synchronous / asynchronous mode determination process and a synchronous / asynchronous mode determination signal; Combination logic circuit which combines the output of the sequential logic circuit 3 with the first input X and the second input Y and inputs the sequential logic circuit 3 and outputs a signal for determining a synchronous / asynchronous state. (4), the sequential logic circuit (3) is composed of four JK flip-flops (U _0, U ₁ , U ₂ , U ₃ ) synchronized with a common clock pulse, connected to a common clear input Each combination input (A ₀ ) through each input terminal (J ₀ K ₀ , J ₁ K ₁ , J ₂ K ₂ , J ₃ K ₃ ) of the JK flip-flop (U _0, U ₁ , U ₂ , U ₃ ) _{, B 0, a | 1,} B 1, a 2, B 2, a 3, B 3) the input, the output terminals _{(Q 0 Q 0, Q 1} Q 1, Q 2 Q 2, and Q ₃ Q | ₃ ) to the combinational logic circuit 4, and the combinational logic circuit 4 is Each logic circuit combines the first input (X), the second input (Y), and the outputs of each JK flip-flop (U _0, U ₁ , U ₂ , U ₃ ) to satisfy the a-boolean equation described below. The output of each of these logic circuits is set to the input terminal (J ₀ K ₀ , J ₁ K ₁ , J ₂ K ₂ , J ₃ K ₃ ) of each JK flip-flop (U _0, U ₁ , U ₂ , U ₃ ). And a logic circuit that satisfies the b-Boolean formula described below, and connected to the final output (Z), thereby minimizing data loss.

5. The sequential logic circuit (3) according to claim 4 comprises a first JK flip-flop (U ₀ ), a second JK flip-flop (U ₁ ), a third JK flip-flop (U ₂ ), and a fourth JK flip-flop (U ₃ ). The combined logic circuit 4 is connected to the AND logic means 11, 12, 13, the OR logic means 31, and the inverter 41 by the first input X and the first to third JK flip flops U ₀ ,. Output of U ₁ , U ₂ )

Is connected to the J ₀ input terminal of the first flip-flop (U ₀ ), and the first input (X) and the second to third JK platforms are connected to the AND logic means (14, 15) and the OR logic means (32). Output of the flops U ₁ and U ₂

Negative output of the 4JK flip-flop (U ₃ )

Combination connected to the 1JK flip-K ₀ input terminal of the (U ₀₎ to the first input (X) and defines the output of the 1JK flip-flop (U _0), in an AND logic unit 25 and the inverter 41 Negative output of (Q ₀ ) and third to fourth JK flip flops (U ₂ , U ₃ )

Is connected to the J ₁ input terminal of (U ₁ ) of the second JK flip-flop, and the first input (X) and the first JK flip-flop (U ₀ ) to the AND logic means 16 and the OR logic means 33. the defined output defining the output (Q _2, Q ₃ in (Q ₀₎ and the third to 4JK flip-flop (U ₀₎ defining the output (Q ₀₎ and the third to 4JK flip-flop (U _2, U ₃₎ of the ) Is connected to the K ₁ input terminal of the second JK flip-flop (U | ₁ ), and the _first JK flip-flop is connected to each logic means (17, 18), OR logic means (34), and each inverter (41, 42). Negative output of (U ₀ )

And the outputs of the second and fourth JK flip flops (U ₁ , U ₂ )

And the first and second inputs (X, Y) are combined and connected to the J ₂ input terminals of the third JK flip-flop (U ₂ ), and the AND logic means (19, 20) and the OR logic means (35) The third JK flip-flop U ₂ by combining the first input X and the positive outputs Q ₀ , Q ₁ and Q ₃ of the first and second and fourth JK flip-flops U ₀ , U ₁ and U ₂ . of K ₂ connected to the input terminal and, aND logic unit 26 and the inverter 41 to a first input (X) and the first to 2JK negative output of the flip-flop (U _0, U ₁₎

And the 3JK flip-flop (U ₂₎ defining an output (Q ₂₎ by combining the 4JK flip-flop (U ₃₎ of the J ₃ input connected to the terminal and, AND logic unit 21 and each of the OR logic means (36, 37) negative outputs of the _first , second and fourth JK flip-flops U ₀ , U ₁ , U ₃ and the third JK flip-flops U | ₂ .

And the second input (Y) are combined and connected to the K ₃ input terminals of the fourth JK flip-flop (U ₃ ), and each AND logic means (21, 22, 23, 24) and each OR logic means (37, 38) a first input (X) and a second input (Y) and the first to the 2JK flip-flop (U _0, U ₁₎ defining an output (Q _0, Q ₁₎ and the third to 4JK flip-flop (U ₂ of , U ₃ ) negative output

And synchronous / asynchronous mode determining circuits with minimal loss data. A sequential logic circuit (7) and a sequential logic circuit (7) for inputting a clock pulse and a combined input to output a signal indicating each transition state in the synchronous / asynchronous mode determination process and a synchronous / asynchronous mode determination signal; Combination logic for inputting the output of the sequential logic circuit 7, the first input (X) and the second input (Y) to the sequential logic circuit (7) and outputting a signal for determining a synchronous / asynchronous state. four D flip-flop configuration is, the sequential logic circuit is synchronized by a common clock pulse is connected to the clear input of the common _{(U 5, U 6, U} 7, U 8) the D flip-flop (U ₅ and composed, Input each combination input (C ₀ , C ₁ , C ₂ , C ₃ ) through each input terminal (D | ₀ , D ₁ , D ₂ , D ₃ ) of U ₆ , U ₇ , U ₈ , Output terminal

The combinational logic circuit 8 is connected to the combinational logic circuit 8 through the first input X and the second input Y and the respective D flip-flops U ₅ , U ₆ , U ₇ , and U ₈ . Combining the outputs of the logic circuits to satisfy the a-boolean formula described below, and outputs the outputs of these logic circuits to the input stages of each D flip-flop (U ₅ , U ₆ , U ₇ , U ₈ ) D ₀ , D ₁ , D ₂ , and D ₃ ), and a logic circuit that satisfies the b Boolean formula described below is configured to connect to the final output (Z) to minimize data loss. Synchronous / Asynchronous Mode Decision Circuit.

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