JPS6257329A - Frame synchronizing pattern detection circuit - Google Patents

Abstract

PURPOSE:To attain restoration to synchronization in a very short time by detecting it when each synchronizing bit is inputted to a frame synchronizing pattern detection section and outputting a in-frame phase signal in response to the order of the synchronizing bit. CONSTITUTION:Shift register function sections 1-l-1-n shift sequentially the input data and act like a shift register. In constituting a frame synchronizing pattern detection section 2 by a ROM, the ROM outputs a synchronizing pattern signal when an address with synchronizing bits S1-S11 is inputted and outputs the in-frame signal in response to the address. Thus, the synchronization is restored and also the location of each frame is recognizd as the 1st frame F1, the 2nd frame F2..., then the synchronization restoration is applied complete ly.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields (Figure 1 (a)) Prior Art (Figure 8) Problems to be Solved by the Invention Implementation of Means and Actions to Solve the Problems Example (11) First embodiment of the present invention (Figures 2 and 3) (2) Second embodiment of the present invention (Figures 4 to 7) Effects of the invention [Summary] Frame synchronization of PCM communication device In order to detect this by performing multi-point monitoring of the input PCM signal, inputting the output of the shift register means to a frame synchronization pattern identification means;
It detects a frame synchronization pattern and obtains the intra-frame phase at that time.

[Industrial application field]

The present invention relates to a frame synchronization circuit for a PCM communication device, and in particular, in order to shorten the recovery time when synchronization is lost, a shift register means is used to monitor input PCM signals at multiple points, and a frame synchronization pattern is detected and identified. It relates to something that can be done without being limited to the phase.

In a PCM communication device, for example, as shown in FIG. 1(a),
One multiframe is composed of frames F1 to F12 (Fl' to F12') to form a PCM signal. At the beginning of each frame is a 1-bit synchronization bit Si (i
=1 to 11), but when one multiframe is composed of 12 frames, an alarm bit X is provided at the beginning of the 12 frames F12. The synchronization pitches) S+ and S2-'s + + form one specific pattern.

Further, in the sixth frame F6 and the twelfth frame F12, when transmitting an audio signal, a signaling bit normally exists.

[Conventional technology]

In PCM communication, in order to receive each frame correctly, it is necessary to establish synchronization, and this synchronization is performed by accurately detecting the pattern of the synchronization bits 81 to S1+.

For example, in FIG. 1(a), a hunting state occurs at the timing following the synchronization bit S1 of the first frame F1,
When out of synchronization occurs, these synchronization bits 81 to S1
It is necessary to confirm the positions of the synchronization bits 81 to S11 by detecting the pattern formed by the synchronization bits 81 to S11, and to restore synchronization.

For this synchronization recovery process, conventionally, as shown in FIG. 8, an inverter IN (in the example where S2 is "0" in the figure) is connected according to the state of the synchronization bit St (t=1.2-.11). An input NAND circuit was used to detect the synchronization pattern.

[Problem that the invention seeks to solve]

By the way, as mentioned above, when an out-of-synchronization occurs at the timing following the synchronization bit S1 of the first frame F1 in FIG. 1(a), the conventional synchronization pattern detection circuit as shown in FIG. The synchronization pattern could not be detected until the synchronization bits 81 to S11 of the first frames F1' to F11' were input to the NAND circuit NAND in FIG.

Therefore, in the above case, the first frame F1 to the eleventh frame
Synchronization cannot be restored until after the time of frame F11',
There was a problem in that it took a long time to recover from synchronization.

As described above, an object of the present invention is to enable the multi-contact monitoring type frame synchronization detection circuit to detect synchronization bit 8 when in the hunting state.
Detecting only a certain phase of the frame synchronization pattern formed by 1 to Sit, that is, only when 31 to St+ are input in this order to the NAND circuit in FIG.
To provide a frame synchronization pattern detection circuit which improves the problem that synchronization cannot be restored until the specific phase of the frame synchronization pattern is inputted because it is in a backward protection state or a synchronization establishment state, and therefore it takes a long time to restore synchronization. That's true.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention has the following features, for example, as shown in FIG.
As shown in bl, shift register function units 1-1 to 1-n
and a frame synchronization pattern detection unit 2, each frame F
The first synchronization bit S in the shift register function section 1
-1 to 1-n, and when these synchronization bits are simultaneously input to the frame synchronization pattern detection section 2,
The synchronization pattern detection circuit 2 outputs a synchronization pattern detection signal and its intra-frame phase signal.

[Effect]

In the present invention, each synchronization bit is detected in any order when it is input to the frame synchronization pattern detection section, and is detected according to the order of the synchronization bits (S+, 3
2-・511), (Sz, Sz --'S i 1,
Since it outputs an intra-frame phase signal indicating which pattern it is, S+), (S3-.Sl, S2)-., synchronization can be restored in a very short time.

〔Example〕

(1) First embodiment of the present invention The first embodiment of the present invention is described in the first embodiment based on FIGS. 2 and 3.
This will be explained with reference to the figures.

FIG. 2 shows the configuration of an embodiment of the present invention, in which 1 is a shift register section, which is composed of shift register function sections l-1 to 1-n, and 2 is a frame synchronization pattern detection section, which is a ROM. (Read Only Memory)
Figure 3 shows a PC using the present invention.
This is an example of an M communication device.

In FIG. 3, 10 is a synchronization pattern detector,
Frame synchronization pattern detection unit 2 constituted by shift register function units 1-1 to l-n (Fig. 1) and ROM
11 is a channel unit which outputs a digital signal or an audio signal, 12 is a timing pulse generator, and 13 is a synchronization protection circuit.

The shift register function units 1-1 to 1-n sequentially shift input data and perform the same operation as a shift register, and can of course be configured by a shift register. However, one frame is 8 bits x 24
Since it is composed of CH and 1 synchronization bit S (1 bit) and has a length of 193 bits, it would be expensive to configure it with a shift register, so by converting the address of the memory, this shift register function section 1-1 ~ln can be constructed.

When the frame synchronization pattern detection unit 2 is configured with a ROM, this ROM has the order of synchronization bits S1, Sz, Sz-. (this is taken as the first intra-frame phase) as shown by ■ in FIG. When the address is entered in , ■ in Figure 2
As shown, the order of synchronization bits X, S1, Sz・- (X is the alarm bit) (this is the second intra-frame phase)
When the address is entered in , as shown by ■ in Figure 2,
The order of synchronization bits S11,
When an address is input at the in-frame phase), when an address is input at the synchronization bits 81 to S11, a synchronization pattern detection signal is output,
In accordance with the address at that time, an intra-frame phase signal (1 in the case of (1) and 2.- in the case of (2)) is output. As a result, not only synchronization is restored, but also the first frame F1,
Since the position of each frame, such as the second frame F2, etc., is also known, complete synchronization recovery can be performed.

In the above example, a case has been described in which the frame synchronization pattern detection section 2 is configured with a ROM, but of course, not only a ROM but also an inverter and a NAND circuit (AND circuit) may be used. In this case, the inverter and NAND circuit are
It is necessary to prepare the same number of frame synchronization patterns (12 in this example), and the intra-frame phase can be determined by identifying from which NAND circuit the synchronization pattern detection signal is output.

A PCM communication device using the present invention will be briefly explained with reference to FIG.

When a hunting state occurs and synchronization is lost, the shift register function units 1-1 to 1 of the synchronization pattern detector 10
-n and frame synchronization pattern detection section 2 immediately outputs a synchronization pattern detection signal and an intraframe phase signal, and synchronization recovery is performed.

That is, this synchronization pattern detection signal is transmitted to the synchronization protection circuit 2.
Based on this, the synchronization protection circuit 13 sends a timing signal to the timing pulse generation section 12.

By the way, since an intra-frame phase signal is output to this timing pulse generating section 12, this causes the channel section 1 to
It is possible to determine which frame the signal transmitted in the first frame is. A digital signal from a data terminal or the like is output as a digital signal, and an audio signal is output as an audio signal after D/A conversion in the channel unit 11. In this case, since signaling exists in the sixth frame F6, the twelfth frame F12, etc., it is also possible to read this.

(2) Second embodiment of the present invention A second embodiment of the present invention will be described with reference to FIGS. 4 to 7.

FIG. 4 shows a second embodiment of the present invention, FIG. 5 shows a PN (pseudorandom) pattern generation circuit, FIG. 6 shows a PN pattern detection circuit, and FIG. 7 shows a PN pattern detection logic diagram.

In the second embodiment, synchronization pattern detection and intraframe phase detection are performed by monitoring only part of the synchronization bits.

A case where a PN pattern is used as a synchronization pattern will be explained.

The PN pattern is as shown in FIG.
This can be obtained by calculating it by a circuit and using it as the input (number) of the shift register.If the number of stages of the shift register is N, the pattern in the shift register is 2.
There are N-1 (excluding all "0") ways. The output signal of the 808 circuit at this time also repeats in a 2N-1 bit length pattern (PN pattern).

Regarding the characteristics of the PN pattern, an example using, for example, a three-stage shift register will be briefly explained with reference to the seventh drawing.

When rl 01J is set in the shift register, the EOR output of the center stage and output stage becomes "1", and when the data is sequentially shifted one bit at a time, 7 bits as shown in Fig. 7(a) are generated. A PN pattern of 1 is obtained.

In this case, the number of stages N of the shift register is 3.808. Since the output stage M to the circuit is in the center, it is the second stage. At this time, the output of the first state Ro is "1", and the output of the next state R1 is "1".
", the output of the third state R2 becomes "0".-. At this time, as shown in FIG. 7(b), the exclusive OR of state Ro, R1, and R3 is "0", the exclusive OR of R1, R2, and R4 is r OJ, and the exclusive OR of -Rs, Ro, and R2 is "0". The logical sum is “0”
”. In other words, when the outputs of the 808 circuits in each state are sequentially set in the shift register R shown by the dotted line in FIG. The exclusive OR of the outputs of the 2nd and 3rd stages is always “0” if this data is a PN pattern.
”.

In general, in a PN pattern obtained by taking the EOR of the first bit of the Mth bit in an N-stage shift register, in the shift register R, the first bit and the N
The exclusive OR of the −M19th bit and the Nth bit becomes 0. Therefore, in the case of FIG. 7(a),
The exclusive OR of the first four sets is obtained using RO to R6 in FIG. 2(b), and if the OR output is "0", it is understood that the pattern is a PN pattern.

Furthermore, in the PN pattern in FIG. 7(a), all three consecutive bits show different patterns, so for example, the three bits in the state Ro-R2, that is, the O
By monitoring the 3 bits from stage B1 to stage B2, the intra-frame phase can be determined. Note that this applies not only to continuous bits but also to monitoring of three specific bits.

Generally, in a PN pattern obtained by an N-stage shift register, the intra-frame phase can be determined by monitoring N consecutive bits.

That is, as shown in FIG. 6, the input PCM signal is input to the shift register function units 22-1 to 22-n, and the leading bits are transferred to the register stages Ro, R(NM), and RN as described above. When monitored by the EOR circuit, these first bits are the PN obtained from the generation circuit as shown in Figure 5.
If a pattern is formed, the monitoring signal from this EOR circuit becomes O.

Therefore, shift register function units 22-1 to 22-n
When calculating the exclusive OR of the outputs of each of the combinations as explained in FIG. 7 (b3) and calculating their OR, if this OR output is "0", it means that a PN pattern has been detected.

And synchronization bits 81 to S1 of each frame F1 to F12
For example, if the pattern formed by 1 is a PN pattern obtained using a 4-bit shift register, the intra-frame phase can be detected by monitoring the specific 4 bits (for example, 4 consecutive bits).

Therefore, as shown in FIG. 4, a phase detector 20 for detecting an intra-frame phase signal, a frame synchronization pattern detector 21 for detecting a <PN pattern as described above, and a shift register section 22 are used to detect a frame synchronization pattern and a frame. Internal phase can be detected.

Here, the phase detector 2o is composed of a ROM, and the frame synchronization pattern detector 21 calculates the EOR of the signal transmitted from the shift register section 22 as described above, detects that all of these become rOJ, and synchronizes. It outputs a pattern detection signal. The shift register section 22 includes shift register function sections 22-1 to 22-n, and has an input P.
CM signals are transmitted sequentially. Each shift register function section 2
2-1 to 22-n are bit lengths constituting one frame.

In the above description, an example in which the frame synchronization pattern is a PN pattern has been described, but the present invention is of course not limited to this, and any pattern having the properties described above may be used.

〔Effect of the invention〕

According to the present invention, the output of the shift register function for performing multi-point monitoring of the input PCM signal is used as input to determine whether or not the frame synchronization pattern is longer than a predetermined length without limiting it to a specific phase. Since it can be detected together with the intra-frame phase, the recovery time when synchronization is lost can be greatly shortened.

Further, according to the second embodiment, it is possible to detect the intra-frame phase by simply monitoring a plurality of specific bits.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is an embodiment of the invention, Fig. 3 is a PCM communication device to which the invention is applied, Fig. 4 is a second embodiment of the invention, Fig. 5 6 is a PN pattern generating circuit, FIG. 6 is a PN pattern detecting circuit, FIG. 7 is a diagram explaining the principle of PN pattern detection, and FIG. 8 is a conventional synchronization pattern detecting circuit. 1 - Shift register section 2 - Frame synchronization pattern detection section 10 - Synchronization pattern detector 11 - Channel section 12 - Timing pulse generation section 13 - Synchronization protection circuit 20 - Phase detector 21 - Frame synchronization pattern Detector 22 - Shift Register Section Patent Applicant: Fujitsu Limited (1 other person) Agent: Akira Yamatani, Sakae Figure PN pattern hand*field circuit Figure 6 Figure 8

Claims (4)

[Claims] (1) A frame synchronization pattern detection circuit that monitors input PCM signals at multiple points and detects frame synchronization, which includes a shift register function section into which input PCM signals are sequentially input, and a predetermined input signal from the shift register function section. A synchronization pattern detection unit is provided that identifies a frame synchronization pattern with a length greater than or equal to 1. A frame synchronization pattern detection circuit characterized in that the frame synchronization detection circuit performs frame synchronization detection for a frame synchronization pattern and identifies the intra-frame phase of the frame synchronization pattern. (2) Claim (1) characterized in that the synchronization pattern detection unit is capable of outputting an intra-frame phase signal.
) The frame synchronization pattern detection circuit described in section 2. (3) A pseudo-random signal is used as the frame synchronization pattern, and the frame synchronization pattern detector is configured to monitor an exclusive OR of specific bits. frame synchronization pattern detection circuit. (4) The intra-frame phase detection means monitors a specific bit of a frame synchronization pattern and detects the intra-frame phase according to the pattern. The frame synchronization pattern detection circuit described in (3).