JPS6223231A - Parity counter circuit - Google Patents

Abstract

PURPOSE:To attain high speed processing by providing plural counters so as to eliminate the need for the count of data number in consecutive frames by one counter and the complicated operation at a sectioning point at each frame. CONSTITUTION:A changeover circuit 101 outputting a switching signal at the head of each frame depending of position information of a reception data and plural counters 102, 103 counting the data number in a frame are provided, the switching signal operates sequentially plural counters to count the data number over all bits in the frame. Thus, complicated control is not required at sections of frames and the data number is counted over all bits in the frame without the provision of a space in the frame.

Description

[Detailed Description of the Invention] [Summary] In a system that monitors a digital transmission path using parity check, a plurality of counters are provided to increase the operating margin of the circuit, and each counter is sequentially operated for each frame. It is something that makes it work.

[Industrial application field]

The present invention relates to a parity counting circuit for parity checking which is used as a monitoring system for digital transmission paths, and in particular counts all bits in a frame in order to increase the reliability of transmission path monitoring even in high-speed digital transmission paths. The present invention relates to a parity counting circuit that enables

As a digital transmission system, optical communication methods are being adopted, and technology development to make them ultra-high-speed is active, and there are already 4
Optical communication systems with a bit rate of 00 Mbps have been put into practical use.

Figure 2 shows an example of such an optical communication system configuration;
The figure shows an example of a frame structure. One frame consists of, for example, eight subframes, and a frame synchronization pulse F is placed at the beginning of each subframe.

A supervisory control signal SC, a parity check bit P, an auxiliary data signal AUX, etc. are inserted.

These signals are inserted by the pulse insertion section of the terminal relay device 1.4 to form a frame. That is, the speed converter 11
．． 22, converting the input data signal to an appropriate speed,
A pulse inserter 12.21 inserts the various signals described above, which are converted into optical signals by an optical transmitter 13.20 and input into an optical fiber. The intermediate repeater 2.3 amplifies the signal transmitted within the optical fiber and relays it to the terminal repeater. The optical signal received by the optical receiver 17.16 of the terminal repeater 1.4 is converted into an electrical signal and sent to the pulse separator 2.
At step 1.15, the various signals inserted by the pulse insertion section 12.21 are extracted and sent to the monitoring device 5.9, and the input data signal input to the speed conversion section 11.22 is sent to the speed conversion section 19. For example, if .14 is reached, it is transmitted to a switching center, etc.

In the above system, the pulse separator 15 generates a frame synchronization pulse F l + F l* F
Frame synchronization is achieved using l*F2, and parity bit P is extracted. Further, the number of data in the frame is counted by a parity counting circuit, and the counting result is compared with the contents of the parity bit P to perform a parity check. If the error rate of the transmission path is sufficiently low, if the content comparison results in an error, it can be estimated that one code error has occurred within the frame. Therefore, by monitoring the parity check results, it is possible to know the bit error rate of the transmission path. This parity check result is sent to the monitoring devices 5 and 9.

If the code error rate becomes worse than a predetermined value, the monitoring device 5.9 determines that the quality of the transmission path has deteriorated, generates an alarm, and takes measures such as switching to a backup system. . This kind of parity check is usually performed at the end station relay equipment 1.4, but the intermediate repeaters 2 and 3 also have a similar parity check function in order to quickly detect the state of the transmission path and deal with failures. Since a parity error may be detected by the monitoring device 7.8, it is desirable to simplify the control.

Furthermore, as mentioned above, there is a need for a parity counting circuit suitable for possible ultra-high-speed digital transmission.

[Conventional technology]

FIG. 4 shows a configuration example of an intermediate repeater having a parity check function. The optical signal received by the optical receiver 23 is converted into an electrical signal, and the equalization amplifier 24 shapes the waveform and amplifies it to a constant level.The output signal of the zero equalization amplifier 24 is sent to the identification circuit 25 and the timing extraction circuit 27. is input. The timing extraction circuit 27 extracts a clock component, and the identification circuit 25 uses this clock signal to identify the digital data signal transmitted from the terminal relay device. The identified digital data signal is again converted into an optical signal by the optical transmitter 26 and input into the optical fiber. The data signal identified by the identification circuit 25 and the clock signal extracted by the timing extraction circuit 27 are input to a frame pattern detection circuit 28. Further, the clock signal is input to a frame counter 32 via a gate circuit 31. The frame counter 32 has a frequency division function and outputs a frame synchronization pattern from the input clock signal at the insertion positions of frame synchronization pulses Ft, FL, Ft, Fz shown in FIG. The frame is inserted. The frame synchronization pattern output by the frame counter 32 and the frame synchronization pattern detected by the frame pattern detection circuit 28 are compared in the comparator circuit 2. If the comparison results match, it means that frame synchronization is achieved. If the comparison results do not match, a signal indicating a mismatch is sent to the synchronization protection circuit 30, and the synchronization protection circuit 30 closes the gate circuit 31, thereby skipping one bit of the clock signal input to the frame counter 32 and converting it into a frame counter. 32 outputs a frame synchronization pattern by one clock.

By repeating the above operations, frame synchronization of the received data signals is established.

When frame synchronization is established, the frame counter 32
outputs various control signals, ie, signals indicating the bit position of the data signal. In the following description, it is assumed that the frame counter outputs a signal indicating the bit position of the data signal.

Although FIG. 4 only shows the configuration of the intermediate repeater, by connecting the output of the identification circuit 25 to the pulse separation section shown in FIG. 2, the configuration is similar to that of the terminal repeater.

Next, regarding the parity counting circuit shown in FIG. 4, the configuration of the conventional parity counting circuit is shown in FIG. 7, and its operation will be explained using the time chart of FIG. 8.

The RZ waveform received data (a) is passed through an inverter,
It is input to the N'OR circuit 37 together with the inhibit pulse ('b) output from the frame counter, and the various control signals inserted by the pulse insertion section of the terminal relay device are removed to generate the N0R37 output (c). do. this is,
Only the data signal is extracted. N0R37 output (C1 is input to the binary counter 35 constituted by a D-type flip-flop, and “1” of the N0R37 output
”. Therefore, the binary counter output (e) is
When the initial state is "0", when the number of "1"s is even, it is "0", and when it is odd, it is "1", which corresponds to even parity, and conversely, when the initial state is "1" , when the number of "1"s is even, it is "1", and when it is odd, it is "0", corresponding to odd parity. In this way, after counting up to just before the AUX bit of the nth frame, the frame counter inputs the read pulse (f) to the C terminal of the D-type flip-flop 36, and changes the output state of the binary counter 35 just before the AUX bit to D.
It is held by a shaped flip-flop 36. That is, the D-type flip-flop serves as a memory. 2 to memory 36
When the count result of the decimal counter 35 is held ((in Fig. 7)
The frame counter outputs a reset pulse (d) to the binary counter 35 at the position of the F bit in the received data (a), and sets the output state of the binary counter 35 to the initial state. Reset to . From then on, the same operation is repeated and the data signals in each frame are
Count the number of 1”.

The counting result held in the memory 36 is extracted by the parity bit extraction circuit 33 at the Pn bit position by the parity bit extraction pulse (h) output from the frame counter, and its output (1) ( The content of the parity bit (Pn) is compared with the EOR 38 to perform a parity check.

[Problem that the invention seeks to solve]

In the above description, the counter 35 cannot be operated unless there is an interval of several bits or more between the shaded portion in the figure, that is, the AUX bit and the Fl bit in the received data fal. This is between the AUX bit and the FI bit, the read pulse (fl) and the reset pulse (
This is because, after successively generating dl and holding the counting result, it is necessary to return the binary counter to its initial state in order to count the number of data in consecutive subsequent frames. In particular, the read pulse (f) ensures that the binary counter 35
It needs to be done just before the bit.

Therefore, conventionally, between the AUX bit and the F bit,
The problem was dealt with by devising the frame structure, such as by leaving several blank bits. In other words, if the operating speed of the circuit elements is ultra-high-speed, only two bits, the AUX bit and the F/ bit, can be used.
Although it is possible to read the counting results and reset the binary counter 35, as mentioned above, when the bit rate exceeds 400 Mbps, it is difficult and extremely expensive to manufacture circuit elements that operate at higher speeds. Become.

An object of the present invention is to eliminate the need for manipulating the frame structure to provide blank spaces between counting intervals as in the past, and to enable data counting without using expensive high-speed circuit elements. It is in.

[Means for solving problems]

As shown in the principle block diagram of the present invention shown in FIG. 1, the above problem is solved by a switching circuit (101) that outputs a switching signal at the beginning position of each frame based on position information of received data, and a switching circuit (101) that counts the number of data in a frame. This problem is solved by sequentially operating the plurality of counters (102 and 103) according to the switching signal and counting the number of data over all bits in the frame.

[Effect]

By providing a plurality of counters, the number of data in consecutive frames is counted by the same counter [Example] Hereinafter, an example of the present invention will be explained in detail with reference to FIGS. 5 and 6. .

FIG. 5 is a parity counting circuit diagram of an embodiment of the present invention, and FIG. 6 is an operation time chart of each part of the parity counting circuit of FIG. Note that the circuit diagram in Figure 5 is based on the circuit diagram in Figure 7.
This figure shows the parity counting circuit in FIG. 4 similarly to the figure, and the same parts as in FIG. 1 are given the same reference numerals.

Receive data and inhibit pulse are each N0R40
The various control signals inputted to the terminal relay device and inserted by the pulse insertion section of the terminal relay device are removed.

The switching pulse is a signal output from the frame counter, and is output at the F bit position at the beginning of the frame.

This switching pulse is input to the frequency divider 41, and the frequency divider 41Q output and the frequency divider 41Q output shown in FIG. 6 are generated.

The output of the frequency divider 41Q becomes "LOW" level in the n-th frame, the n+2-th frame - m--, and opens the N0Rs 42 and 45. becomes “LOW” level in the odd-numbered frame, and N0R43
Open ゜44.

Therefore, even frame data is passed through N0R42 to 2
The number of data “1” is inputted to the decimal counter 46 and counted, and the odd frame data is inputted to the N0R44 (N0R44).
output of OR40) is input to the binary counter 47 and the data "
1'' is counted. That is, the data within each frame is alternately input to the binary counters 46, 47.

During the odd frame period, the Q output of the frequency divider 41
Since 0R42 is closed, the binary counter 46 is
The counting results for even frames are held during the odd frame period. Similarly, the binary counter 47 holds the count results for odd frames during even frame periods.

Here, the reset pulses of the binary counters 46 and 47 outputted from the frame counter are input to N0R43 and 45, so the output signal of N0R43 is used to count the even frames in the binary counter 46 at the next odd frame. Similarly, the output signal of the NOR 45 becomes a reset pulse that resets the binary counter 47 for counting odd frames at the next even frame.

Furthermore, the output of the frequency divider 41Q is input to N0R48, which is closed during even frame periods. Therefore, the counting result of the binary counter 46 for even frame counting is output to the EOR 51 via N0R50 only during the next odd frame period.Similarly, the output of the frequency divider 41Q is input to N0R49, NOR49 will be closed during this period. Therefore, the counting result of the binary counter 47 for odd frame counting is output to EOR,51 via N0R50 only during the next even frame period.

In other words, the switching circuit 101 allows each binary counter to satisfy the function of counting the number of data in a frame and the memory function of continuing to hold the counting result in the next frame period.

Binary power ≠ → Ta 46.47 due to runs N0R48 and N0R49
The counting result is inverted, but since it is inverted again by NOR, 50, the signal input to EOR 51 is the same as the output of binary counters 46, 47.

Parity bits P n , Pz++ in received data
As explained in time chart 1- of FIG. 8, the parity bit extraction pulse from the frame counter
The parity bit extraction circuit 33 extracts the count results of the binary counters 46 and 47 and the parity.

Parity Pn, P, y outputted from the bit extraction circuit 33.

are compared in EOR 51 and a parity check is performed.

The reset and 7 pulses output by the frame counter may be output between the positions of Pn and PH+t and the position of the next frame pulse F1 to reset the binary counters 46 and 47.

In addition, in the above explanation, Fl, 5C2F2. Pn, F,
, SC, AUX, etc. are inserted into the data signal and transmitted, so we have explained that these are removed by the inhibit pulse and only the data signal is output to the counter. However, the inhibit pulse It is also possible to count all bits including control signals without using . In addition, when transmitting control signals separately,
There is no need to use inhibitor pulses.

〔Effect of the invention〕

As described in detail above, in the present invention, a plurality of parity counting circuits are provided, and the number of data in consecutive frames is sequentially counted, and a switching circuit is used to control the number of data to be held as is. Therefore, there is no need to perform complicated control at frame divisions, and the number of data can be counted across all bits in a frame without providing a blank space in the frame.

Furthermore, with the configuration described above, the number of data can be counted across all bits in a frame even in ultra-high-speed digital transmission, so the number of data can be counted without converting to low-speed data by speed conversion of the data signal. It becomes possible,
Since the configuration is simplified, intermediate repeaters etc. can also be actively provided with a parity check function.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is an example of a digital transmission system configuration, Figure 3 is an example of a frame configuration, Figure 4 is an example of a block configuration of an intermediate repeater with a parity check function, and Figure 5 is an example of a block configuration of an intermediate repeater with a parity check function. A parity counting circuit showing an embodiment of the present invention, FIG. 6 is a time chart of various parts of the circuit shown in FIG. 5, FIG. 7 is a conventional parity counting circuit, and FIG. 8 is a time chart of various parts of the circuit shown in FIG.

Claims (1)

[Scope of Claims] A switching circuit that outputs a switching signal at the beginning position of each frame based on position information of received data, and a plurality of counters that count the number of data in a frame, and the number of counters is counted based on the switching signal. A parity counting circuit is characterized in that it sequentially operates devices and counts the number of data.