JP2693831B2 - Auxiliary signal transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention is an auxiliary signal for transmitting a line switching control signal, a supervisory signal, or a meeting signal superimposed on a main signal when a CMI code is used as a transmission path code. The present invention relates to a transmission method, and particularly to a method for superimposing a plurality of auxiliary signals.

[Conventional technology]

The CMI code used as the transmission code will be generally described with reference to FIG.

Normally, binary code is converted into CMI code according to the following rules. That is, when the normal binary code (FIG. 3) is “0”, the CMI code (FIG. 3) is “01”, and the normal binary code (3rd).
22) is “1”, the CMI code (FIG. 23 in FIG. 3) is converted into the alternating code of “00” and “11”. FIG. 3 is a clock pulse of a normal binary code 22 in FIG. In the CMI code 23, the method of causing violation (CMI code rule violation) is performed according to the following rules. That is, when the normal binary code 22 of the time slot for performing the violation is "0", the "01" of the CMI code 23 is set to "10", and when the normal binary code 22 is "1", the time is set to "1". Alternating 00 "and" 11 "is prohibited, and the CMI code with violation (Fig. 3 24) is used. In FIG. 3, * indicates the position of violation.

Conventionally, when superimposing and transmitting a plurality of auxiliary signals using violation, a frame for violation is used to use a specific time slot for superimposing an auxiliary signal, and an auxiliary signal for superimposing a specific time slot. Or prepare auxiliary signals alternately on a frame-by-frame basis,
A general method is to synchronize the frame on the receiving side and separate the auxiliary signal.

FIG. 4 shows the case where the number of auxiliary signals in the method of preparing the number of auxiliary signals for superimposing the time slots is shown, and its operation will be outlined. The main signal 1 input to the transmitter 25 is converted into a CMI code string by the CMI conversion circuit 27. On the other hand, the auxiliary signal 2 and the auxiliary signal 2'input to the transmitter 25, and the frame pattern signal 3 generated by the frame pattern generation circuit 29
Are alternately sampled by the sampling circuit 28 to obtain the violation designation pulse 4. The violation designation pulse 4 is input to the CMI conversion circuit 27, and the CMI code string of the main signal is violated only in the time slot of the violation designation pulse 4. In this way, the transmission path signal 5 (CMI code) which has been violated is sent to the receiving unit 26 according to the frame pattern signal 3, the auxiliary signal 2 and the auxiliary signal 2 '.

On the other hand, in the receiver 26, a violation detection circuit
At 31, the time slot with the violation in the CMI code string of the transmission path signal 5 is detected, and the violation position pulse 8 which becomes “1” at the time slot position is generated,
It is sent to the frame synchronization circuit 32 and the auxiliary signal separation circuit 33. The frame synchronization circuit 32 detects the frame pattern signal in the violation position pulse 8 to establish synchronization, and sets "1" at the time slot position where the auxiliary signal should be superimposed.
The auxiliary signal superposition position pulse 9 is generated and sent to the auxiliary signal separation circuit 33. The auxiliary signal separation circuit 33 detects the sign of the violation position pulse 8 at the time slot position where the auxiliary signal superposition position pulse 9 is "1", separates the auxiliary signal, and the auxiliary signal output 7 is also similarly assisted. The auxiliary signal output 7'is output by the signal superposition position pulse 9'and the violation position pulse 8. A time chart of each section in FIG. 4 is shown in FIG. In FIG. 4, 10 is a clock pulse. In the figure, (* 1) to (* 5) have the following meanings.

(* 1) Symbol Sn of auxiliary signal input 2 or auxiliary signal input 2 '
Or, when Sn '(n = 1,2,3 ...) is "0", it is "0", Sn or S
"1" when n'is "1".

(* 2) Code Fn of frame pattern signal 3 (n = 1, 2, 3,
…) Is “0”, “0”, Fn is “1”, “1”.

(* 3) Violation designation pulse 4 indicates no violation when the sign is “0”, violation is present when “1”.

(* 4) The code of the transmission path signal 5 (CMI code) is "0" when there is no violation and "1" when there is violation.

(* 5) When the sign of the violation position pulse 8 is "0", the sign Sn of the auxiliary signal output 7 or the auxiliary signal output 7'or
Sn 'is "0", and when it is "1", Sn or Sn' is "1".

Further, in the method of alternately superimposing the auxiliary signal on a frame-by-frame basis, the auxiliary signal superimposing time slot in one frame is only 1 bit, and for example, the auxiliary signal superimposing time slot in an odd number frame is for the auxiliary signal 2. The auxiliary signal superposition time slot in the even-numbered frame is used for the auxiliary signal 2 '.

[Problems to be solved by the invention]

As described above, in the conventional method, the transmission side assembles a frame for violation and the reception side synchronizes the frame to separate the auxiliary signal. A circuit that generates a frame pattern, a circuit that detects the frame pattern in the code string of the received violation, a synchronization pull-in circuit that establishes synchronization, and a synchronization protection circuit that protects synchronization against code errors are required. Therefore, there is a drawback that the circuit is complicated and the scale becomes considerably large.

An object of the present invention is to provide an auxiliary signal transmission system that solves the above problems.

[Means for solving the problem]

In order to achieve the above-mentioned object, the auxiliary signal transmission method according to the present invention uses a CMI code as a transmission path code, performs CMI coding rule violation corresponding to the auxiliary signal, and superimposes a plurality of auxiliary signals on the main signal. Then, the transmitting side transmits the signal from the receiving side to the receiving side, and the transmitting side uses CMI conversion circuits for CMI conversion of the main signal and n (n: number of auxiliary signals to be superimposed) sampling auxiliary signals. The sampling circuit and the sampling circuit are individually connected, and when the sampling circuit signal is “0”, this time slot and 1 ₁ to 1 _n (1 ₁ to 1 _n ≧ 1 integer, 1 ₁ ≠ 1 ₂ ≠ ... 1 _n-1 ≠ 1 _n ) bits later, CMI code violation is specified in the time slot, and when the sampling circuit output signal is "1", this time slot and m ₁ ~ m _n (m ₁ ~ m An integer of _n ≧ 1, m ₁ ≠ m ₂ ≠ ... m _n-1
≠ m _n and m _{1 to} m _n are _values other than 1 ₁ to 1 _{n and} the intervals of each violation pulse are not the same) n violation designations that specify the CMI code rule violation in the time slot after bit A circuit is provided to superimpose a plurality of auxiliary signals on the main signal for transmission, and the receiving side obtains the original main signal from the received CMI code sequence.
MI decoding circuit, violation signal of CMI code rule with (1 ₁ -1) bit interval and violation signal of CMI code rule with (m ₁ -1) bit interval, (1 ₂ -1) bit interval and (m ₂
-1) Bit interval ... (1 _n-1 -1) bit interval and (m _n-1 )
Of n number of violation detection circuits for detecting the CMI code rule violation signals of bit intervals and (1 _n −1) bit intervals and (m _n −1) bit intervals, and the n number of violation detection circuits An auxiliary signal decoding circuit for obtaining the original auxiliary signal from each output is provided, and a plurality of auxiliary signals superimposed on the main signal are individually decoded.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention in which the number of auxiliary signals is two.

In the figure, the transmitting unit 34 has a main signal 1 (usually a binary code).
To a CMI code, a sampling circuit 37 for sampling the auxiliary signal 2, and an auxiliary signal 2 '.
The output signals of sampling circuit 38 and sampling circuit 37
When 11 is “0”, this time slot and l ₁ (l ₁ ≧ 1
When the output signal 11 of the sampling circuit 37 is "1", the violation is specified in the time slot after (integer number of) and m ₁ (m ₁ ≧ 1 and an integer other than l ₁ ) bit after this time slot. When the output signal 11 of the sampling circuit 38 is "0", the violation designation circuit 39 for designating the violation in the time slot and this time slot and l ₂ (l ₂ ≧ 1 and an integer other than l ₁ and m ₁ 1l ₂
‐L ₁ -11 ≠ l ₂ −1 ≠ m ₂ -1,1l ₂ −l ₁ -11 ≠ l ₂ −1 ≠ m ₂ −
1) Violation is designated in the time slot after one bit, and when the output signal 11 'of the sampling circuit 38 is "1", this time slot and m ₂ (m ₂ ≧ 1 l ₁ , m
An integer other than ₁ and l ₂ 1m ₂ ‐l ₁ -11 ≠ m ₂ −1 ≠ l ₂ -1,1m ₂
-M ₁ -11 ≠ m ₂ -1 ≠ l ₂ -1) It is constituted by the violation designation circuit 40 which performs the violation designation in the time slot after.

The receiving unit 35 receives the transmission path signal sent through the transmission path.
CMI to obtain main signal 6 (usually binary code) from 13 (CMI code)
The decoding circuit 41 and the violation of the (l ₁ -1) bit interval and the violation of the (m ₁ -1) bit interval in the CMI code string are detected, and the output 14 thereof is sent to the auxiliary signal decoding circuit 44. The detection circuit 42 and (l in the CMI code string
₂ −1) bit interval violation and (m ₂ −1)
Detects bit interval violation and outputs it 14 '
Detection circuit that sends the signal to the auxiliary signal decoding circuit 45
43, a first auxiliary signal decoding circuit 44 for decoding the auxiliary signal, and a second auxiliary signal decoding circuit 45.

Below, the number of auxiliary signals is 2 (n = 2) and l ₁ = 1, l ₂ = 5, m ₁
= 2, m ₂ = 8, the time chart of each part of the present invention is shown in FIG. 2 and the operation is shown.

The main signal 1 input to the transmission unit 34 is converted into a CMI code string by the CMI encoding circuit 36. On the other hand, the auxiliary signal 2 input to the transmitter 34 is sampled by the sampling circuit 37 and becomes the sampling output 11. When the sampling output 11 is "0", the violation specifying circuit 39 specifies the violation in this time slot and the time slot after l ₁ (l ₁ ≥1) bits, and the sampling output 11 is "1". In this case, the violation is designated in this time slot and the time slot after m ₁ (m ₁ ≧ 1 and an integer other than l ₁ ) bits. Similarly, the auxiliary signal 2'input to the transmitting section 34 is supplied to the sampling circuit 38.
Is sampled at to become a sampling output 11 '. In the violation designation circuit 40, when the sampling output 11 ′ is “0”, this time slot and l ₂ (l ₂ ≧ 1 and l ₁ and an integer other than m ₁ are 1 ₂ −l ₁ −11 ≠ l ₂ −1 ≠ m ₂ -1,1 ₂
-L ₁ -11 ≠ l ₂ -1 ≠ m ₂ -1) Violation is specified in the time slot after bit, and when the sampling output signal 11 ′ is “1”, this time slot and m ₂
(M ₂ ≧ 1 and an integer other than l ₁ , m ₁ and l ₂ is 1m ₂ −l ₁ −11 ≠ m ₂ −
1 ≠ l ₂ -1,1m ₂ -m ₁ -11 ≠ m ₂ -1 ≠ l ₂ -1) Violation is designated in the time slot after the bit.
Violation designation pulse by the output of the violation designation circuit 39 and the output of the violation designation circuit 40.
Make twelve.

The violation designation pulse 12 is input to the CMI conversion circuit 36, and the CMI code string of the main signal is violated only in the time slot of the violation designation pulse. In this way, the transmission path signal 13 (CMI code) violated according to the auxiliary signal 2 and the auxiliary signal 2 '
Is sent to the receiving unit 35.

On the other hand, the transmission path signal 13 sent by the receiving unit 35
(CMI code) is sent to the violation detection circuit 42 and the violation detection circuit 43, and at the same time, the CMI decoding circuit 4
It is sent to 1 and returned to the original main signal 6. The violation detection circuit 42 performs the violation detection of the (l ₁ -1) bit interval and the violation detection of the (m ₁ -1) bit interval in the CMI code string 13, and its output 14 is the auxiliary signal decoding circuit. It is returned to the original auxiliary signal 7 by 44. Similarly, in the violation detection circuit 43, the violation detection at the (l ₂ -1) bit interval and the violation detection at the (m ₂ -1) bit interval in the CMI code string 13 are performed, and its output 14 'is The auxiliary signal decoding circuit 45 restores the original auxiliary signal 7 '.

 Reference numeral 15 in FIGS. 1 and 2 is a clock pulse.

(* 6) to (* 14) in FIG. 2 have the following meanings.

(* 6) Symbol S of auxiliary signal input 2 or auxiliary signal input 2 '
"0" when r, S'r is "0", "1" when Sr, S'r is "1".

(* 7) Always "1".

(* 8) “1” when sampling output 11 is “0”, “0” when it is “1”.

(* 9) “0” when the sampling output 11 is “0”, “1” when it is “1”.

(* 10) "1", "1" when sampling output 11 'is "0"
Is “0”.

(* 11) "0", "1" when sampling output 11 'is "0"
When "1".

(* 12) Violation designated pulse 12 is violated when it is “1”, and is not violated when it is “0”.

(* 13) "0" when the presence of violation appears continuously in the code of the transmission path signal 13 (CMI code), and "1" when the presence of violation appears every other bit.

(* 14) "0" when the presence of violation appears every 4 bits in the code of the transmission path signal 13 (CMI code), "1" when it appears every 7 bits.

〔The invention's effect〕

As described above, the present invention performs the CMI code rule violation of a plurality of auxiliary signals, and when superimposing the auxiliary signal on the main signal, the violation occurrence interval by each auxiliary signal is appropriately set, and the violation occurrence interval is Superimposing them so that they are not the same, and decoding the auxiliary signal only at the violence generation interval at the receiving section does not require a complicated and large-scale circuit such as a synchronization protection circuit, and is simple and relatively small. The circuit has the effect of enabling multiple auxiliary signal transmissions using CMI code violation.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of an auxiliary signal transmission system according to the present invention, FIG. 2 is a time chart of the configuration of the auxiliary signal transmission system according to the present invention, and FIG. 3 shows a general operation of a CMI code. 4 and 5 are configuration diagrams showing a conventional auxiliary signal transmission system, and FIG. 5 is a time chart of a configuration showing the conventional auxiliary signal transmission system. 1 ... Main signal (normal binary code) input 2, 2 '... Auxiliary signal input 3 ... Frame pattern signal 4, 12 ... Violation designation pulse 5, 13 ... Transmission line signal (CMI code) 6 ... Main signal (normal) Binary code) Output 7,7 '... Auxiliary signal output 8 ... Violation position pulse 9,9' ... Auxiliary signal superposition position pulse 10,15 ... Clock pulse 11,11 '... Sampling auxiliary signal 14,14' ... Violation Detection output 25 ... Conventional transmitter, 26 ... Conventional receiver 27,36 ... CMI conversion circuit 28,37,38 ... Sampling circuit 29 ... Frame pattern generation circuit 30,41 ... CMI decoding circuit 31,42,43 ... Bio Ratio detection circuit 32 ... Frame synchronization circuit 33 ... Auxiliary signal separation circuit 34 ... Transmission unit, 35 ... Reception unit 39, 40 ... Violation designation pulse generation circuit 44, 45 ... Auxiliary signal decoding circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-60-55760 (JP, A) JP-A-64-30342 (JP, A) JP-A-1-122226 (JP, A)

Claims (1)

(57) [Claims] 1. A method in which a CMI code is used as a transmission path code, CMI code rule violation is performed corresponding to an auxiliary signal, and a plurality of auxiliary signals are superimposed on a main signal and transmitted from a transmission side to a reception side. Therefore, the transmitting side is connected to the CMI conversion circuit that performs CMI conversion of the main signal, the n sampling circuits (n: the number of auxiliary signals to be superimposed) that sample the auxiliary signal, and the sampling circuits that are individually connected. , When the sampling circuit signal is “0”, this time slot and 1 ₁ to 1 _n (1 ₁ to 1 _n ≧ 1 integer,
1 ₁ ≠ 1 ₂ ≠ ... 1 _n-1 ≠ 1 _n ) CMI coding rule violation is specified in the time slot after the bit, and when the sampling circuit output signal is "1", this time slot and m ₁ ~ m _n (m _{1 to} m _n ≧ 1 integer, m ₁ ≠ m ₂ ≠ ... m _n-1 ≠ m _n
Where m _{1 to} m _n are _values other than 1 ₁ to 1 _{n and} the intervals of each violation pulse are not the same) n number of violation specifying circuits that specify the CMI coding rule violation in the time slot after bit It is equipped with a plurality of auxiliary signals superimposed on the main signal for transmission, and the receiving side obtains the original main signal from the received CMI code string.
Decoding circuit, violation code of CMI code rule of (1 ₁ -1) bit interval and violation signal of CMI code rule of (m ₁ -1) bit interval, (1 ₂ -1) bit interval and (m ₂ −
1) Bit interval ... (1 _n-1 -1) bit interval and (m _n-1 ) bit interval and (1 _n -1) bit interval and (m _n -1) bit interval violation signal of CMI coding rule A number of violence detection circuits for detecting each of the above, and n number of auxiliary signal decoding circuits for obtaining the original auxiliary signal by the output of each of the n number of violation detection circuits. An auxiliary signal transmission method characterized in that the auxiliary signal is individually decoded.