JPS6430342A - Transmitter - Google Patents

Transmitter

Info

Publication number
JPS6430342A
JPS6430342A JP62185385A JP18538587A JPS6430342A JP S6430342 A JPS6430342 A JP S6430342A JP 62185385 A JP62185385 A JP 62185385A JP 18538587 A JP18538587 A JP 18538587A JP S6430342 A JPS6430342 A JP S6430342A
Authority
JP
Japan
Prior art keywords
subsignal
cmi
circuit
violation
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62185385A
Other languages
Japanese (ja)
Inventor
Akira Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62185385A priority Critical patent/JPS6430342A/en
Publication of JPS6430342A publication Critical patent/JPS6430342A/en
Pending legal-status Critical Current

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  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To eliminate a necessity to add a frame synchronizing bit for a subsignal and to make it sufficient to prepare a violation bit of a CMI(Coded Mark Inversion) code rule by a subsignal degree by making the violation interval of the CMI to superimpose the subsignal into two kinds or more. CONSTITUTION:The titled device is composed of a CMI encoding circuit 1 to CMI-encode a main signal, a subsignal imposing circuit 2 to make the output of the circuit 1 into an input and execute the violation of the CMI code rule corresponding to the subsignal for two kinds or more of bit intervals of the main signal, a subsignal separating circuit 3 to be connected at the output side of the circuit 2 and to separate the subsignal by identifying the violation of the CMI code rule and the violation interval, and a CMI decoding circuit 4 to make the output of the circuit 3 into an input and to decode the CMI code. Thus, it is not necessary to add a synchronizing bit for the subsignal for a subsignal superimposing, and it is sufficient to prepare the bit of only the subsignal to be superimposed to the main signal for the violation of the CMI code rule.
JP62185385A 1987-07-27 1987-07-27 Transmitter Pending JPS6430342A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62185385A JPS6430342A (en) 1987-07-27 1987-07-27 Transmitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62185385A JPS6430342A (en) 1987-07-27 1987-07-27 Transmitter

Publications (1)

Publication Number Publication Date
JPS6430342A true JPS6430342A (en) 1989-02-01

Family

ID=16169884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62185385A Pending JPS6430342A (en) 1987-07-27 1987-07-27 Transmitter

Country Status (1)

Country Link
JP (1) JPS6430342A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0342933A (en) * 1989-07-11 1991-02-25 Nec Corp Auxiliary signal transmission system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0342933A (en) * 1989-07-11 1991-02-25 Nec Corp Auxiliary signal transmission system

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