CA2088210A1 - Procedure for synchronizing circuit elements of a telecommunications system - Google Patents
Procedure for synchronizing circuit elements of a telecommunications systemInfo
- Publication number
- CA2088210A1 CA2088210A1 CA 2088210 CA2088210A CA2088210A1 CA 2088210 A1 CA2088210 A1 CA 2088210A1 CA 2088210 CA2088210 CA 2088210 CA 2088210 A CA2088210 A CA 2088210A CA 2088210 A1 CA2088210 A1 CA 2088210A1
- Authority
- CA
- Canada
- Prior art keywords
- bit
- pulse
- frame
- sequence
- circuit elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 230000001360 synchronised effect Effects 0.000 claims abstract description 34
- 238000012806 monitoring device Methods 0.000 claims abstract description 20
- 230000001960 triggered effect Effects 0.000 claims description 4
- 230000002950 deficient Effects 0.000 description 7
- 230000000630 rising effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000005236 sound signal Effects 0.000 description 6
- 108010076504 Protein Sorting Signals Proteins 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 108010000178 IGF-I-IGFBP-3 complex Proteins 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0691—Synchronisation in a TDM node
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Time-Division Multiplex Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
Abstract The present invention relates to a process for synchronizing the circuit elements of a digital telecommunications systems, with at least one central clock system that is connected to the synchronizing and clock pulse failure monitoring devices of the circuit elements through a bit pulse line and a frame pulse line.
A first, predetermined, sequence of signal states that is generated by the clock and sent out on the frame pulse line, and which is at least two bits long, is identified by the synchronizing devices of the circuit elements that are to be synchronized as a frame synchronous word; and in that a second sequence of alternating signal states is transmitted between sequential frame synchronous words, this being different from the first predetermined sequence and serving to post-trigger the clock pulse failure monitoring devices. This leads to a more frequent change of state on the frame pulse line, and this can be utilized by the clock pulse failure monitoring devices in order to identify drop-out or error more rapidly.
A first, predetermined, sequence of signal states that is generated by the clock and sent out on the frame pulse line, and which is at least two bits long, is identified by the synchronizing devices of the circuit elements that are to be synchronized as a frame synchronous word; and in that a second sequence of alternating signal states is transmitted between sequential frame synchronous words, this being different from the first predetermined sequence and serving to post-trigger the clock pulse failure monitoring devices. This leads to a more frequent change of state on the frame pulse line, and this can be utilized by the clock pulse failure monitoring devices in order to identify drop-out or error more rapidly.
Description
~882~
A PROCEDURE FOR SYNCHRONIZING CIRCUIT ELEMENTS
OF A TELECOMMUNICATIONS SYSTEM
The present invention relates to a procPss for synchronizing the circuit elements of a digital telecommunications systems, with at least one c~ntral clock system that is connected to the synchronizi~g and clock pulse failure monitoring devices of the circuit elements through a bit pulse line and a frame pulse line.
In digital telecommunications systems, subscribers' lines and inter-office trunk lines are connectPd through appropriate connector circuits to a digital switching field. These connections to the digital switching field are effected through lines that are operated in time division multiplexing. These time division multiplex lines have a frame structure in which time windows, within which the connected circuit elements may access the line, are repeated regularly in sequential timeframes.
Thus, access to these time division multiplex lines must be synchronized by bit and by frame in order to avoid corruption of the data and to avoid interference from adjacent time windows.
To this end, within the telecommunications system, a bit pulse and a frame pulse are apportioned to all the circuit elements that are to be synchronized on a bit pulse line and a frame pulse line, these being generated from a central clock.
Synchronizing circuits are provided within the circuit elements and these synchronize the intra-circuit pulse signals to the bit pulse and the frame pulse and derive all the internally required pulse signals from the bit or frame pulse, respectively.
In the event that one of the pulse connections to a circuit element is distorted or drops out, it is not possible to synchroni~e to thelbit pulse or the frame pulse. This can lead 2~882~
to faulty accesses to the time division mul~iplex lines and thus to disruption of the particular and to other connections.
In order to avoid this, every circuit element has clock pulse failure monitoring devices that monitor the correctness of the bit pulse and the frame pulse for faults. In the event that a clock pulse failure monitoring device identifies a fault then, as a minimum, access to time division multiplex lines is suppressed within the circuit element so affected.
Because of the low recurrence frequency of the frame pulse, which can be 8 kHz, for example, the absence of this pulse can only be identified with certainty after a period of time that is lengthy relative to internal data transmission. Until this point in time, faulty accesses to a time division multiplex line may have already been made.
For this reason, it is the task of the present invention to describe a procedure with which any disruption/distortion of a frame pulse signal can be identified as quickly as possible.
The present invention solves this problem in that a first predetermined, sequence of signal states that is generated by the clock and sent out on the frame pulse line, and which is at least two bits long, is identified by the synchronizing devices o~ the circuit elements that are to be synchronized as a frame synchronous word; and in that a second sequence o-E alternating signal states is transmitted between sequential frame synchronous words, this being differant from the first predetermined sequence and serving to post-trigger the clock pulse failure monitoring devices.
The frame pulse is formed by a frame synchronous word and an interposed sequence of alternating signal states. This leads to a more frequent change of state on the frame pulse line, and this ' -` 2~2:~0 can be utilized by the clock pulse failure monitoring devices in order to identify drop-out or error more rapidly.
The frame synchronous word can be identified by the synchronizing devices by simple comparison of the signal sequence on the frame pulse line with the predetermined sequence, after which it can be converted to a frame pulse signal within the circuit.
It is preferred that an edge-controlled clock pulse failure monitoring device be used for the frame pu]se line, its response time for error identification being determined by the maximum duration between two signal state changes of the same type on the frame pulse line. Edge-controlled clock pulse failure monitoring devices are particularly simple to realize, and because of the frame pulse signal according to the present invention, the response time is considerably shorter than the time that would result from the recurrence frequency of the frame pulse as in the prior art.
The shortest response time for error identification is achieved if the signal state of the second sequence that is transmitted bett~een sequential frame synchronous words changes with every bit pulse. Then, the maximum duration is determined by the signal state change before or after the frame synchronous word that is at least two bits long.
It is preferred that an 8-bit long frame synchronous word be used. This corresponds to the length of a word or time window, respectively, on the time division multiplex lines and a frame synchronous word can be formed that has a sufficient signal (hamming) distance for the second series that is transmitted between the frame synchronous words.
2 ~
In the same way, the second series that is transmitted between sequential frame synchronous words can also consist of a series of 8-bit words that are built up in the same way.
In a development of the present invention, in each instance one bit of this 8-bit word is used to transmit status information.
~ithout any significant modification of the response time of the clock pulse failure monitoring device, one bit can be used to transmit status information from the clock to all of the circuit elements that are connected to the frame pulse line. In this respect, this can be status information, the content of which alters very seldom and which is related to the pulse delivery or other system states.
In particular in ~he case of tha redundant structure of the telecommunications system, which permits switching between doubled circuit elements and time multiplex lines, information concerning current status can be transmitted as status information.
The present invention will be described in greater detail below on the basis of one embodiment that is shown in the drawings appended hereto. These drawings show the following:
igure 1: a block circuit diagram of a telecommunications system with a redundant structure;
Figure 2: time diagrams of the bit pulse and frame pulse signals;
Figure 3: time diagrams to determine the response time of the pulse monitoring device.
Figure 1 is a block-circuit diagram of a telecommunications system that is constructed so as to incorporate redundancy, in which the circuit elements and connection lines that are required by a plurality of circuit elements together to form a connection ~rn ~ hl.od.
A first clock 10 is connected through a bit pulse line BT and a frame pulse line RT to an audio signal generator 12, a redundant audio signal generator 12', a digital switching field 1~, a redundant digital switching field 14', the connector group 16, a central control 18, and a redundant central control 18'.
A redundant clock 10' is connected through a second bit pulse line BT' and a second frame pulse line RT' to the audio signal generator 12, the redundant audio signal generator 12', the digital switching field 14, the redundant digital switching field 14', the connector group 16, the central control 18, and the redundant central control 18'.
The connector group 16 and the audio signal generators 12, 12' are connected through the first time division multiplex lines 20, 22, 24, and the redundant time division multiplex lines 20', 22', and 24', with the digital switching field 14 and the redundant digital switching field 14'.
For reasons of clarity, the subscriber lines by which the subscriber end devices are connected to the connector group are not shown in this diagram. In order to provide connection control, the connector groups 16 are connected by similar control lines 30, 32, which are similarly operated in time division multiplex and through redundant control lines 30', 32', to the central control 18 and the redundant central control 18'.
In order to provide control of the switching fields 14, 14' these are connected through control lines 34, 34' with the central controls 18, 18'. In order to exchange system data, the clock systems 10, 10' and the audio signal generators 12, 12' are 2~82~
connected through the control lines 36, 36' to the central controls 18, 18'.
A telecommunications system that incorporates these redundant circuit elements has a higher level of availability for, in the event of drop-outs or faults, it is possible to re-switch to the redundant circuit elements. To this end, each circuit element has a device that monitors its own functionality as well as that of the connecting lines that are connected to it. If these monitoring devices report a fault, then either the particular circuit element itself or the central control can implement re-switching into the other level of redundancy.
The monitored connection lines also include. the bit pulse and frame pulse line that serves to synchronize all the circuit elements, in particular for access to the time division multiplex lines 20, 22, 24, 23', 22', 24', and the control lines 30, 32, 34, 36, 30', 32', 34', and 36'. In the connected circuit elements 12, 12', 14, 14', 16, 18, and 18', in each instance the bit pulse line BT and the frame pulse line RT or the redundant bi~ pulse line BT' and the frame pulse line RT' are selected for synchronizing.
The time division lines 20, 20', 22, 22', 24, 24' operate with a frame structure which in this embodiment, at a bit pulse of 8192 Khz and a frame pulse with an 8 Khz repetition fre~uency makes 128 time windows available for each 8 bits for signal transmission.
The control lines 30, 30', 32, 32', 34, 34', 36, and 36', which are similarly operated in time division multiplex, also opPrate with a frame structure which for this embodiment, at a bit pulse of 1024 Khz and a frame pulse with 8 kHz repetition ~requency makes 16 time windows available for connection control. The bit - ' : ~' ' - .
-~ ` 2~2~ ~
pulse is derived by internal circuit elements from the pulse onthe bit pulse line BT or sT~, respectively.
Figures 2a and 2b show the bit pulse of 8192 kHz that is transmitted on the bit pulse line BT and the signal sequences that are transmitted on the frame pulse line ~T.
~t time tO, the first sequence begins and this represents the frame synchronous word RSW. In this embodiment the se~uence "0001 1011" is used as the frame synchronous word RSW. At time tl, the second sequence with alternating signal states is joined to this; in the embodiment shown this consists of a sequence of 127 8-bit words FW1, FW2, FW3, FW127 with the content "0101 OlOx." In bit position x, which is shown shaded in figure 2b, different status information can be transmitted from the sending clock to the connected circuit elements in the words that follow each other.
Thus, in the words FW, the content of bit position x may have the following values:
Word FWn Content "O" Content "1"
FWl TG defective TG ok FW2 TG is slave TG is master FW3 Slave/master async Slave/master synchronous FW4 HTG defective HTG ok FW5 HTG' defective HTG' ok FW6 KF defective KF ok FW7 KF' defective KF' ok FW8 Control line n defective Control line n ok FW9 Control line n' defective Control line n' ok -` 2~8~
On the basis of this status information, each circuit element that is connected to the frame tack line can be provided with the systems data that is required for possible re-switching to a redundant function.
A CRC sign is formed by way of all the x bits that contain status information and this is transmitted in the last x-bits and can be evaluated by the receivers. Only when the CRC signs that are transmitted and identified in the receiver are in agreement is there an error-free data transmission and internal control processes can be initiated on the basis of the data contents.
Figure 3 shows time diagrams to determine the response time of an edge-triggered pulse monitoring device. Figure 3a shows the bit pulse BT as a standard for the required times. In figures 3b an~
figure 3c the frame pulse signal from figure 2b is shown with fixed values to determine the maximum response time.
.
Figure 3b applies to a pulse monitoring device that is triggered with the falling signal edge. The first frame synchronous word RSW begins with a falling edge that, after the time nl (5 bit periods), follows the next falling edge. Within the sequence of 8-bit words FW the longest gap occurs between the signal edges when the x-bit has the value "0." This is the case for word FWl.
The time n2 (4 bit periods) passes from the last falling signal edge of the word FW1 to the first falling signal edge of the word FW2. The last x-bit before the frame synchronous words also has the value "0." Thus, the time n3 (7 bit periods) passes from the last falling signal edge of the word FW127 until the first falling signal edge of the frame synchronous word RSW. The time n3 is important as the longest occurring time as response time for the pulse monitoring device. For a bit pulse of 8192 Khz, 7 bit periods correspond to a time of 855 ns. This time i5 considerably shorter than the 125 us of a frame.
- ~
, .
-- 2~2~ ~
Figure 3c applies for a pulse monitoring device that is post-triggered with the rising signal edge. Proceeding from the last rising edge ahead of the first frame synchronous word, after a time pl (4 bit periods) the first rising edge in the frame synchronous word RSW follows. Within the sequence of 8-bit words FW, the longest gap occurs between the signal edges when the x-bit has the value "O." This is the case for word FW1. The time p2 (4 bit periods) passes from the last rising signal edge of the word FWl until the first rising signal edge of the word FW2. The last x-bit before the frame synchronous word also has the value "O." Thus, the time p3 (6 bit periods) passes from the last rising signal edge of the word FW127 until the first rising signal edge of the frame synchronous word RSW. As the longest occurring time, the time p3 is important as the response time for the pulse monitoring device. Six bit periods of a time of 732 ns correspond for a bit pulse of 8192 Xhz. This time is considerably shorter than the 125 us of a frame.
A PROCEDURE FOR SYNCHRONIZING CIRCUIT ELEMENTS
OF A TELECOMMUNICATIONS SYSTEM
The present invention relates to a procPss for synchronizing the circuit elements of a digital telecommunications systems, with at least one c~ntral clock system that is connected to the synchronizi~g and clock pulse failure monitoring devices of the circuit elements through a bit pulse line and a frame pulse line.
In digital telecommunications systems, subscribers' lines and inter-office trunk lines are connectPd through appropriate connector circuits to a digital switching field. These connections to the digital switching field are effected through lines that are operated in time division multiplexing. These time division multiplex lines have a frame structure in which time windows, within which the connected circuit elements may access the line, are repeated regularly in sequential timeframes.
Thus, access to these time division multiplex lines must be synchronized by bit and by frame in order to avoid corruption of the data and to avoid interference from adjacent time windows.
To this end, within the telecommunications system, a bit pulse and a frame pulse are apportioned to all the circuit elements that are to be synchronized on a bit pulse line and a frame pulse line, these being generated from a central clock.
Synchronizing circuits are provided within the circuit elements and these synchronize the intra-circuit pulse signals to the bit pulse and the frame pulse and derive all the internally required pulse signals from the bit or frame pulse, respectively.
In the event that one of the pulse connections to a circuit element is distorted or drops out, it is not possible to synchroni~e to thelbit pulse or the frame pulse. This can lead 2~882~
to faulty accesses to the time division mul~iplex lines and thus to disruption of the particular and to other connections.
In order to avoid this, every circuit element has clock pulse failure monitoring devices that monitor the correctness of the bit pulse and the frame pulse for faults. In the event that a clock pulse failure monitoring device identifies a fault then, as a minimum, access to time division multiplex lines is suppressed within the circuit element so affected.
Because of the low recurrence frequency of the frame pulse, which can be 8 kHz, for example, the absence of this pulse can only be identified with certainty after a period of time that is lengthy relative to internal data transmission. Until this point in time, faulty accesses to a time division multiplex line may have already been made.
For this reason, it is the task of the present invention to describe a procedure with which any disruption/distortion of a frame pulse signal can be identified as quickly as possible.
The present invention solves this problem in that a first predetermined, sequence of signal states that is generated by the clock and sent out on the frame pulse line, and which is at least two bits long, is identified by the synchronizing devices o~ the circuit elements that are to be synchronized as a frame synchronous word; and in that a second sequence o-E alternating signal states is transmitted between sequential frame synchronous words, this being differant from the first predetermined sequence and serving to post-trigger the clock pulse failure monitoring devices.
The frame pulse is formed by a frame synchronous word and an interposed sequence of alternating signal states. This leads to a more frequent change of state on the frame pulse line, and this ' -` 2~2:~0 can be utilized by the clock pulse failure monitoring devices in order to identify drop-out or error more rapidly.
The frame synchronous word can be identified by the synchronizing devices by simple comparison of the signal sequence on the frame pulse line with the predetermined sequence, after which it can be converted to a frame pulse signal within the circuit.
It is preferred that an edge-controlled clock pulse failure monitoring device be used for the frame pu]se line, its response time for error identification being determined by the maximum duration between two signal state changes of the same type on the frame pulse line. Edge-controlled clock pulse failure monitoring devices are particularly simple to realize, and because of the frame pulse signal according to the present invention, the response time is considerably shorter than the time that would result from the recurrence frequency of the frame pulse as in the prior art.
The shortest response time for error identification is achieved if the signal state of the second sequence that is transmitted bett~een sequential frame synchronous words changes with every bit pulse. Then, the maximum duration is determined by the signal state change before or after the frame synchronous word that is at least two bits long.
It is preferred that an 8-bit long frame synchronous word be used. This corresponds to the length of a word or time window, respectively, on the time division multiplex lines and a frame synchronous word can be formed that has a sufficient signal (hamming) distance for the second series that is transmitted between the frame synchronous words.
2 ~
In the same way, the second series that is transmitted between sequential frame synchronous words can also consist of a series of 8-bit words that are built up in the same way.
In a development of the present invention, in each instance one bit of this 8-bit word is used to transmit status information.
~ithout any significant modification of the response time of the clock pulse failure monitoring device, one bit can be used to transmit status information from the clock to all of the circuit elements that are connected to the frame pulse line. In this respect, this can be status information, the content of which alters very seldom and which is related to the pulse delivery or other system states.
In particular in ~he case of tha redundant structure of the telecommunications system, which permits switching between doubled circuit elements and time multiplex lines, information concerning current status can be transmitted as status information.
The present invention will be described in greater detail below on the basis of one embodiment that is shown in the drawings appended hereto. These drawings show the following:
igure 1: a block circuit diagram of a telecommunications system with a redundant structure;
Figure 2: time diagrams of the bit pulse and frame pulse signals;
Figure 3: time diagrams to determine the response time of the pulse monitoring device.
Figure 1 is a block-circuit diagram of a telecommunications system that is constructed so as to incorporate redundancy, in which the circuit elements and connection lines that are required by a plurality of circuit elements together to form a connection ~rn ~ hl.od.
A first clock 10 is connected through a bit pulse line BT and a frame pulse line RT to an audio signal generator 12, a redundant audio signal generator 12', a digital switching field 1~, a redundant digital switching field 14', the connector group 16, a central control 18, and a redundant central control 18'.
A redundant clock 10' is connected through a second bit pulse line BT' and a second frame pulse line RT' to the audio signal generator 12, the redundant audio signal generator 12', the digital switching field 14, the redundant digital switching field 14', the connector group 16, the central control 18, and the redundant central control 18'.
The connector group 16 and the audio signal generators 12, 12' are connected through the first time division multiplex lines 20, 22, 24, and the redundant time division multiplex lines 20', 22', and 24', with the digital switching field 14 and the redundant digital switching field 14'.
For reasons of clarity, the subscriber lines by which the subscriber end devices are connected to the connector group are not shown in this diagram. In order to provide connection control, the connector groups 16 are connected by similar control lines 30, 32, which are similarly operated in time division multiplex and through redundant control lines 30', 32', to the central control 18 and the redundant central control 18'.
In order to provide control of the switching fields 14, 14' these are connected through control lines 34, 34' with the central controls 18, 18'. In order to exchange system data, the clock systems 10, 10' and the audio signal generators 12, 12' are 2~82~
connected through the control lines 36, 36' to the central controls 18, 18'.
A telecommunications system that incorporates these redundant circuit elements has a higher level of availability for, in the event of drop-outs or faults, it is possible to re-switch to the redundant circuit elements. To this end, each circuit element has a device that monitors its own functionality as well as that of the connecting lines that are connected to it. If these monitoring devices report a fault, then either the particular circuit element itself or the central control can implement re-switching into the other level of redundancy.
The monitored connection lines also include. the bit pulse and frame pulse line that serves to synchronize all the circuit elements, in particular for access to the time division multiplex lines 20, 22, 24, 23', 22', 24', and the control lines 30, 32, 34, 36, 30', 32', 34', and 36'. In the connected circuit elements 12, 12', 14, 14', 16, 18, and 18', in each instance the bit pulse line BT and the frame pulse line RT or the redundant bi~ pulse line BT' and the frame pulse line RT' are selected for synchronizing.
The time division lines 20, 20', 22, 22', 24, 24' operate with a frame structure which in this embodiment, at a bit pulse of 8192 Khz and a frame pulse with an 8 Khz repetition fre~uency makes 128 time windows available for each 8 bits for signal transmission.
The control lines 30, 30', 32, 32', 34, 34', 36, and 36', which are similarly operated in time division multiplex, also opPrate with a frame structure which for this embodiment, at a bit pulse of 1024 Khz and a frame pulse with 8 kHz repetition ~requency makes 16 time windows available for connection control. The bit - ' : ~' ' - .
-~ ` 2~2~ ~
pulse is derived by internal circuit elements from the pulse onthe bit pulse line BT or sT~, respectively.
Figures 2a and 2b show the bit pulse of 8192 kHz that is transmitted on the bit pulse line BT and the signal sequences that are transmitted on the frame pulse line ~T.
~t time tO, the first sequence begins and this represents the frame synchronous word RSW. In this embodiment the se~uence "0001 1011" is used as the frame synchronous word RSW. At time tl, the second sequence with alternating signal states is joined to this; in the embodiment shown this consists of a sequence of 127 8-bit words FW1, FW2, FW3, FW127 with the content "0101 OlOx." In bit position x, which is shown shaded in figure 2b, different status information can be transmitted from the sending clock to the connected circuit elements in the words that follow each other.
Thus, in the words FW, the content of bit position x may have the following values:
Word FWn Content "O" Content "1"
FWl TG defective TG ok FW2 TG is slave TG is master FW3 Slave/master async Slave/master synchronous FW4 HTG defective HTG ok FW5 HTG' defective HTG' ok FW6 KF defective KF ok FW7 KF' defective KF' ok FW8 Control line n defective Control line n ok FW9 Control line n' defective Control line n' ok -` 2~8~
On the basis of this status information, each circuit element that is connected to the frame tack line can be provided with the systems data that is required for possible re-switching to a redundant function.
A CRC sign is formed by way of all the x bits that contain status information and this is transmitted in the last x-bits and can be evaluated by the receivers. Only when the CRC signs that are transmitted and identified in the receiver are in agreement is there an error-free data transmission and internal control processes can be initiated on the basis of the data contents.
Figure 3 shows time diagrams to determine the response time of an edge-triggered pulse monitoring device. Figure 3a shows the bit pulse BT as a standard for the required times. In figures 3b an~
figure 3c the frame pulse signal from figure 2b is shown with fixed values to determine the maximum response time.
.
Figure 3b applies to a pulse monitoring device that is triggered with the falling signal edge. The first frame synchronous word RSW begins with a falling edge that, after the time nl (5 bit periods), follows the next falling edge. Within the sequence of 8-bit words FW the longest gap occurs between the signal edges when the x-bit has the value "0." This is the case for word FWl.
The time n2 (4 bit periods) passes from the last falling signal edge of the word FW1 to the first falling signal edge of the word FW2. The last x-bit before the frame synchronous words also has the value "0." Thus, the time n3 (7 bit periods) passes from the last falling signal edge of the word FW127 until the first falling signal edge of the frame synchronous word RSW. The time n3 is important as the longest occurring time as response time for the pulse monitoring device. For a bit pulse of 8192 Khz, 7 bit periods correspond to a time of 855 ns. This time i5 considerably shorter than the 125 us of a frame.
- ~
, .
-- 2~2~ ~
Figure 3c applies for a pulse monitoring device that is post-triggered with the rising signal edge. Proceeding from the last rising edge ahead of the first frame synchronous word, after a time pl (4 bit periods) the first rising edge in the frame synchronous word RSW follows. Within the sequence of 8-bit words FW, the longest gap occurs between the signal edges when the x-bit has the value "O." This is the case for word FW1. The time p2 (4 bit periods) passes from the last rising signal edge of the word FWl until the first rising signal edge of the word FW2. The last x-bit before the frame synchronous word also has the value "O." Thus, the time p3 (6 bit periods) passes from the last rising signal edge of the word FW127 until the first rising signal edge of the frame synchronous word RSW. As the longest occurring time, the time p3 is important as the response time for the pulse monitoring device. Six bit periods of a time of 732 ns correspond for a bit pulse of 8192 Xhz. This time is considerably shorter than the 125 us of a frame.
Claims (9)
1. A process for synchronizing the circuit elements of a telecommunications system, with at least one central clock that is connected with the synchronizing devices and the clock pulse failure monitoring devices of the circuit elements through a bit pulse line and a frame pulse line, characterized in that a first predetermined sequence of signal states that is at least two bits long and that is generated by the clock and sent on the frame pulse line is identified as a frame synchronous word by the synchronizing devices of the circuit elements that are to be synchronized;
and in that a second sequence of alternating signal states, which is different from the first predetermined sequence, is transmitted between sequential frame synchronous words, this serving to trigger the block pulse failure monitoring devices.
and in that a second sequence of alternating signal states, which is different from the first predetermined sequence, is transmitted between sequential frame synchronous words, this serving to trigger the block pulse failure monitoring devices.
2. A process as defined in claim 1, characterized in that an edge-triggered clock pulse failure device is used, the response time of which is determined by the maximum duration between two identical signal state changes on the frame pulse line.
3. A process as defined in claim 1, characterized in that the signal state of the second sequence, which is transmitted between sequential frame synchronous words, changes with each bit pulse.
4. A process as defined in one of the preceding claims, characterized in that an 8-bit long frame synchronous word is used.
5. A process as defined in claim 4, characterized in that the sequence "0001 1011" is used as the frame synchronous word.
6. A process as defined in one of the preceding claims, characterized in that the second sequence, which is transmitted between sequential frame synchronous words, consists of a series of identically composed 8-bit words.
7. A process as defined in claim 6, characterized in that in each instance one bit of this 8-bit word can be used to transmit status information.
8. A process as defined in claim 7, characterized in that the 8-bit word consists of the sequence "0101 010x," x distinguishing the bit that can be used for transmitting status information.
9. A process as defined in claim 7 or claim 8, characterized in that a CRC sign is formed from the n-m status information that is transmitted and this is transmitted, n indicating the number of 8-bit words between sequential frame synchronous words and m indicating the length of the CRC
sign.
sign.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP4202341.6 | 1992-01-29 | ||
| DE19924202341 DE4202341A1 (en) | 1992-01-29 | 1992-01-29 | METHOD FOR SYNCHRONIZING CIRCUIT PARTS OF A TELECOMMUNICATION SYSTEM |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2088210A1 true CA2088210A1 (en) | 1993-07-30 |
Family
ID=6450436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2088210 Abandoned CA2088210A1 (en) | 1992-01-29 | 1993-01-27 | Procedure for synchronizing circuit elements of a telecommunications system |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0553610A1 (en) |
| JP (1) | JPH0722286B2 (en) |
| CA (1) | CA2088210A1 (en) |
| DE (1) | DE4202341A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4329733A1 (en) * | 1993-09-03 | 1995-03-09 | Sel Alcatel Ag | Time division multiplexing |
| DE4448022B4 (en) * | 1994-08-09 | 2010-01-28 | Thermozell Entwicklungs- Und Vertriebs Ges.M.B.H. | Polystyrene bells, as well as its use |
| DE4442506A1 (en) * | 1994-11-30 | 1996-06-05 | Sel Alcatel Ag | Synchronization monitoring in a network |
| CA2240633A1 (en) * | 1995-12-15 | 1997-06-26 | Telefonaktiebolaget Lm Ericsson | Error correcting timing reference distribution |
| NZ330678A (en) * | 1995-12-15 | 1999-11-29 | Ericsson Telefon Ab L M | Discrete phase locked loop |
| US6081550A (en) * | 1997-02-26 | 2000-06-27 | Alcatel | Method of testing clock paths and network elements for carrying out the method |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2351478C3 (en) * | 1973-10-13 | 1981-10-01 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Method for synchronizing the time frame in the receiver of a time division multiplex transmission system with the time frame of the transmitter |
| US4316385A (en) * | 1980-06-18 | 1982-02-23 | General Electric Company | Fingerprinting crystals |
| JPS59147155A (en) * | 1983-02-09 | 1984-08-23 | Daikin Mfg Co Ltd | Power transmission mechanism with fluid coupling |
| DE3643002A1 (en) * | 1986-12-17 | 1988-06-30 | Philips Patentverwaltung | CIRCUIT ARRANGEMENT FOR SYNCHRONIZING DEVICES IN THE SWITCHING AND AMPLIFIER POINTS OF A TIME MULTIPLEX TRANSMISSION SYSTEM |
| US5048062A (en) * | 1989-10-30 | 1991-09-10 | International Business Machines Corp. | Transmitting commands over a serial link |
| DE59008809D1 (en) * | 1990-06-01 | 1995-05-04 | Siemens Ag | Method and arrangement for transmitting operating status information between central and decentralized devices of a communication system. |
-
1992
- 1992-01-29 DE DE19924202341 patent/DE4202341A1/en not_active Withdrawn
-
1993
- 1993-01-05 EP EP93100069A patent/EP0553610A1/en not_active Withdrawn
- 1993-01-27 CA CA 2088210 patent/CA2088210A1/en not_active Abandoned
- 1993-01-28 JP JP5012381A patent/JPH0722286B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05276154A (en) | 1993-10-22 |
| DE4202341A1 (en) | 1993-08-05 |
| EP0553610A1 (en) | 1993-08-04 |
| JPH0722286B2 (en) | 1995-03-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4397020A (en) | Error monitoring in digital transmission systems | |
| USRE33900E (en) | Error monitoring in digital transmission systems | |
| US4009469A (en) | Loop communications system with method and apparatus for switch to secondary loop | |
| US4316284A (en) | Frame resynchronization circuit for digital receiver | |
| US5926303A (en) | System and apparatus for optical fiber interface | |
| US4316285A (en) | Framing circuit for digital receiver | |
| US5651033A (en) | Inter-system data communication channel comprised of parallel electrical conductors that simulates the performance of a bit serial optical communications link | |
| US4696001A (en) | Reconfigurable high-speed integrated local network | |
| HU219747B (en) | Synchronizing method | |
| US3564145A (en) | Serial loop data transmission system fault locator | |
| CA1109168A (en) | T.d.m. transmission systems | |
| US5081619A (en) | Digital signal multiplex communication system having signal path monitoring function | |
| US4862480A (en) | Digital data service system | |
| US4730302A (en) | Monitoring means for digital signal multiplex equipment | |
| US5566203A (en) | Intelligent repeater functionality | |
| CA2088210A1 (en) | Procedure for synchronizing circuit elements of a telecommunications system | |
| CA1156384A (en) | Error monitoring in digital transmission systems | |
| JP3773959B2 (en) | Frame synchronization | |
| US6490317B1 (en) | Data, path and flow integrity monitor | |
| JP3920261B2 (en) | Frame synchronizer and optical transceiver | |
| JP4712233B2 (en) | Transmission equipment | |
| JPH0425743B2 (en) | ||
| Schneider et al. | A N+ 2 protection switching system for synchronous STM-1 signals and plesiochronous 140 Mbit/s signals by using two carrier technique | |
| JP2500609B2 (en) | Cable misconnection monitoring method | |
| KR20010060690A (en) | A device of fault detection for optical signal path |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Dead |