JP2616695B2 - Line switching device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line switching device, and more particularly to a line switching device for a digital radio communication system having a function of matching data phases between a plurality of carriers.

[0002]

2. Description of the Related Art Conventionally, in a digital microwave radio communication system, a data signal transmitted in a radio section is transmitted by a plurality of carriers and a working line and a protection line are connected in order to reduce the influence of deterioration of radio channel quality. A line switching device is provided which has a redundant configuration with a line and switches to a protection line when a line failure occurs in the working line (for example,
JP-A-4-208732).

FIG. 2 is a block diagram showing an example of the above-mentioned conventional line switching device. Received data (a first working signal) of a certain working line carrier is supplied from an input terminal 1 to a frame synchronization circuit 5, and received data (a second working signal) of another working line carrier is provided at an input terminal. 2 to the frame synchronization circuit 6. In addition, received data (a first protection signal) of one protection channel carrier is supplied from an input terminal 3 to a frame synchronization circuit 7, and reception data (a second protection signal) of another protection channel carrier is provided. It is supplied from an input terminal 4 to a frame synchronization circuit 8.

The frame synchronization circuits 5 and 6 establish the frame synchronization of the input first and second working signals, respectively, and supply them to the synchronization switching circuits 9 and 10. Similarly, the frame synchronization circuits 7 and 8 establish frame synchronization of the input first and second standby signals, respectively, and supply them to the synchronization switching circuits 9 and 10.

[0005] The synchronization switching circuit 9 normally selects the first working system signal from the first working system signal input from the frame synchronization circuit 5 and the first protection system signal input from the frame synchronization circuit 7. When a line failure occurs in the working line, the first protection system signal is selected and output. Similarly, the synchronization switching circuit 10 normally selects the second working system signal from the second working system signal inputted from the frame synchronization circuit 6 and the second protection system signal inputted from the frame synchronization circuit 8. The second protection signal is selected and output only when a line failure occurs in the working line.

In order to finally convert data transmitted on a plurality of carriers into parallel / serial and convert the data signals into a row of data signals, an operation of matching the data phases between the carriers is performed as follows. The first working signal or the first protection signal extracted from the synchronization switching circuit 9 is supplied to the phase matching circuit 11 and the timing generation circuit 13
Supplied to On the other hand, the second working system signal or the second protection system signal extracted from the synchronization switching circuit 10 is supplied to the phase matching circuit 12.

The phase matching circuits 11 and 12 resynchronize output signals of the synchronization switching circuits 9 and 10 based on a timing signal generated by the timing generation circuit 13 using a clock signal in the output signal of the synchronization switching circuit 9 as a reference clock. Perform timing. Thereby, the phase matching circuit 1
From 1 and 12, signals whose data phases are matched between the carriers based on the timing signal are extracted and supplied to signal processing circuits 14 and 15.

[0008] The signal processing circuits 14 and 15 respectively perform signal processing such as extraction of additional bits in the input signal. Parallel /
The serial conversion circuit 16 includes these signal processing circuits 14 and 15
Signals taken out in parallel are received as input signals, converted into serial signals, and output to the output terminal 17 as a series of data.

[0009]

However, in the above-mentioned conventional line switching device, the first working signal or the first protection signal extracted from the synchronization switching circuit 9 is fixedly used as a reference clock. Since the data phases between the carriers are matched, deterioration of line quality or equipment failure occurs in both the working line for transmitting the first working signal and the protection line for transmitting the first protection signal. In this case, the carrier other than the reference (the second working system signal and the second protection system signal) is also affected by this, and there is a problem that the phase matching operation and the signal processing operation are not performed normally.

In the above-mentioned conventional line switching apparatus, the reference carrier is fixedly switched to the working line or the protection line, and when the selected carrier is selected, when the quality of the selected line is degraded, or Also, when a device failure occurs, there is a problem that a carrier which is not a reference is affected by the failure and the phase matching operation and the signal processing operation are not performed normally.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a line switching device that can surely match the data phase between carriers with a simple circuit configuration.

[0012]

According to the present invention, in order to achieve the above object, a plurality of data signals of different carriers are input and a plurality of frame synchronization circuits for separately performing frame synchronization, and a plurality of data signals are provided. A plurality of detecting means for outputting a warning signal when the quality deterioration or the equipment failure is detected, and a detecting means which does not output the warning signal among the plurality of detecting means. A clock selection circuit for selecting a clock signal of a carrier data signal from an output data signal of the frame synchronization circuit; and a phase of a plurality of data signals respectively output from the plurality of frame synchronization circuits based on the output clock signal of the clock selection circuit. And a phase matching means for matching the two.

[0013]

According to the present invention, the timing signal for matching the phases of a plurality of data signals of different carriers by the phase matching means is a clock signal of the carrier data signal detected by the detection means which does not output the alarm signal. Because it is selected and generated by the selection circuit,
A clock signal of a data signal of a carrier having good line quality and having no equipment failure can be used as a reference clock (timing signal) for a phase matching circuit.

[0014]

Next, an embodiment of the present invention will be described. FIG. 1 is a block diagram showing an embodiment of a line switching apparatus according to the present invention. 2, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 1, circuits and signal lines that are not particularly important are not shown.

In this embodiment, as compared with the conventional line switching device shown in FIG. 2, the output data signals of the synchronization switching circuits 9 and 10 and the alarm signals ALM1 and ALM2 are applied, respectively.
Synchronous switching circuit 9 according to alarm signals ALM1 and ALM2
And a clock selection circuit 18 for selecting one of the output data signals of the input terminals 1 and 3, and a signal processing circuit 19 monitors the quality deterioration of the transmission lines of the input signals of the input terminals 1 and 3 and the equipment failure, and the quality deterioration or The alarm signal ALM1 is output when an equipment failure is detected, and the signal processing circuit 20 monitors the quality degradation and equipment failure of the transmission lines of the input signals of the input terminals 2 and 4, and outputs the alarm signal ALM1 when the quality degradation or equipment failure is detected. The feature is that it is configured to output.

Next, the operation of this embodiment will be described.
Similarly to the above-described conventional device, the synchronization switching circuit 9 establishes frame synchronization by the frame synchronization circuit 5 and outputs the working line data (first working system signal) output thereto, and establishes frame synchronization by the frame synchronization circuit 7. The protection line data (first protection system signal) output and output is input and normally outputs a first working system signal. However, if a line failure of the working system occurs, the first protection system signal is output. Select a signal. When the line failure of the working line is recovered, the first working signal of the working line is selected again by the synchronization switching circuit 9.

Similarly, the synchronization switching circuit 10 establishes frame synchronization by the frame synchronization circuit 6 and outputs the working line data (second working system signal), and the frame synchronization circuit 8 establishes frame synchronization and outputs the same. Protection line data (second protection signal) is input,
, The second protection signal is selected when a line failure of the working line occurs. When the line failure of the working line is recovered, the second working signal of the working line is selected again by the synchronization switching circuit 10.

The data output from the synchronization switching circuits 9 and 10 respectively correspond to the phase matching circuits 11 provided correspondingly.
And 12 are separately supplied to the clock selection circuit 1
8 are commonly supplied. The signal processing circuits 19 and 20 receive, as input signals, the data extracted from the phase matching circuits 11 and 12, respectively, and apply the same processing to the input signals as in the prior art such as extraction of additional bits to the parallel / serial conversion circuit 16. In addition to the supply, the quality of the transmission line of the input signal and the presence or absence of equipment failure are monitored based on, for example, the parity bit of the input signal data. The alarm signals ALM1 and ALM2 are also detected when the input signal data has been cut off for a predetermined period of time or longer.
Is generated and output.

The alarm signal ALM1 extracted from the signal processing circuit 19 and the alarm signal ALM2 extracted from the signal processing circuit 20 are supplied to the clock selection circuit 18, respectively. The clock selection circuit 18 outputs the alarm signal A
The clock signal of the transmission data of the line to which the alarm signal is not input is selected from LM1 and ALM2.

That is, when the alarm signal ALM1 is input, the clock selection circuit 18 selects and outputs the clock signal of the output data of the synchronization switching circuit 10, and when the alarm signal ALM2 is input, the clock selection circuit 18 selects the clock signal. 9 to select and output the clock signal of the output data. When neither of the alarm signals ALM1 and ALM2 is input, all the lines are normal, so that the selected state is held (a clock signal of data on a predetermined side may be selected).

In this manner, the clock signal selected by the clock selection circuit 18 is applied to the timing generation circuit 1
3 is supplied as a reference clock to be converted into a timing signal, and then supplied to phase matching circuits 11 and 12, respectively, and the synchronization switching circuits 9 and 10 are supplied with the same timing signal.
By retiming both output signal data,
The data phase between both carriers is made to match.

The data extracted from the phase matching circuits 11 and 12 are separately subjected to the signal processing by the signal processing circuits 19 and 20, and then converted into serial data by the parallel / serial conversion circuit 16 and output to the output terminal. 17 is output.

As described above, according to the present embodiment, the clock signal of the data of the carrier having a good line quality and having no equipment failure is used as the reference clock (timing signal) for the phase matching circuits 11 and 12. Therefore, if a failure occurs in the line or device of one carrier that was the reference, the clock signal of the data of the other carrier will be switched and used as the reference clock, and will be transmitted to the other carrier. It is possible to simply and reliably match the data phases between the two carriers without affecting them.

It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that the present invention can be similarly applied to a case where the number of carriers is three or more.

[0025]

As described above, according to the present invention,
Since the clock signal of the data signal of the carrier with good line quality and no equipment failure is always used as the reference clock (timing signal) for the phase matching circuit, the line or equipment of the reference carrier is damaged. Even if the error occurs, the clock signal of the data of another carrier in which no trouble has occurred in the line and the device can be automatically switched and used as a reference clock, so that the other carrier is not affected at all times. With a simple circuit configuration,
The data phases between the carriers can be surely matched.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of an example of a conventional line switching device.

[Description of Signs] 1 First working system signal input terminal 2 Second working system signal input terminal 3 First protection system signal input terminal 4 Second protection system signal input terminal 5-8 Frame synchronization circuit 9,10 Synchronization switching circuit 11, 12 Phase matching circuit 13 Timing generation circuit 16 Parallel / serial conversion circuit 17 Output terminal 18 Clock selection circuit 19, 20 Signal processing circuit

Claims (2)

(57) [Claims] 1. A plurality of frame synchronization circuits each receiving a plurality of data signals of different carriers and separately performing frame synchronization; and monitoring the transmission line for quality deterioration and equipment failure for each of the plurality of data signals. A plurality of detection means for outputting an alarm signal when the quality deterioration or equipment failure is detected; and a clock signal of a data signal of a carrier detected by the detection means which does not output the alarm signal among the plurality of detection means. A clock selection circuit for selecting from output data signals of the synchronization circuit; and phase matching means for matching the phases of the plurality of data signals respectively output from the plurality of frame synchronization circuits based on the output clock signal of the clock selection circuit. A line switching device comprising: 2. The data signals of the plurality of carriers are signals transmitted on a working line and a protection line, respectively. The plurality of frame synchronization circuits are provided in pairs for each carrier, and the data signals of the working line are The data signal of the protection channel is separately frame-synchronized with the data signal of the protection channel, and the data signal of the working channel and the data signal of the protection channel, which is taken out of the pair of frame synchronization circuits, has no line failure. 2. The line switching device according to claim 1, further comprising a plurality of synchronous switching circuits for selecting the clock signal and outputting the selected clock signal to the clock selection circuit and the phase matching means.