JPH0535931B2 - - Google Patents
Info
- Publication number
- JPH0535931B2 JPH0535931B2 JP60234041A JP23404185A JPH0535931B2 JP H0535931 B2 JPH0535931 B2 JP H0535931B2 JP 60234041 A JP60234041 A JP 60234041A JP 23404185 A JP23404185 A JP 23404185A JP H0535931 B2 JPH0535931 B2 JP H0535931B2
- Authority
- JP
- Japan
- Prior art keywords
- wireless system
- control signals
- board
- intermediate relay
- parity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 claims description 24
- 238000003780 insertion Methods 0.000 claims description 15
- 230000037431 insertion Effects 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 15
- 238000012937 correction Methods 0.000 claims description 10
- 238000012544 monitoring process Methods 0.000 claims description 9
- 238000004891 communication Methods 0.000 claims description 8
- 238000012545 processing Methods 0.000 description 10
- 101000786631 Homo sapiens Protein SYS1 homolog Proteins 0.000 description 7
- 102100025575 Protein SYS1 homolog Human genes 0.000 description 7
- 230000001360 synchronised effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は遅延補正方式に関し、特にデイジタル
無線通信回線において、打合わせ通話信号、監視
制御信号等の制御用信号を主信号にビツト挿入し
て伝送する無線システムと、制御用信号を伝送し
ない他の無線システムとの間の伝送時間差を補正
する遅延補正方式に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a delay correction method, and in particular, in a digital wireless communication line, control signals such as meeting call signals and supervisory control signals are transmitted by inserting bits into the main signal. The present invention relates to a delay correction method for correcting a transmission time difference between a wireless system that transmits control signals and another wireless system that does not transmit control signals.
デイジタル無線通信回線において、打合わせ通
話信号、監視制御信号等の制御用信号を伝送する
方法には、主信号にFM等の複合変調を行うアナ
ログ方式と、主信号にビツト挿入して伝送するデ
イジタル方式とがある。アナログ方式は構成が簡
単で安価であることから従来広く使われていた
が、周波数帯域有効利用の観点から最近開発され
た多値直交振幅変調方式（例えば16値QAM又は
64値QAMなど）では、主としてデイジタル方式
が用いられる。
In digital wireless communication lines, there are two methods for transmitting control signals such as meeting call signals and supervisory control signals: an analog method that performs complex modulation such as FM on the main signal, and a digital method that inserts bits into the main signal and transmits it. There is. Analog systems have been widely used in the past due to their simple configuration and low cost.
64-value QAM, etc.), a digital method is mainly used.
上述の制御用信号は、通常は予備無線システム
と現用の１無線システムとに並列に伝送され、他
の現用無線システムには制御用信号は伝送されな
い。制御用信号を伝送する無線システムには、各
中間中継局にこの制御用信号を分岐および挿入す
るための分岐挿入盤が設けられる。この分岐挿入
盤を挿入することにより、中継されるデータ信号
には少なくとも数ビツトの時間遅延が発生する。
従つて、制御用信号を伝送する無線システムと、
制御用信号を伝送しない無線システムとでは、中
間中継局の数が多くなると可成りの伝送時間差が
生ずる。デイジタル無線通信回路ではフエーシン
グ等による回線障害を防止するため、無線断の同
期切替が採用されることが多い。この場合、制御
信号を伝送する予備無線システムと、伝送用信号
を伝送しない現用の無線システムとの間で大きな
伝送時間差があると同期切替ができなくなるた
め、制御用信号を伝送しない無線システムに補正
用遅延回路を挿入することが行われる。 The above-mentioned control signal is normally transmitted in parallel to the standby radio system and one working radio system, and the control signal is not transmitted to the other working radio system. A wireless system that transmits control signals is provided with a branch/add board for branching and inserting the control signals at each intermediate relay station. By inserting this add/drop board, a time delay of at least several bits occurs in the relayed data signal.
Therefore, a wireless system for transmitting control signals,
In a wireless system that does not transmit control signals, when the number of intermediate relay stations increases, a considerable difference in transmission time occurs. In digital wireless communication circuits, synchronous switching with wireless disconnection is often employed to prevent line failures due to phasing and the like. In this case, if there is a large transmission time difference between the standby wireless system that transmits control signals and the working wireless system that does not transmit transmission signals, synchronized switching will not be possible, so the system will be corrected to a wireless system that does not transmit control signals. This is done by inserting a delay circuit.
しかしながら、上述した従来の遅延補正方式
は、伝送時間差の補正のみを目的とする専用の遅
延回路が必要であるという問題点がある。本発明
の目的は、上述の問題点を除去し、専用の遅延回
路を必要としない遅延補正方式を提供することで
ある。
However, the conventional delay correction method described above has a problem in that it requires a dedicated delay circuit whose purpose is only to correct the transmission time difference. An object of the present invention is to eliminate the above-mentioned problems and provide a delay correction method that does not require a dedicated delay circuit.
本発明の遅延補正方式は、送信端局、中間中継
局、受信端局から構成されるデイジタル無線通信
回線で、打合わせ通話信号、監視制御信号等の制
御用信号を主信号にビツト挿入して伝送する第１
の無線システムと前記制御用信号を伝送しない第
２の無線システムとの伝送時間の差を補正する遅
延補正方式において、前記第１の無線システムの
前記中間中継局に設けられ前記制御用信号の分岐
挿入とパリテイ・チエツク・パルスの監視とを行
う分岐挿入盤の挿入遅延時間と、前記第２の無線
システムの前記中間中継局に設けられパリテイ・
チエツク・パルスの監視を行うパリテイ監視盤の
挿入遅延時間とを等しくなるように構成されてい
る。
The delay correction method of the present invention is a digital wireless communication line consisting of a transmitting terminal station, an intermediate relay station, and a receiving terminal station, and transmits control signals such as meeting call signals and supervisory control signals by inserting bits into the main signal. First thing to do
In the delay correction method for correcting the difference in transmission time between a wireless system and a second wireless system that does not transmit the control signal, the control signal is branched at the intermediate relay station of the first wireless system. an insertion delay time of a drop-and-add board that performs insertion and monitoring of parity check pulses; and a parity check pulse provided at the intermediate relay station of the second wireless system.
The insertion delay time of the parity monitoring board that monitors the check pulse is made equal to the insertion delay time.
次に、本発明の実施例を図面を参照して説明す
る。
Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の回線構成を示すブ
ロツク図であり、中間中継局が１局の場合につい
て、一伝送方向のみを示してある。第１図におい
て、予備無線システムSP及び現用無線システム
SYS１は制御用信号を主信号にビツト挿入して
伝送する第１の無線システム、現用無線システ
ム、SYS２〜SYSnは制御用信号を伝送しない第
２の無線システムであり、送信端局１０、中間中
継局２０、受信端局３０はそれぞれ下記のように
構成されている。 FIG. 1 is a block diagram showing the line configuration of an embodiment of the present invention, and only one transmission direction is shown in the case where there is one intermediate relay station. In Figure 1, the backup radio system SP and the working radio system
SYS1 is a first wireless system or working wireless system that transmits a control signal by inserting bits into the main signal; SYS2 to SYSn are second wireless systems that do not transmit control signals; The station 20 and the receiving terminal station 30 are each configured as follows.
送信端局１０において、正常時SYS１〜SYSn
で伝送されるデータ入力信号は送信符号処理盤１
１，１２でバイポーラ符号からユニポーラ符号に
変換され、フレーム同期パルス、パリテイ・チエ
ツク・パルスを含む付加ビツトが挿入されたの
ち、各送信装置１３とSPの送信符号処理盤１４
の後に設けられた送信同期切替器１５とに分配さ
れる。SP及びSYS１で伝送される制御用信号１
０１は二分され、その一方はSYS１の送信符号
処理盤１２に、他方は送信同期切替器１５の後に
設けられている信号挿入盤１６に送られ、それぞ
れ主信号にビツト挿入された制御用信号の付加ビ
ツトを置換して信号を挿入するよう構成されてい
る。 At the transmitting terminal station 10, SYS1 to SYSn during normal operation
The data input signal transmitted by the transmission code processing board 1
After the bipolar code is converted into a unipolar code in steps 1 and 12, and additional bits including a frame synchronization pulse and a parity check pulse are inserted, each transmitter 13 and the transmission code processing board 14 of the SP
and a transmission synchronization switch 15 provided after the transmission synchronization switch 15. Control signal 1 transmitted by SP and SYS1
01 is divided into two parts, one of which is sent to the transmission code processing board 12 of SYS1, and the other to the signal insertion board 16 installed after the transmission synchronization switch 15. It is configured to replace the additional bits and insert the signal.
中間中継局２０においては、各無線システムの
うち制御用信号を伝送するSP及びSYS１には、
受信装置２１と送信装置２２との間に制御用信号
の分岐挿入と区間用パリテイ・チエツク・パルス
の監視および訂正とを行う分岐挿入盤２３が挿入
され制御用信号を伝送しないSYS２〜SYSnに
は、区間用パリテイ・チエツク・パルスの監視お
よび訂正のみを行うパリテイ監視盤２４が挿入さ
れている。そして、分岐挿入盤２３及びパリテイ
監視盤２４を挿入したための主信号の伝送時間の
遅れ（挿入遅延時間）は、両者が等しくなるよう
に構成されている。なお、各無線システムの機能
配置および信号ケーブル長、導波管長は、通常各
無線システムの伝送時間がほぼ等しくなるように
設定されている。 In the intermediate relay station 20, among the wireless systems, the SP and SYS1 that transmit control signals are
A drop-and-drop board 23 is inserted between the receiving device 21 and the transmitting device 22 to add and drop control signals, and monitor and correct parity check pulses for sections. , a parity monitoring board 24 is inserted which only monitors and corrects the parity check pulses for the sections. The main signal transmission time delay (insertion delay time) due to insertion of the branch/insertion board 23 and the parity monitoring board 24 is configured to be equal. Note that the functional arrangement, signal cable length, and waveguide length of each wireless system are usually set so that the transmission time of each wireless system is approximately equal.
受信端局３０においては、各受信装置３１で受
信復調された信号うち、SYS１〜SYSnの信号は
受信同期切替器３２を経て受信符号処理盤３３，
３４に、SPの信号は受信分配盤３５を経て受信
符号処理盤３３に加えられ、それぞれ送信符号処
理盤と逆の符号処理が行われる。SPの信号は受
信分配盤３５でSYS１〜SYSnの受信同期切替器
３２に分配され、受信同期切替器３２は送信端局
から現用と予備とに並列に送出された信号間の同
期をとり、フエージングにより発生するフレーム
同期パルス間の位相ずれを合わせたのち、無瞬断
の同期切替が行われるように構成されている。な
お、受信符号処理盤３３では制御用信号の抽出が
行われる。 In the reception terminal station 30, among the signals received and demodulated by each reception device 31, the signals SYS1 to SYSn are sent to the reception code processing board 33, via the reception synchronization switch 32,
34, the SP signal is applied to the reception code processing board 33 via the reception distribution board 35, and is subjected to code processing opposite to that of the transmission code processing board. The SP signal is distributed by the reception distribution board 35 to the reception synchronization switchers 32 of SYS1 to SYSn, and the reception synchronization switch 32 synchronizes the signals sent in parallel from the transmitting terminal station to the working and standby signals. After adjusting the phase shift between frame synchronization pulses that occurs due to aging, synchronization switching is performed without momentary interruption. Note that the received code processing board 33 extracts control signals.
大容量の通信を行なう最近のデイジタル無線通
信回線では、送受信端局間の伝送品質を監視し予
備無線システムへの切替を制御するためのシステ
ム切替用のパリテイ・チエツク・パルスのほか
に、各無線中継区間の伝送品質を監視し不良中継
区間の特定を容易にするための区間用パリテイ・
チエツク・パルスを設定し、各中間中継局でこれ
を検出して監視する方法が用いられる。この目的
のため各中間中継局に挿入されるパリテイ監視盤
２４の挿入遅延時間を、上述したように制御用信
号の分岐挿入とパリテイ監視とを行なう分岐挿入
盤２３の挿入遅延時間と同じに設定しておけば、
第１の無線システムと第２の無線システムとの伝
送時間差をなくすことができる。従つて、受信端
局において、制御用信号を伝送するSPと制御用
信号を伝送しないSYS２〜SYSnとの間に、フエ
ージンによる動的な変動（これは受信同期切替器
で調整できる）を除いては伝送時間差の補正のた
めに専用の遅延回路を設ける必要がない。なお、
送信端局および受信端局の構成は従来と同様であ
る。 In recent digital wireless communication lines that perform large-capacity communications, in addition to the parity check pulse for system switching, which monitors the transmission quality between transmitting and receiving end stations and controls switching to a standby wireless system, each wireless Parity/parity for sections to monitor the transmission quality of relay sections and easily identify defective relay sections.
A method is used in which a check pulse is set and detected and monitored at each intermediate relay station. For this purpose, the insertion delay time of the parity monitoring board 24 inserted into each intermediate relay station is set to be the same as the insertion delay time of the drop-and-drop board 23 that performs drop-and-drop of control signals and parity monitoring as described above. If you do that,
The transmission time difference between the first wireless system and the second wireless system can be eliminated. Therefore, at the receiving terminal station, there is no difference between the SP that transmits control signals and SYS2 to SYSn that do not transmit control signals, except for dynamic fluctuations due to phasing (which can be adjusted with the reception synchronization switch). There is no need to provide a dedicated delay circuit to correct the transmission time difference. In addition,
The configurations of the transmitting terminal station and the receiving terminal station are the same as in the prior art.
以上詳細に説明したように、本発明の遅延補正
方式によれば、各中間中継局で制御用信号を伝送
する無線システムに挿入される分岐挿入盤と、制
御用信号を伝送しない無線システムに挿入される
パリテイ監視盤の挿入遅延時間が同一となるよう
に構成されているので、中間中継局の数にかかわ
らず補正を目的とする専用の遅延回路を用いるこ
となく、同期切替を行うデイジタル無線通信回線
を構成できる効果がある。
As explained in detail above, according to the delay correction method of the present invention, a branch/addition board inserted into a wireless system that transmits control signals at each intermediate relay station and a wireless system that does not transmit control signals can be used. Since the insertion delay time of the parity monitoring board is configured to be the same, regardless of the number of intermediate relay stations, digital wireless communication that performs synchronous switching without using a dedicated delay circuit for correction purpose. This has the effect of configuring the line.
第１図は本発明の一実施例の回線構成を示すブ
ロツク図である。
１０……送信端局、１１，１２，１４……送信
符号処理盤、１３，２２……送信装置、１５……
送信同期切替器、１６……信号挿入盤、２０……
中間中継局、２１，３１……受信装置、２３……
分岐挿入盤、２４……パリテイ監視盤、３０……
受信端局、３２……受信同期切替器、３３，３４
……受信符号処理盤、３５……受信分配盤。
FIG. 1 is a block diagram showing the line configuration of one embodiment of the present invention. 10... Transmission terminal station, 11, 12, 14... Transmission code processing board, 13, 22... Transmission device, 15...
Transmission synchronization switch, 16...Signal insertion board, 20...
Intermediate relay station, 21, 31... Receiving device, 23...
Branch/insertion board, 24... Parity monitoring board, 30...
Receiving terminal station, 32...Receiving synchronization switch, 33, 34
...Reception code processing board, 35...Reception distribution board.
Claims (1)
れるデイジタル無線通信回線で、打合わせ通話信
号、監視制御信号等の制御用信号を主信号にビツ
ト挿入して伝送する第１の無線システムと前記制
御用信号を伝送しない第２の無線システムとの伝
送時間の差を補正する遅延補正方式において、前
記第１の無線システムの前記中間中継局に設けら
れ前記制御用信号の分岐挿入とパリテイ・チエツ
ク・パルスの監視とを行う分岐挿入盤の挿入遅延
時間と、前記第２の無線システムの前記中間中継
局に設けられパリテイ・チエツク・パルスの監視
を行うパリテイ監視盤の挿入遅延時間とを等しく
設定したことを特徴とする遅延補正方式。1. A first wireless system that transmits control signals such as meeting call signals and supervisory control signals by inserting bits into the main signal, using a digital wireless communication line consisting of a transmitting terminal station, an intermediate relay station, and a receiving terminal station. In the delay correction method for correcting the difference in transmission time with the second wireless system that does not transmit the control signal, the intermediate relay station of the first wireless system is provided with a method for adding and dropping the control signal and parity control. The insertion delay time of a branch/additional board that monitors check pulses is made equal to the insertion delay time of a parity monitoring board that monitors parity check pulses provided at the intermediate relay station of the second wireless system. A delay correction method characterized by setting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60234041A JPS6294032A (en) | 1985-10-18 | 1985-10-18 | Delay correction system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60234041A JPS6294032A (en) | 1985-10-18 | 1985-10-18 | Delay correction system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6294032A JPS6294032A (en) | 1987-04-30 |
| JPH0535931B2 true JPH0535931B2 (en) | 1993-05-27 |
Family
ID=16964640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60234041A Granted JPS6294032A (en) | 1985-10-18 | 1985-10-18 | Delay correction system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6294032A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2605399B2 (en) * | 1989-06-28 | 1997-04-30 | 日本電気株式会社 | Auxiliary signal transmission circuit |
| JP2712680B2 (en) * | 1989-12-29 | 1998-02-16 | 日本電気株式会社 | Code error detection method |
-
1985
- 1985-10-18 JP JP60234041A patent/JPS6294032A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6294032A (en) | 1987-04-30 |
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