JPH1155239A - Synchronization detecting and releasing circuit with protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronization detecting and releasing circuit with a protection circuit in which synchronization detection and release can be prevented from being repeated even when a detection pattern code error is generated, and whose protection circuit for synchronization detection and release can be constituted of a simple circuit. SOLUTION: In put data 11 and a clock 12 are clock 12 are inputted to a pattern detecting circuit 1, and specific pattern is detected from the input data 11, so that a pulse signal 14 for one clock, a reference pulse 13, and the clock 12 are inputted to a protection circuit 3, and then the value of the pulse signal 14 is held for each position of the reference clock 13. When an output signal 15 for outputting the continuous detection of '1' is outputted from the protection circuit 3 to a synchronization detecting and releasing circuit 4, a synchronization signal 17 indicating a synchronization detecting state is outputted from the synchronization detecting and releasing circuit 4. Also, when an output signal 16 for outputting the continuos detection of '0' is outputted from the protection circuit 3 to the synchronization detecting and releasing circuit 4, the synchronization signal 17 indicating the synchronization release is outputted from the synchronization detecting and releasing circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization detecting / releasing circuit with a protection circuit in a data communication receiving apparatus, in which a protection circuit which can be constituted by a simple circuit is added to a synchronization signal generator.

[0002]

2. Description of the Related Art A conventional synchronous detection / release circuit will be described with reference to FIG. FIG. 4 is a block diagram showing a configuration of a conventional synchronization detection / release circuit. In FIG. 4, serial input data 11 and a clock 12 are input to the pattern detection circuit 1, and when the clock 12 is input, the pattern of the input data 11 is detected, and the pulse signal 14 is synchronously detected and released. Output to the circuit 5.

A reference pulse 13 from the timing generation circuit 2 is also input to the synchronization detection / release circuit 5. The reference pulse 13 is periodically generated at the same generation timing as the generation position of the pulse signal 14 generated by detecting the pattern by the pattern detection circuit 1. The synchronization detection / release circuit 5 receives the pulse signal 14 output from the pattern detection circuit 1 and the reference pulse 13 output from the timing generation circuit 2 and
A synchronization signal 17 is generated.

Next, a detailed configuration of the conventional synchronization detecting / releasing circuit of FIG. 4 will be described with reference to a block diagram of FIG.
FIG. 5 shows the internal configuration of a portion other than the timing generation circuit 2, and the same portions as those in FIG. 4 are denoted by the same reference numerals. The pattern detection circuit 1 includes a shift register 1A and a gate 1B. The serial input data 11 and the clock 12 are input to the shift register 1A, and the input data 11 is shifted every time the clock 12 is input, converted into 4-bit parallel data, and output from the output terminals Q0 to Q3. The signal is output to the gate 1B (4-input AND gate).

A pulse signal 14 is sent from the output terminal of the gate 1B to the synchronization detecting / releasing circuit 5. The synchronization detecting / releasing circuit 5 includes a gate 5A and a flip-flop 5B. First input terminal of gate 5A (negative input terminal)
Receives a pulse signal 14, and the pulse signal 14
Is also input to the set input terminal of the flip-flop 5B. When the pulse signal 14 is input to the set input terminal of the flip-flop 5B, the flip-flop 5B is set, and the synchronization signal 17 is output from the output terminal Q.

Although not shown in FIG. 5, a reference pulse 13 output from the timing generation circuit 2 is input to the second input terminal of the gate 5A, and the gate 5A receives the reference pulse at the time when the pulse signal 14 is not generated. When 13 is input, the output is sent to the reset input terminal of the flip-flop 5B to reset the flip-flop 5B. That is, the flip-flop 5B is set or reset in accordance with the value of the pulse signal 14 at the timing of the reference pulse 13.

Next, the operation of the conventional synchronization detecting / releasing circuit will be described with reference to FIG. 5 and a timing chart of FIG. The pattern detection circuit 1 in FIG. 5 is an example in which the serial input data 11 performs synchronization detection in a pattern of “1111”. Input data 11 as shown in FIG. 6A is input to the input terminal D of the shift register 1A of the pattern detection circuit 1, and a clock 12 as shown in FIG. 6B is supplied to the clock input terminal of the shift register 1A. CK
Is input to The clock 12 is supplied to the shift register 1A.
Is input, the serial input data 11 is shifted by the shift register 1A, converted into 4-bit parallel data, and output ends Q0 to Q of the shift register 1A.
3 to the gate 1B.

The gate 1B receives the output of the shift register 1A, performs an AND logic operation on the output of the shift register 1A,
When the output of "1111" is "1111", a specific pattern of the input data 11 is detected and "1" is output as a pulse signal 14, that is, the first input terminal of the gate 5A of the synchronous detection / release circuit 5 and the flip-flop. 5B to the set input terminal. "1" is applied to the set input terminal of the flip-flop 5B.
Is input, the flip-flop 5B is set, and the synchronizing signal 17 is output as shown in FIG.

When the reference pulse 13 is inputted to the second input terminal of the gate 5A at the time when the pulse signal 14 is not inputted to the first input terminal of the gate 5A, the gate 5A takes an AND logic of the two signals. By outputting the output to the reset input terminal of the flip-flop 5B, the flip-flop 5B is reset, and as shown in FIG.
7 is not output.

[0010]

In such a conventional synchronization detecting / releasing circuit, when a code error occurs in a pattern to be detected in the input data 11, there is a problem that the synchronization releasing / detection is repeated. There is a problem that a circuit for realizing the protection function is complicated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and a protection circuit for detecting and canceling synchronization when a pattern match / mismatch is continuously detected is constituted by a simple circuit. It can be added to the synchronization detection / release circuit, and even if a code error occurs in the detection pattern,
An object of the present invention is to provide a synchronization detection / release circuit with a protection circuit that can prevent repetition of synchronization release and detection.

[0012]

In order to achieve this object, a synchronization detecting / releasing circuit with a protection circuit according to the present invention receives an input data 11 and a clock 12 and inputs a specific pattern from the received input data 11. A pattern detection circuit 1 for detecting and outputting a pulse signal 14 for one clock;
A timing generation circuit 2 for periodically generating a reference pulse 13 at the same position as the pulse signal 14, a pulse signal 14 of the pattern detection circuit 1, a reference pulse 13 and a clock 12 of the timing generation circuit 2, and a reference pulse The value of the pulse signal 14 is held for each of the 13 positions, and "1"
A protection circuit 3 that outputs an output signal 15 that outputs a continuous detection of “0” and an output signal 16 that outputs a continuous detection of “0”;
A synchronizing signal 17 to which the output signals 15 and 16 of the protection circuit 3 are input, which is detected by the output signal 15 and released by the output signal 16
And a synchronization detection / cancellation circuit 4 for generating

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a synchronization detecting / releasing circuit with a protection circuit according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In FIG. 1, the same parts as those in the conventional example shown in FIGS. 4 and 5 are denoted by the same reference numerals to avoid repeated description, and the parts different from the conventional example in FIGS. 4 and 5 will be mainly described.

The pattern generation circuit 1, timing generation circuit 2, and synchronization detection / cancellation circuit 4 of FIG. 1 are the same as those of the conventional example shown in FIG. 1, and in the first embodiment, the conventional example shown in FIG. The protection circuit 3 is newly added to the configuration of FIG. The protection circuit 3 includes a pulse signal 14 from the pattern generation circuit 1 and a reference pulse 1 from the timing generation circuit 2.
3 and a clock 12 are input.

The protection circuit 3 holds a pulse signal 14 for each position where the reference pulse 13 is generated, and sends an output signal 15 for outputting a continuous detection of "1" to the synchronization detection / cancellation circuit 4 as a detection signal. The output signal 16 that outputs the continuous detection of “0” is sent to the synchronization detection / cancellation circuit 4 as a cancellation signal. The synchronization detection / cancellation circuit 4 receives the output signal 15 and receives the synchronization signal 1 of “1” indicating the synchronization detection state.
7 is output, and an output signal 16 is input, thereby outputting a synchronization signal 17 of “0” indicating a synchronization release state.

Next, a detailed configuration of the first embodiment will be described with reference to FIG. FIG. 2 is a block diagram showing a detailed configuration of the first embodiment. 2, in the description of the configuration, the same parts as those in the conventional example shown in FIG. 5 are denoted by the same reference numerals, and parts different from FIG. 5 will be mainly described. Since the pattern detection circuit 1 of FIG. 2 has the same configuration as the pattern detection circuit 1 of FIG. 5, the description of the configuration of the pattern detection circuit 1 will be omitted.

The protection circuit 3 comprises a shift register 3A and gates 3B and 3C.
A pulse signal 14 output from the gate 1B of the pattern detection circuit 1 is input to an input terminal D of A, and a reference pulse 13 from the timing generation circuit 2 (not shown in FIG. 2) is input to an input terminal EN. , And shift register 3
The clock 12 is input to the clock input terminal CK of A.

An output signal 31 is output from an output terminal Q0 of the shift register 3A, and an output signal 32 is output from an output terminal Q1. These output signals 31 and 32 are respectively connected to a gate 3B as a first gate and a second gate. It is sent to the gate 3C as a gate. The gate 3B uses an AND gate, and the gate 3C uses a NOR gate.

The output signal 15 is sent from the output terminal of the gate 3B to the set input terminal S of the flip-flop 4A of the synchronization detection / release circuit 4, and the output signal 16 is output from the output terminal of the gate 3C.
To the reset input terminal R of the flip-flop 4A. The synchronization signal 17 is output from the output terminal Q of the flip-flop 4A.
Is output.

Next, the operation of the first embodiment of the present invention configured as described above will be described with reference to the block diagram of FIG. 2 and the timing chart of FIG. The first embodiment shown in FIG. 2 shows a case where the serial input data input to the data communication receiving device performs synchronization detection in a pattern of “1111”. In other words, this is an example in which the number of times of pattern matching / mismatch at the position where the reference pulse 13 is generated is two consecutive times.

The operation of the pattern detection circuit 1 and the timing generation circuit 2 of FIG. 2 is the same as that of FIG. 4, and the input data 11 as shown in FIG. Is input to FIG.
A clock 12 as shown in FIG. 2B is input to a clock input terminal CK of the shift register 1A.

When the clock 12 is input to the shift register 1A, the serial input data 11 is shifted by the shift register 1A, converted into 4-bit parallel data, and output from the output terminals Q0 to Q3 of the shift register 1A to the gate 1B. Is output to The gate 1B inputs the output of the shift register 1A, performs an AND logic, detects a specific pattern of the input data 11 when the output of the shift register 1A is "1111", and outputs "1" as an output signal, that is, FIG. As the pulse signal 14 shown in FIG.
To the input terminal D of the shift register 3A.

In the protection circuit 3, the reference pulse 13 from the timing generation circuit 2 (see FIG. 1) shown in FIG. 3C is input to the input terminal EN of the shift register 3A.
The clock input terminal CK of this shift register 3A is
The clock 12 shown in FIG. When the reference pulse 13 is “1” and the clock 1
2 is input, the pulse signal 14 is shifted and the value of the pulse signal 14 is held, and the output signal 3 shown in FIG.
1 and an output signal 32 shown in FIG. 3 (f) and output to the gates 3B and 3C, respectively.

The gate 3B inputs a total of 2 bits, ie, the “1” bit of the output signal 31 and the “1” bit of the output signal 32, and the output signals 31 and 32 are both “1”, that is, “1”.
In the case of "1", the AND logic is taken and the output signal 15 indicating the continuous detection of "1" is applied to the set input terminal S of the flip-flop 4A of the synchronous detection / release circuit 4 as shown in FIG. Send out.

When the output signal 15 is input to the set input terminal S of the flip-flop 4A, the flip-flop 4A is set, and the synchronizing signal 17 of "1" is output as shown in FIG. Indicates the synchronization detection state.
That is, when the pattern detection pulse exists in the input data 11 twice consecutively at the position of the reference pulse 13, the output signal 15 is output from the gate 3B and the flip-flop 4
A is set, and the synchronization signal output from the flip-flop 4A indicates a synchronization detection state.

The gate 3C receives the output signal 31 and the output signal 32, and inputs a total of 2 bits of the "1" bit of the output signal 31 and the "1" bit of the output signal 32. If both are “0”, that is, “00”, the NOR logic is taken to output the output signal 16 indicating the continuous detection of “0” as shown in FIG. 4A to the reset input terminal R.

The reset input terminal R of the flip-flop 4A
When the output signal 16 is input to the flip-flop 4A
Is reset, and the output signal 17 becomes "0", indicating a synchronization release state. That is, if there is no pattern detection pulse in the input data 11 twice consecutively at the position of the reference pulse 13, the output signal 16 is output from the gate 3C,
The flip-flop 4A is reset, and the synchronization signal output from the flip-flop 4A indicates a synchronization detection state.

[0028]

According to the synchronization detecting / releasing circuit with a protection circuit of the present invention, input data and a clock are input to a pattern detection circuit, a specific pattern is detected from the input data, and a pulse signal for one clock is generated. , A reference pulse and a clock are input to a protection circuit, and a protection circuit having a simple circuit configuration for detecting and canceling synchronization when a match / mismatch of input data patterns is continuously detected is added to the conventional configuration.
Even if a code error occurs in the detection pattern,
The problem of repeating synchronization detection can be solved with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a first embodiment of a synchronization detection / release circuit with a protection circuit according to the present invention;

FIG. 2 is a block diagram showing a detailed configuration of a synchronization detection / release circuit with a protection circuit of FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the synchronization detection / release circuit with the protection circuit of FIG. 2;

FIG. 4 is a block diagram showing a schematic configuration of a conventional synchronization detection / release circuit.

FIG. 5 is a block diagram showing a detailed configuration of a synchronization detection / release circuit of FIG. 4;

FIG. 6 is a timing chart for explaining the operation of the synchronization detection / release circuit of FIG. 5;

[Explanation of symbols]

 1 Pattern detection circuit 1A. 3A shift register 1B, 3B, 3C gate 2 timing generation circuit 3 protection circuit 4 synchronization detection / cancellation circuit 4A flip-flop

Claims (4)

[Claims] 1. A pattern detection circuit which receives input data (11) and a clock (12), detects a specific pattern from received input data (11), and outputs a pulse signal (14) for one clock. (1) and the reference pulse (13) at the same position as the pulse signal (14)
, A pulse signal (14) of the pattern detection circuit (1), a reference pulse (13) and a clock (1) of the timing generation circuit (2).
2) as input, and pulse signal (1) for each position of reference pulse (13)
Output signal (15) that holds the value of 4) and indicates continuous detection of "1"
And a protection circuit (3) that outputs an output signal (16) indicating continuous detection of “0”. The output signals (15) and (16) of the protection circuit (3) are input, and an output signal (15 ), And a synchronization detection / release circuit (4) for generating a synchronization signal (17) to be released by an output signal (16). 2. A synchronous detection circuit with a protection circuit according to claim 1.
In the cancellation circuit, the pattern detection circuit (1) includes: a shift register (1A) that shifts serial input data (11) for each input of a clock (12) and converts the data into 4-bit parallel data; When the 4-bit parallel data output from (1A) is “1111”, the pulse signal (14)
A synchronization detection / cancellation circuit with a protection circuit, comprising a gate (1B) for outputting a signal. 3. A synchronous detection circuit with a protection circuit according to claim 1.
In the release circuit, the protection circuit (3) receives the clock (12), and receives a reference pulse (13) output from the timing generation circuit (2) at "1", and the pattern detection circuit (1). Shift register (3) that shifts the pulse signal (14)
A), an output signal (31) and an output signal (32) of the shift register (3A).
A first gate (3B) that outputs an output signal (15) of “1” when both are “1”; an output signal (31) and an output signal (32) of the shift register (3A)
A synchronization detection / cancellation circuit with a protection circuit, comprising a first gate (3C) that outputs an output signal (16) of “1” when both are “0”. 4. A synchronous detection circuit with a protection circuit according to claim 1.
In the release circuit, the synchronization detection / release circuit (4) is set by an output signal (15) output from the protection circuit (3), and is set by an output signal (16) output from the protection circuit (3). A synchronization detection / release circuit with a protection circuit, comprising a flip-flop (4A) to be reset.