JPH01137728A - Circuit device for serial/parallel conversion - Google Patents

Abstract

PURPOSE:To obtain an S/P conversion circuit device whose circuit constitution can be simplified at the time of designing it by providing a control ROM with a synchronism detecting function and a control function. CONSTITUTION:A serial signal 1 consists of an idle signal, a synchronizing signal and a data signal, the idle signal is inputted to the control ROM 51, a counter signal 4 shows '0' and a synchronism detecting signal 6 clears the contents of a synchronizing counter 3 at the time of detecting no synchronism. Then, the synchronizing signal is inputted to the ROM 51, the signal 6 is turned to a synchronism detecting state by increasing the signal 4, the contents of the counter 3 are not cleared, and said state is held until the end of synchronism detection. At the time of ending the synchronism detection by the ROM 51, the input timing of the data signal is set up and a parallel data detecting clock signal 7 is outputted to a terminal CK of a D-FF 19 in a parallel conversion circuit 8. The FF 19 outputs a semi-parallel signal 20 as a parallel signal 9 based on the signal 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit device for converting serial serial signals into parallel parallel signals, and particularly to serial signals including synchronization signals, data signals, and idle signals, as well as serial signals. The present invention relates to a serial/parallel conversion circuit device that inputs clocks of serial signals sampling data signals, converts the data signals into parallel signals, and outputs the parallel signals.

[Prior Art J] A serial transmission system for data transmission requires a circuit that synchronizes at the receiving end and converts a gj-serial serial signal into a parallel signal. Circuits that convert serial signals into parallel signals are commonly used. The serial signals include, for example, an idle signal 13, a synchronization signal 14, and a data signal 15, as shown in FIG.
It is a serial signal containing .

Conventionally, this type of serial/parallel conversion circuit device, as shown in FIG. It was converted to signal 9.

In FIG. 5, when the idle signal 13 of the serial signal 1 is input to the synchronization detection circuit IO, the counter clear signal 11 outputted by the synchronization detection circuit IO is output from the OR circuit because the synchronization signal 14 is not detected. The synchronization counter 3 is cleared via 12. On the other hand, the synchronization counter 3 notifies the control glue-only memory (hereinafter referred to as ROM) 5 that the end of synchronization has been detected using a counter signal 4.

Next, when the synchronization signal 14 of the serial signal 1 is supplied,
Synchronization detection N path 1O indicates the synchronization detection state.Cw.

The rear signal 11 is output, and the synchronization counter 3 operates without being cleared. and data signal 1 of serial signal 1
5 is supplied, the control ROM 5 outputs the clock 7 for parallel data detection via the count signal 4. Thus, the parallel conversion circuit 8 converts the data signal 15 into a parallel signal 9 and outputs the parallel signal 9.

The operation shown in FIG. 5 will be explained below with reference to FIGS. 6 to 10.

As shown in FIG. 6, the synchronization detection circuit IO is constituted by a synchronization signal setting circuit 16 consisting of, for example, a NOT circuit 10a and a buffer circuit 10b, and a selector 17, and creates the same pattern as the synchronization signal 14. Note that FIG. 6 shows the synchronization signal setting circuit 16 when the synchronization signal 14 is r 0100OOOIJ. The selector 17 inputs the counter signal 4 to the terminal SEL and outputs the value shown in the counter signal 4 as a counter clear signal 11, thereby detecting whether or not the synchronization signal 14 of the serial signal 1 has been received.

FIG. 8 shows a pattern when the synchronization signal 14 of the serial pronunciation code 1 is input to the synchronization detection circuit IO, that is, when synchronization is detected. The output of the counter clear signal 11 is normally incremented by the counter signal 4 being sequentially incremented from 0 to an integer n (n is the number of bits of the synchronization signal 14, and in the case of FIG. 6, n=8). This means that the synchronization signal 14 has been detected, and at that time t, the synchronization detection signal 6 changes from the synchronization undetected state to the synchronization detected state. Then, the synchronization detection signal 6 enters a state in which the operations of the synchronization counter 3 and the synchronization detection circuit 10 are stopped, and the synchronization detection ends.

FIG. 9 shows a pattern when the idle signal 13 or the data signal 14, which is a signal other than the synchronization signal 14 of the serial signal 1, is input to the synchronization detection circuit 10, that is, when the synchronization is detected in which it is not determined as the synchronization signal 14. It shows. At this time, the counter clear signal 11 indicates that the counter signal 4 is n.
Before the synchronization occurs, tl, t2. By entering the state of t3 and returning to "0", the state in which it is not judged as the synchronization signal 14 continues, and the state in which the synchronization counter 3 is cleared midway continues. However, when the synchronization detection signal 6 is in a state in which the synchronization counter 3 and the synchronization detection circuit 10 are in a state where the operations are stopped, the operation described in FIG. 9 is not performed.

Next, the operations of the synchronization counter 3 and the control ROM 5 will be explained. FIG. 10 shows the patterns of the counter signal 4, synchronization detection signal 6, and clock 7 for detecting parallel data when detecting the synchronization signal 14 and creating the parallel signal 9.

The synchronization counter 3 sequentially increments the value of the counter signal 4 using the serial signal clock 2 when the synchronization signal 14 is detected, and when the synchronization signal 14 is not detected, the synchronization detection signal 6 and the counter clear signal 11 increment the value of the counter signal 4. An operation is performed to return the value of to rOJ.

The control ROM 5 operates as follows based on the counter value that is the output of the synchronization counter 3. First, if the value of the counter signal 4 is "0" to "n", that is, when the synchronization signal 14 is detected, it is determined that the synchronization signal 14 has not been detected yet, and the selector 17 of the synchronization detection circuit IO An operation is performed to detect the synchronization signal 14. At this time, the parallel data detection clock 7 is not output.

Then, when the counter signal 4 exceeds rnJ, that is, when the parallel signal 9 is created, the clock 7 for parallel data detection is transmitted at intervals of m (the integer m is the number of bits of the parallel signal 9), as shown in FIG. (Parallel signal 9 for integer
(number of data) is output.

The synchronization detection signal 6 at this time is set to always indicate the synchronization detection state, and the counter clear signal 11 causes the OR circuit 1
2 prevents the synchronization counter 3 from being cleared. After outputting the second signal to the parallel data detection clock 7, that is, after completing the creation of the parallel signal 9, the synchronization detection signal 6 is set to a state in which synchronization detection is performed again on the value of the counter signal 4. For time detection, clear the synchronization counter 3 and set the value of the counter signal 4 to "0".
Return to

Next, according to the operation of the parallel conversion circuit 8 as shown in FIG. 7, the shift register 18 is
is converted into a quasi-parallel signal 20 by. This quasi-parallel signal 20 does not distinguish between LSB (the least significant bit of the parallel signal 9) and MSB (the most significant bit of the parallel signal 9), and is simply a signal divided into m pieces. In order to convert this quasi-parallel signal 20 into a parallel signal 9 with the LSB and MSB aligned, the parallel signal 9 is created by the D-type flip-flop 19 at the timing of the parallel data detection clock 7 and sent to the outside.

[Problem that the invention seeks to solve]

In the conventional serial/parallel conversion circuit device described above, the synchronization detection circuit IO operates only when the idle signal I3 of the serial signal 1 and the synchronization signal 14 are input, and stops its function in the case of the data signal 15. ing.

Further, the parallel data detection clock 7, which is the output of the control ROM 5, is connected to the idle signal 13 and the synchronization signal 1.
In the case of 4, the operation is stopped, and it operates only when the data signal 15 of the serial signal 1 is input.

In this way, the synchronization detection circuit lO and the control ROM 5
When one circuit is operating, the other is not operating, resulting in a part of the circuit's operation being wasted.

The object of the present invention is to provide a synchronization detection circuit 10 and a control RO
It is an object of the present invention to provide a serial/parallel conversion circuit device which has a simplified configuration and structure by combining both functions of M5 into a control ROM 5.

Means for Solving Problem L] The circuit device of the present invention inputs a serial signal consisting of an idle signal, a synchronization signal, and a data signal, and inputs a clock for sampling the serial signal.
In a circuit device that outputs converted parallel signals,
a synchronization counter that inputs the clock of the serial signal and sends out a counter signal that is the counted value; and a synchronization counter that inputs the counter signal and the serial signal as an address signal to detect a synchronization signal, and outputs the synchronization detection signal. A control ROM that sends out a clock for parallel data detection as well as to the synchronization counter, and inputs the serial signal, the clock of the serial signal, and the clock for parallel data detection, and converts the converted data. A parallel conversion circuit that sends out parallel signals,
It is characterized by having the following.

[For production]

Therefore, according to the present invention, since the control ROM has a synchronization detection function and a control function, the circuit can be simplified at the time of circuit design, and the failure rate during operation is reduced, resulting in improved reliability. It will improve.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention;
The figure is a time chart showing the operations of the control ROM 51 and synchronization counter 3 shown in FIG. 1, and FIG. 4 is a flowchart showing the operation of the control ROM 51 shown in FIG.

First, as shown in FIG.
The clock 2 of the serial signal is input to the OM51 and the shift register 18 of the parallel conversion circuit 8, and the clock 2 of the serial signal is input to the synchronization counter 3 and the shift register 1 of the parallel conversion circuit 8.
It is connected so as to be input to the clock terminal CK of No. 8. The synchronization counter 3 inputs the serial signal clock 2 to the clock terminal CK, inputs the synchronization detection signal 6 to the clear terminal CLR, and outputs the counter signal 4 to the control RO.
It is connected to output to M51.

The control ROM 51 receives the serial signal 1 and the counter signal 4, outputs the synchronization detection signal 6 to the synchronization counter 3, and outputs the clock 7 for parallel data detection to the D-type flip-flop 19 of the parallel conversion circuit 8.
The clock terminal GK is connected to output the clock terminal GK of the clock terminal GK.

The shift register 18 is connected to a D-type flip-flop 19 so as to output a quasi-parallel signal 20, and the D-type flip-flop 19 outputs a parallel signal 9.

Next, the operation of the serial/parallel conversion circuit device shown in FIG. 1 will be explained with reference to FIGS. 2 to 4.

This embodiment will be explained in the case where the serial signal 1 is an idle signal 13 that is a repetition of "0011", a synchronization signal 14 that is 8 bits of "old 0000 old", and a data signal 15 that is 8 bits and 510 bytes. .

Therefore, as shown in FIG. 1, the quasi-parallel signal 20, which is the output of the shift register 18 of the parallel conversion circuit 8, and the parallel signal 9, which is the output from the D-type flip-flop 19, are respectively 20-1 to 20-8. Consisting of 8 pieces,
In addition, it has an eight-piece configuration from 9-1 to 9-8.

Then, 12 counter signals 4 are output from the synchronization counter 3, and the values of the counter signal 4 from rOJ to "7" are used when receiving the synchronization signal 14, and the values from "8" to r40 are used when receiving the synchronization signal 14.
87J (8-bit data signal 15 has 510 bytes, so if it is converted to serial signal 1, 8 x 510
= 4080 (required) is used when processing the data signal 15, and the remaining values r4088J~:,;;nor up to r4095J (maximum value that can be expressed by counter signal 4) are used when waiting for reception of the synchronization signal 14. In other words, it is used to return the value of counter signal 4 to rOJ.

Serial signal 1 is input to control ROM 51, serial signal clock 2 is input to synchronization counter 3, and the operation of control ROM 51 and synchronization counter 3 determines whether the content of serial signal l is synchronization signal 14 or not. Detection is performed to determine whether or not.

As shown in FIGS. 3 and 4, the idle signal 13 of rollJ is stored in the control ROM 5 as the serial signal 1.
1, the value of the counter signal 4 indicates "0" and the synchronization detection signal 6 is set to be in a state where synchronization has not been detected, so that the synchronization counter 3 is cleared (step 5TI).

Next, when the synchronization signal 14 of r0100OOOIJ is input to the control ROM 51, step S in FIG.
As shown in T2 to STM, the value of counter signal 4 is "0" to "
7" and assuming that the value of the counter signal 4 indicates the position of each bit of the synchronization signal 14, the synchronization detection signal 6 is in a state of synchronization detection so that the synchronization counter 3 is not cleared. (Step STM)
. Then, when the value of the counter signal 4 is "7", it means that the synchronization detection is completed, and the synchronization detection signal 6 continues to be in the state of synchronization detection and the synchronization counter 3 is not cleared.

When the control ROM 51 compares the 8th bit "7" of the synchronization signal 14 and completes synchronization detection, the timing when the data signal 15 is input is reached, and the signal of the clock 7 for parallel data detection is D type flip-flop 19
Meanwhile, the value of the counter signal 4 is sequentially incremented by "8" or more. Note that the signal of the parallel data detection clock 7 is as follows.
As in the conventional case, as shown in FIG. 1O, the signals are output at intervals of m.

The parallel conversion circuit 8 is similar to the conventional one, and the shift register 1
8 is serial signal 1 and serial signal clock 2
20-1 to 2 which is the quasi-parallel signal 20.
0 to 8 are output to the D-type flip-flop 19, and the D-type flip-flop 19 outputs the quasi-parallel signal 20 as a parallel signal 9 from 9-1 to 9-8 using the parallel data detection clock 7.

Then, when the data signal 15 ends, the idle signal 15 returns again.
When the synchronization detection signal 6 is inputted, the synchronization detection signal 6 is set to the synchronization undetected state again, and the synchronization counter 3 is cleared to enter the state of waiting for synchronization detection.

[Effects of the Invention] As explained above, the present invention provides the control ROM with both the synchronization detection function and the control function, so that the configuration and structure can be simplified, and the circuit can be simplified when designing the circuit. In addition, since the failure rate during operation can be reduced, reliability is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a signal diagram explaining the same as the above, Figure 3 is a time chart without showing the operation of Figure 1, Figure 4 is a flow chart without showing the operation of Figure 1, Figure 5 is a block diagram without showing the conventional example, FIG. 6 is a block diagram showing the configuration of the synchronization detection circuit in FIG.
7 is a block diagram of the synchronizing signal setting circuit of FIG. 5, and FIG. 81.
¥1. 9 is a time chart of the synchronization detection circuit of FIG. 5, and FIG. 1O is a time chart explaining the operation of FIG. 5. 1... Serial signal, 2... Serial signal clock, 3...
. . . Synchronization counter, 4 --- Counter signal, 51 . . . Control ROM. 6...... Synchronization detection signal, 7...... Parallel data detection clock,
8...Parallel conversion circuit, 9...
...Parallel signal, 13...Idle signal, 14...
...Synchronization signal, 15...Data signal, 18...Shift register, 19...
...D type flip-flop, 20...
...Semi-parallel signal.

Claims (1)

[Scope of Claims] 1) A circuit device that inputs a serial signal consisting of an idle signal, a synchronization signal, and a data signal, and also inputs a clock for sampling the serial signal and outputs a converted parallel signal, comprising: a synchronization counter that inputs a serial signal clock and sends out a counter signal that is the count value; a synchronization counter that inputs the counter signal and the serial signal as an address signal to detect a synchronization signal; A control ROM that sends out a clock for detecting parallel data as well as a synchronization counter; and a control ROM that inputs the serial signal, the clock of the serial signal, and the clock for detecting parallel data, A serial/parallel conversion circuit that transmits signals.
Parallel conversion circuit device. 2) Claim 1, wherein the parallel conversion circuit is a shift register and a D-type flip-flop.
The circuit device described in Section.