JPS619057A - Zero inserting circuit - Google Patents

Abstract

PURPOSE:To obtain a zero insertion circuit with simple circuit constitution by outputting a pulse signal from a serial input parallel shift register and utilizing the said pulse signal when the same high level of >=consecutive 5 bits is inputted. CONSTITUTION:A parallel data signal (a) is outputted as a serial data signal (c) from a parallel input serial output converting element 1, then same consecutive high level of >=5 bits is outputted as the signal (c), and when a control signal (h) enabling zero insertion is at a possible level, a pulse signal is outputted from an output data representing a level 5 clocks before among parallel data from the serial input parallel shift register 3. The shift operation of the converting element 1 is stopped by one clock's share by using the signal and the said signal is fed to a counter circuit 2 via an inverter 13 at the same time, the counting is stopped by one clock's share to retard a signal (d) as a load signal by a time inserted with zero. Further, an output signal of the inverter 13 is fed to a gate circuit 11 together with the signal (c) and zero is inserted to the signal (c) by bringing the output to a zero level.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a zero insertion port that performs signal processing of zero insertion when transmitting a parallel data signal as a serial transmission data signal in a method compliant with HDLC transmission procedures. It is something.

Conventional configuration and its problems When data stored in the memory of a microcomputer, etc. is transmitted as a serial data signal in accordance with the HDLC transmission procedure, the flag and data part can be recognized on the receiving side without error. like.

When 5 or more bits are at the same high level continuously except for flags, it is necessary to insert a zero that does not exist in the data signal into the next 1 bit.

Conventionally, zero insertion is performed as a software process, and when there is data with the same high level for 5 or more consecutive bits, the process of inserting zeros that do not exist in the data is performed using a calculation process such as a microcomputer, and the data is transmitted as a serial data signal. A method is being taken. Normally, microcomputers also process other programs in parallel. For this reason, it is desirable that the time occupied by the microcomputer for a program to be processed in parallel is as short as possible, but programs that perform the above-mentioned processing inevitably have the problem of increasing the occupied time and slowing down the program processing speed.

Next, a conventional example of hardware processing will be explained using Fig. 1.6 Fig. 1 shows how parallel data signals are
This is a circuit diagram of a conventional zero insertion circuit that performs hardware processing. (1) is a parallel input serial output conversion element.

The transmitted parallel data signal (a) is shifted every time it receives a clock signal (b) and is converted into a serial data signal (C).
Convert to (2) is a counter circuit with a clock signal (
Every time b) is counted a certain number (8 times in this case), a pulse signal (d) is generated, and is used as a load signal to the parallel input serial output conversion element (1), and is used as a D (described later) to control whether or not to insert zero. Each is supplied as a clock signal to the flip-flop (6).

(3) is a serial input parallel shift register which inputs the serial data signal (c) from the parallel input serial output conversion element (1), shifts the input every time it receives the clock signal (b), and converts the parallel data (e-processing) into parallel data. ) to (e5) and supplied to the gate circuit (4). (5) is a flip-flop at J-, which inputs the output (f) of the gate circuit (4), and the output (g) is used as a clear signal to the series input parallel shift register (3), and also to the gate circuit (7). as an input signal. (6) is a D flip-flop that controls whether or not to insert zero, and uses the pulse signal (d), which is the output signal of the counter circuit (2), as a clock signal, and outputs the load signal to the parallel input serial output conversion element (1). At the same time as the timing, a control signal (h) indicating whether or not to insert a zero is latched as an input signal, and is sent to J- along with the output (g) of the flip-flop (5) as a signal (i) indicating whether or not to insert a zero. ). The gate circuit (7)
The output signal (j) of the parallel input serial output conversion element (1)
The signal is supplied to the inverter (8) as a clock input signal, to the counter circuit (2) as an enable signal, and to the gate circuit (9) as a zero level input signal. At the same time, it is input to the gate circuit (9) together with the serial data signal (C) from the parallel input serial output conversion element (1) to obtain a serial transmission data signal (k).

Pulse signal (d) which is the output signal of the counter circuit (2)
is output to the outside, and at the same time, the parallel data signal (a) is transmitted to the parallel input serial output conversion element (1) and output as a serial data signal (, ). When the serial data signal (c) is at the same high level for 5 or more consecutive bits, the parallel data (el) to (
e,), all outputs from the latest clock to the output of 5 clocks ago are high level, and the output (f) of the gate circuit (4) is output as a high level signal. The flip-flop (5) at J- inputs the output (f) which is the high level signal, receives the clock signal (b), and outputs a pulse signal as an output (g). When the control signal (h) indicating whether or not to insert zero is at a level that allows, the output (g) which is the pulse signal and the signal (i) from the D flip-flop (6) which controls whether or not to insert zero are input. The gate circuit (7) outputs an output signal (j) which is a pulse signal. This output signal (j) is supplied to the parallel input/serial output conversion element (1) via the inverter (8) to stop the shift operation by one clock, and at the same time, the output signal (j) is sent to the counter circuit (2). is supplied to stop the counting operation for one clock, delay the pulse signal (d) as a load signal by the time to insert zero, and simultaneously supply it to the gate circuit (9) together with the serial data signal (c). inserts a non-existent zero into the parallel data signal (,) by setting its output to zero level. When the control signal (h) indicating whether zero insertion is possible is a negative level signal, the output signal (j) of the gate circuit (7) is not output as a pulse signal, and zero insertion is not performed. Through the above operation, the parallel data signal (a) is converted into the serially transmitted data signal (k).
When transmitting the parallel data signal (a), if five or more bits are continuously at the same high level, zeros that do not exist are inserted into the parallel data signal (a).

However, in such a conventional circuit, since the serial data signal (c) is outputted as parallel data (el) to (e,) by the serial input parallel shift register (3), the gate circuit (4) which receives these as input, A flip-flop (5) is connected to J-, which inputs the output of this gate circuit (4), and this J
- A large number of gate-configured circuits are required, such as a gate circuit (7) whose input is the output of the flip-flop (5), and a gate circuit (9) whose input is the output of this gate circuit (7). The problem was that there were a lot of

Purpose of the Invention The present invention solves the above-mentioned drawbacks of the conventional technology, and provides a zero insertion circuit with a simple circuit configuration and low cost.
The purpose is to provide.

Structure of the Invention In order to achieve the above object, the zero insertion circuit of the present invention includes a parallel input serial output conversion element that converts a parallel data signal into a serial data signal every time a clock signal is input, and a parallel input serial output conversion element that counts the clock signal. and a counter circuit that supplies an output signal to the parallel input serial output conversion element as a load signal, and a control signal for indicating whether or not to insert a zero at the same time as the timing of loading to the parallel input serial output conversion element using the output signal of this counter circuit as a clock. a D flip-flop that latches a D flip-flop, and a D flip-flop that shifts and converts the serial data signal from the parallel input serial output conversion element into parallel data every time the clock signal is input;
A serial input parallel shift register that supplies the output data before the clock to the counter circuit, and the latest clock and 6 of the parallel data of this serial input parallel shift register.
a gate circuit which receives the output data before the clock and the output of the D flip-flop and outputs a clear signal to the series input parallel shift register and the star;
(TE) an output gate circuit which receives the output data of 5 clocks earlier of the parallel data of the serial input parallel shift register and the serial data signal from the parallel input serial output conversion element and outputs a serial transmission data signal. The structure is as follows.

That is, in converting a parallel data signal into a serial transmission data signal, the present invention first inputs the parallel data signal to a parallel input serial output conversion element, converts it into a serial data signal, and transmits it by an output gate circuit. When this output is input to a serial input parallel shift register and the same high level is input for 5 bits or more consecutively, a pulse signal is output from the series input parallel shift register, and this pulse signal is sent to the parallel input serial output conversion element. the pulse signal, the shift operation of the parallel input serial output conversion element is stopped for one clock, and at the same time the pulse signal is supplied to the counter circuit, the counting operation is stopped for one clock, and zero is inserted. By delaying the load signal by the same amount and also setting the signal of the output gate circuit to zero, a zero that does not exist in the parallel data signal is inserted and transmitted, and the circuit configuration is different from that of the conventional circuit. can be simplified.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit block diagram of a zero insertion circuit according to an embodiment of the present invention, in which the same components as those shown in FIG. 1 are given the same reference numerals and their explanations will be omitted.

(1) is a parallel input serial output conversion element, (2) is a counter circuit, (3) is a serial input parallel shift register, and (6) is a D flip-flop that controls whether or not to insert zero. This is the same as the conventional example shown.

The serial input parallel shift register (3) receives the serial data signal (Q) from the parallel input serial output conversion element (1) and outputs parallel data. Among the parallel data, output data of the latest clock (flood) and a signal obtained by inverting the output data of six clocks ago (,) by an inverter (12) are supplied to a gate circuit (10). A control signal (h) indicating whether zero insertion is possible is inputted to the D flip-flop (6), and a latched output signal is used as a clock signal to determine whether zero insertion is possible. The output signal (n) of the six gate circuits (10), which is supplied as a signal (i) to the gate circuit (10), is supplied as a clear signal to the series input parallel shift register (3). Of the parallel data, the output data (O) 5 clocks ago is sent to the parallel input serial output conversion element (1) as a clock input signal and also to the counter circuit (2).
) as an enable signal via an inverter (13). At the same time, the output data (0) from 5 clocks ago is supplied to the gate circuit (11) through the inverter (13) together with the serial data signal (c), and the serial transmission data signal (p
).

Next, the operation will be explained. The pulse signal (d), which is the output of the counter circuit (2), is output to the outside, and at the same time, the parallel data signal (,) is transmitted to the parallel input serial output conversion element (1), and is converted into a serial data signal (c). Out'
It is activated. At that time, if the serial data signal (c) is output at the same high level for 5 bits or more, and the zero insertion control signal (h) is at the enable level, the serial input parallel shift register (3) outputs the parallel data. A pulse signal is output from the output data (o) indicating the level 5 clocks earlier. This pulse signal is supplied to the parallel input serial output conversion element (1), and the parallel input serial output conversion element (1)
The shift operation by the clock signal (b) of the clock signal (b) is stopped by one clock, and at the same time, the pulse signal is
3) to the counter circuit (2), the counting operation is stopped for one clock, and the pulse signal (d) as a load signal is delayed by the time for inserting zero.

Moreover, the pulse signal passed through the inverter (13) is as follows.

Furthermore, the gate circuit (11) together with the serial data signal (c)
By supplying the output to zero level,
A zero that does not exist in the parallel data signal (a) is inserted into the serial data signal (C), and the control signal (h) for determining whether or not to insert six zeros, which is output as the serial transmission data signal (p), is a signal with a negative level. time, or serial data “signal” (c) i5”
``・Continuous same number of 0s less than 8''・When transmitting a signal or zero level, the clear signal which is the output signal (n) of the gate circuit (10) is input to the series input parallel shift register (3) and is cleared. , a pulse signal is not output to the output data (0) of the parallel data, which is a zero insertion signal,
Zero insertion is not performed.

With the above operation, when converting the parallel data signal (a) to the serial transmission data signal (p), it is possible to insert zeros that do not exist in the data after 5 or more consecutive bits are at the same high level. can.

FIG. 3 shows signal waveforms at various parts of the circuit shown in FIGS. 1 and 2. In Figure 3, the dashed line portion of parallel data is (
Include only when e, )(e,)(e,)(e,)(a,). Also, the broken line portion of the zero level signal is included only in case (g).

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, parallel data signals are
When transmitting as a serial transmission data signal according to the DLC transmission procedure, when 5 or more bits are continuously at the same high level.

A zero insertion circuit can be realized with a simpler circuit than the conventional circuit. Furthermore, the processing program in the microcomputer or the like on the data sending side becomes easier, and the processing speed can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of a conventional zero insertion circuit. FIG. 2 is a circuit block diagram of a zero insertion circuit according to an embodiment of the present invention, and FIG. 3 is a signal waveform diagram of each part of the circuit shown in FIGS. 1 and 2. (1)...Parallel input serial output conversion element, (2)...
Counter circuit, (3)...Series input parallel shift register, (6)...D flip-flop, (10) (1
1)...Gate circuit.

Claims (1)

[Claims] 1. A parallel input serial output conversion element that converts a parallel data signal into a serial data signal every time a clock signal is input;
a counter circuit that counts the clock signal and supplies the output signal to the parallel input serial output conversion element as a load signal; and a counter circuit that uses the output signal of the counter circuit as a clock to simultaneously load the parallel input serial output conversion element with the timing. A D flip-flop that latches a control signal indicating whether or not to insert a zero; and a D flip-flop that shifts the serial data signal from the parallel input serial output conversion element and converts it into parallel data every time the clock signal is input; a serial input parallel shift register that supplies the output data of 5 clocks ago to the counter circuit, the latest clock of the parallel data of this series input parallel shift register, the output data of 6 clocks ago, and the output of the D flip-flop. a gate circuit that outputs a clear signal to the series input parallel shift register upon input of the above data, and output data of the parallel data of the series input parallel shift register 5 clocks ago and serial data from the parallel input serial output conversion element. A zero insertion circuit comprising: a signal; and an output gate circuit that receives a signal and outputs a serially transmitted data signal.