JPS6226743B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a data transfer method including time-division data in a data processing device, etc., and particularly to a data transfer method completely synchronized with a clock used during data transfer. It is something.

(2) Background of the technology In a data transfer method, data is transferred to and stored in a data receiving register that constitutes a predetermined number of ways (transmission paths...way), or the data stored there is further divided into different types. If the system clock used in the data processing device has a relatively long cycle when transferring the data to the destination,
The operations of each component constituting the data processing device closely follow the system clock to ensure proper data transfer. However, if the cycle of the system clock becomes small, that is, if the clock cycle becomes fast, the decoder operation that decodes the address where data is stored will not be able to follow the clock because it takes time to decode the address where data is stored, and the decoder will not be able to follow the clock. Data transfer is also delayed. In particular, as the number of ways increases, it takes more time for the decoder to decode the address, and the deviation from the predetermined way becomes larger.

(3) Conventional technology and problems In other words, problems that occur when data is transferred using the conventional technology for a certain way as shown in FIG. 1 are summarized in the conventional control circuit configuration and timing diagram shown in FIGS. 2 and 3. This is explained by: In addition, the first
In the case of the figure, in order to simplify the explanation, a case will be described in which time-division data is 4-way and a 1-bit register is used. (Normally, one way is 8 bits.) In Fig. 1, of the address information from the central processing unit (not shown), for example, the last 2 bits of address information specify the first specific way. For example, if way 3 is specified, then ways 0, 1, 2, and so on are accessed sequentially. Then, the data of each way is stored in register A of each way.
To store data in B, C, and D, the operation is performed at the rising edge of set clocks CLK ₀ , CLK ₁ , CLK ₂ , and CLK ₃ , respectively. The circuit configuration shown in FIG. 2 is based on the conventional technology that generates the set clock as described above, and the operation and problems of the circuit are explained in the third section.
This will be explained with reference to the timing diagram shown in the figure.

A start signal S initiates data transfer. The signal is applied to a decoder 2 via a delay circuit 1. The inputs A ₀ and A ₁ of the decoder are bits of a start address indicating which way the transferred data comes from; for example, this uses the lower two bits of the address information. Therefore, once the address of a particular way is determined, the value incremented by 1 becomes the address of each way. Here, it is assumed that way "3" is first selected, and then ways 0, 1, and 2 are determined in sequence.

The operation is started by a start signal S sent in synchronization with the system clock CL, and a decoder output appears at the output of the decoder 2 in accordance with the 2-bit addresses A ₀ and A ₁ . In this case, 4
Since it is a way, the decoding output is four, but it is clear that as the number of ways increases, the decoding time also increases. Here, since it is way 3, the outputs Q ₀ , Q ₁ = 1, and Nandogade 4 _-4
It is given to 2 out of 3 inputs.
The rising edge of ACL (A clock) affects the operation of decoder 2, but in any case, only NAND gate _4-4 is conditioned by the signal W resulting from delaying ACL in delay circuit 3, and its output Signal WG=0, and the “0” output is the NOR gate 5
_-4 , the output of NOR gate 5 _-4 becomes "1", which is applied to input D ₃ of register 6. The register 6 is configured so that "1" is output to the corresponding output terminal to which "1" is input. Therefore "1" on the output side to NAND gate 8 _-4
A signal is generated, which is applied to one input of the NAND gate 8 _-4 and to one of the inputs of the AND gate 9 _-4 .
one input and is conditioned along with the other input. Then, during the period when the CYC signal (cycle control signal) is arriving, the NAND gate 8 _-1 ~
8 _-4 is conditioned, but in this case, since only way 3 had an output from the beginning, the condition of only NAND gate 8 _-4 is satisfied, and its output signal *
CK ₃ =0. However, as can be seen from FIG. 2, the output side of the gate _8-4 is connected to one input of the NOR gate _5-1 of way 1, so the output of the NOR gate _5-1 becomes "1" and the register 6 is input
Since it is given to D ₀ , next the output of register 6 CK ₀ =
It becomes "1". Then, the output of NAND gate 8 _-1 in way 1 goes to one input of NOR gate 5 _-2 in way 2.Similarly, the output side of NAND gate 8 _-2 in way 2 goes to one input of NOR gate 5 _-3 in way 3. , so CK ₃ =
“1”, →CK ₀ = “1”, →CK ₁ = “1”, →CK ₂ =
Pulses are sequentially generated such as "1". Finally, each pulse outputted from the register 6 is outputted via the inverter 7 in synchronization with the inverted signal of the clock CL applied to each AND gate _9-1 to _9-4 , as shown in FIG. Na
_CLK3 , _CLK0 to _CLK2 are generated.

However, as can be seen from Fig. 3, when the system clock CL has a long (slow) cycle, the W and WG signals, including the output of decoder 2, follow the rising edge of the A clock and the The operation of each component follows the timing and the operation progresses smoothly, but if the system clock cycle is small or the number of ways increases and the decoding time of the decoder becomes long, As shown in the figure, after the address bits A ₀ and A ₁ arrive, the address is decoded by the decoder 2 and the data is stored, but a shift occurs for each way.
As mentioned above, this problem becomes more noticeable as the way address becomes larger, and affects the system clock cycle.

(4) Purpose of the Invention The present invention solves the above problem by first specifying that data transfer and storage processes are completely synchronized with the system clock while taking decoder operation time into consideration. The object of the present invention is to provide a data transfer method in which all data of a specific way to be processed is stored once in a register, and then other data is sequentially stored.

(5) Structure of the Invention In order to achieve the above object, the data transfer method of the present invention uses a time-sharing method in which an arbitrary address is specified and then data is transferred and stored by changing the address in sequence. In the data transfer method, the first time-sharing data transferred is temporarily stored in multiple registers regardless of their addresses, and then the second and subsequent data are stored first according to their addresses. The clock is completely synchronized by storing the data superimposed on each data in the register.

(6) Embodiments of the invention Next, embodiments of the invention will be described with reference to the accompanying drawings. Note that for the sake of simplicity, a 4-way case will be similarly described.

In FIG. 4, 11 is a delay circuit, 12 is a decoder, 13 _-1 to 13 _-4 are NAND gates, and 14 _-1 to 1
4 _-4 is Noah gate, 15 is D flip-flop
register (hereinafter simply referred to as register),
_16-1 to _16-4 are NAND gates, 17 is a J-K flip-flop, 18 and 19 are inverters, 20
_-1 ~ 20 _-4 is Noah Gate, and 21 _-1 ~ 21 _-4
is an AND gate, and 22 is an inverter. In particular, in the present invention, the first group of NAND gates 13
_-1 to _13-4 are taken from the outputs of the J-K flip-flops, and the outputs of the NAND gates _13-1 to _13-4 are connected to NOR gates _14-1 to _14-4 in ways shifted by one step. It has a connected configuration. Further, in the present invention, the output of the inverter 19 on the output side of the JK flip-flop is connected to the second group of NOR gates 20 _-1 to 20 _-4 .

The circuit of the present invention constructed in this way will be explained using the timing diagram of FIG. Start signal S
The operation starts, and the lower 2 bits of the address
According to A ₀ and A ₁ , the decoder 1 is activated at the rising edge of ACLK (A clock) input via the delay circuit 11.
The decoded output from 2 is its output Q ₀ , ₀ , Q ₁ ,
₁ , each 3-input NAND gate 1
Given to inputs from 3 _-1 to 13 _-4 . Now, for example,
If way 3 is designated as in the case of FIG. 2, the two inputs of the NAND gate 13 _-4 will be "1".
On the other hand, the start signal S is
Since it is applied directly to the input and also applied to its K input via the inverter 18, the flip-flop 17 is set at the falling edge of the clock CLK via the inverter 22 when the clock CLK arrives. Therefore, the "1" signal T is output to the Q output side of the flip-flop 17, and this is applied to the remaining inputs of the NAND gates 13 _-1 to 13 _-4 , so that the output of the NAND gate 13 _-4 where the condition is satisfied is only becomes "0" and all others become "1".
The output of NAND gate 13 _-4 of way 3 is way 1
Since it is connected to the NOR gate 14 _-1 of the register 15, its output becomes "1", which is applied to the D ₀ input of the register 15. Therefore, its output CK ₀ =1, the output of NAND gate 16 _-1 *CK ₀ = 0, the output of NOR gate 14 _-2 becomes "1", and the input CK ₁ of NAND gate 16 _-2 on the output side of the register becomes "1", so its output *CK ₁ = 0. Therefore, the output of NOR gate 14 _-3 is "1", and first, the data of way 3 is converted to CLK ₀ ~ by the "0" output (K) of inverter 19. CLK ₃ all at once “1”
, and stores it in four registers. After that, the output signal of NAND gate 13 _-4 *G ₀₃
By using and giving it to the 0 system, the signal (T)
Since it is always turned on at the third system clock, CK ₀ in FIG. 5 is generated. After that, CK ₁ and CK ₂ are generated by performing a shift operation while taking the conditions with the CYC signal in the same manner as explained in FIG. As shown in Figure 5, the CYC signal becomes
The on-time of CYC is made one pulse shorter than the conventional one so that the number of pulses shown at CLK ₀ , CLK ₁ , and CLK ₂ is limited to only three. Therefore, the fourth pulse _CK3 is suppressed by this CYC, and the output signal IK of the inverter 19 takes its place. Therefore, the IK signal and the four pulses CK ₀ , CK ₁ , and CK ₂ serve as a set clock, and CLK ₀ to CLK ₃ as shown in FIG. 5 are generated. Therefore, each register in which the data of way 3 was stored all at once stores the data of way 0 with the set clock of CLK ₀ , and then sequentially applies the clock again to ways 1 and 2. and store each data. And way 3
Since only the first IK signal clock is required, the value set at that time remains as is, and all 4-way data can be stored.

In this way, prior to decoding the address,
By first writing the same data into all registers and then writing the data into other registers based on the result of decoding, it is possible to quickly write the necessary data into all registers.

(7) Effects of the Invention As mentioned above, in conventional circuits, the length of the decoding time of the decoder affects the system clock. In contrast, in the present invention, the set clock can be generated quickly regardless of the decoding time of the decoder, and is therefore not affected by the period (speed) of the system clock. . Therefore, even if the system clock speed is increased, reliable operation is possible, and since a special circuit for synchronizing with the system clock is not required, the circuit configuration is also simplified. Furthermore, even if the period of the system clock changes, the circuit of the present invention can follow the change.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram to which the present invention is applied, FIG. 2 is a circuit realizing a data transfer method according to the prior art, FIG. 3 is a timing diagram explaining the operation of the circuit in FIG. 2, and FIG. 5 is a timing diagram illustrating the operation of FIG. 4. FIG. 5 is a timing diagram illustrating the operation of FIG. (in the figure), 11 is a delay circuit, 12 is a decoder,
13, 16 are NAND gates, 14, 20 are Noah gates, 17 are J-K flip-flops, 18, 1
9 represents an inverter, 21 represents an AND gate, and 22 represents an inverter.

Claims (1)

[Claims] 1 In a time-sharing data transfer method in which data is transferred and stored by specifying an arbitrary address and then changing the address regularly, the first time-sharing data transferred is transferred to multiple addresses regardless of the address. The clocks are completely synchronized by temporarily storing the data in the first register, and then storing the second and subsequent data in a superimposed manner on each data stored in the first register according to their addresses. A data transfer method characterized by: