JPS58169387A - Data transferring system - Google Patents

Abstract

PURPOSE:To completely execute clock synchronization, by storing the first transferred time division data in a register and superposing and storing the second and subsequent data in a store data in accordance with an address. CONSTITUTION:First of all, a data of a designated way 3 is stored in 4 registers A-D by setting clocks CLK0-CLK3 to ''1'' simultaneously by a ''0'' output of an invertor. Subsequently, the registers A-D store a data of a way ''0'' by a set clock of the clock CLK0, as to the way ''0'', and after that, as to ways 1, 2, too, they give the clock again successively and store each data. As a result, only a way 3 ends by only a lock by the first IK signal, therefore, a value set in that case is left as it is, and data of 4 ways are also stired. In this way, a necessary data can be entered quickly into all the registers.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a data transfer method including time-division data in a data processing device, particularly a data transfer method completely synchronized with a clock used during data transfer. Technical Background In data transfer methods, a predetermined number of ways (transmission lines...
・It is used in the data processing device when data is transferred and stored in the data receiving side register configuring the ``way'', or when the data stored in the other side is further transferred to another destination. When the cycle of the system clock is relatively long, the operating line of each component constituting the data processing device closely follows the system clock and proper data transfer is performed.゛However,
When the system clock cycle becomes small, that is, when the mosquito clock cycle becomes fast, the decoder operation that decodes the address where data is stored becomes unable to follow the clock because it takes time to decode it9, leading to the target way. 4. In particular, as the number of ways increases, the decoder's address solution RK takes more time, and the deviation from the predetermined way becomes larger. I end up.

(萄) Conventional technology and problems In other words, the problems that occur during data transfer using the conventional technology regarding a certain way as shown in Figure 1 are explained in 2vA.
This will be explained with reference to the conventional control circuit configuration and timing diagram shown in FIGS. In addition, in the case of Fig. 1, to simplify the explanation, time-sharing data is 4-way and 1B per bit of register is used! I will clarify. (Normally, one query is 8 bits, 0) In Figure 1, among the address information from the central unit (not shown), the last 2 bits of address information specify the first specific way. , If you specify the way turtle in the RKS hook, then the company way 0 = ie! They are accessed sequentially. Then, in order to store (memorize) the data of each way in the registers tBtC and DK of each way, it takes 7 storages (memory) for each way.
The circuit configuration of om*WIJ, which operates at the rise of -CLK, @ -CLK@, is based on the conventional technology that uses the set clock t** as described above, and the operation of the wrinkle circuit and the problem t-th. This will be explained with reference to the timing diagram shown in FIG.

A start signal S indicates the transfer of data. The mosquito signal is applied to the decoder 2 via the delay circuit It. Decoder input Am - AI Fi This is a start address bit indicating from which way the transferred data comes, and this uses the lower two bits of the address information. Therefore, once the address of a particular way is determined, the value incremented by the address + 1 becomes the address of each way. Here, the younger sister first selects way "3", then ways 0, 1, and so on. -2 are determined sequentially.

The operation is started by the start signal 8 sent in synchronization with the system clock CL.
The decoded output appears at the output of the decoder 2 as a result of Em *a, tcL. In this case, since there are 4 ways, the decode output is 4, but as the number of ways increases,
It is clear that the decoding time will also be long. ◎Here, the line and way are 3, so the output Q@ -Q*-19,
It will be given to 2 out of 3 people at Nantes Gate 410. The rising edge of MU CL (A clock) affects the operation of the decoder 2, but in any case, the signal W resulting from delaying MU CL in the delay circuit 3 causes the Nante gate 4 to
Only -1 is conditioned, its output signal WG = 0, and the output of the skeleton "0" is given to the input of the NOR gate 5-, so the output of the NOR gate 5-4 becomes "1", which is the register 60 inputs are applied. Register 6 is “1”
'' is input and ``1'' is output to the output terminal corresponding to 9. Therefore, an rlJ redundancy signal is generated on the output side to the Nant gate 8°4, which is the 1 of the Nant gate 8-1.
0 which is applied to one input of the AND gate 9-4 and conditioned along with the other input.
Then, during the period when the CYC signal (cycle control signal) is arriving, the four Nantes gates 8-3 to 8-4 are conditioned, but in this case, the Nomori way 3 which has been output from the beginning
Therefore, the condition of only the Nant gate 8-4 is satisfied, and its output signal becomes CHI=O. and ζroga, 2nd Ia
As can be seen from the figure, the output of the scissors game) L is connected to one input of the Noah gate 5-1 of the side line way 1, so the output of the Noah gate 5-1 is rlJ, and the input of the 9 register 6 is given by X. Then, the output CK of register 6, =rl
It becomes J. And, Nantes Gate 8-1 in Makuway l.
The output of is connected to one input of the Noah gate 5-1 of way 2.Similarly, the output side of the Nant gate 8-3 of way 2 is connected to way 3.
CK and mirlJ are connected to one input of the Noah gate 5-1, and so on.

→CK, = “1”, →CK, = rlJ, ~CK, =
Pulses are sequentially generated as rlJ. Finally, each pulse outputted from the register 6 is outputted via an inverter 7 in synchronization with an inverted signal of the clock CL given to each AND gate 9-0 to 9-4, as shown in FIG. Na CL Ka e CL K @〜CL
lh is generated.

However, as can be seen from Figure 3, the system clock CL
When the timing is slow (slow), the output t of decoder 2 follows the rising edge of the A clock, and the W signal, WG
The decoding is generated with proper timing and the operation progresses smoothly by following the motion of each component element. ) If the time becomes long, as shown in Figure #13, the address is decoded by decoder 2 after the address bit A@-As comes and the data is stored, but there will be a shift for each way.And this As mentioned above, the larger the way address, the more pronounced the impact on the system clock cycle.

(4) Purpose of the original WA#i Based on the above-mentioned problem, this was decided.
In order to ensure that the storage Jlaffl is completely synchronized with the system, all data of a specified way is first stored in a register, and then other data is stored in sequence. is intended to provide.

(5) Structure of the Invention In order to achieve the above object, the data transfer method of the present invention specifies an arbitrary address, and then changes the address regularly and sequentially to transfer and store data. In the divisional data transfer method, the first time-sharing data transferred is temporarily stored in a plurality of registers regardless of their addresses, and then the second and subsequent data are first stored according to their addresses. The clock is completely synchronized by storing the data superimposed on each data in the register.

(Actual example of 1hij1) Next, an actual example of the present invention will be explained with reference to the attached drawings.
I will clarify.

In 114WA, 11 delay circuit, 12Fi decoder, IL, ~13-4 is Nando day), 14-t~14-
4-wire NOR gate, 1saD7 lipfp register (hereinafter simply referred to as register), 16-s to 1-
16a Nant gate, 17tiJIm flip 7p tube, 18.19Fi inverter, 20-3 to 20-4 line Noah gate, and 21. ~2l-aFi and gate,
In the present invention, the control inputs of 13- and 13-1 of the first group of companies are connected to the 22Fi inverter o*.
- is taken from the output of the flip 7Q knob, and the output of the Nandday) IL, ~13-4 is shifted by one stage at the friend way's Noah gate 14. It has a configuration that is *continued from ~1i. Further, in the present invention, the output of the inverter 19 on the output side of the J- clip 70 is connected to the second group of NOR gates 20-1 to 20-.

The circuit of the present invention constructed in this manner will be explained using the tie construction i11 shown in FIG. The operation is started by the start signal S, and in response to the lower 8 bits of the address Aeem, the mu CLK input via the delay circuit 11 (A
At the start-up of the decoder 12, the decoded output is generated at its output Q@-Q@-Q*, q&, and each is given to the human power of the 3-manpower Nandogoo) ILI~13-4. I/II! As in the case of the figure, the way s
If you specify t and set it to 9, the two-man power of Nantes Gate 13-4 is ``
1”. On the other hand, the start signal S is 71
7, and the inverter 1g1-
Since it is also given to its input via
When LK arrives, the signal #7 is set via the inverter 22 at its fall. therefore,
The rlJ signal is applied to the Q output side of the 7-lip 70-tube 17, and is applied to the input of the remaining p of the Nant gate IL, -13-4, so that only the output of Nand's IL4, where the condition is met, is 9 becomes "0", and all others become "1". Nando day of way 3) 1 B-, output line of way 1 Noah day) 14. , K is connected, so its output is "1"9, which is the register 1s
paste, given to the input. Therefore, its output is 0, ±
1, the output of p11 and gate 16-1 is CK, -0 is Noah day) 14-, the output is "1", the output side of the register is NAND day) 1 g-, input CK is r
Since it is IJ, its output brush CK, = O. Therefore, the output of Noah gate 14- is "1", and first, query 4 BOf-/l(n A-/19(D r O
J, output (K) causes CLic*~CLK, f- all at once “
By using the output signal band Gsa of 114 and feeding it to the O system, the third
Since the system clock of Homame turns ') on, C in Figure 5
K is generated. After that, CK, , CKse are generated by performing a shift operation while maintaining the conditions for the CYC signal in the same manner as explained in FIG.

CYC signal signal 1st 5th After storing all the data, CLKI. CLK,.

CYC so that the pulses shown on CLKI remain only three.
The on-time of p is also made shorter by one pulse than the conventional one. Therefore, the p4th pulse CKmH is suppressed by this CYC, and the output signal IK of the inverter 19 is replaced by the IK signal and C Km *
Four pulses of C L * C Km serve as a set clock, and C L K * ~ CLKs as shown in Fig. 5 is generated.
Therefore, even though the data of way 3 is stored all at once, each register is
After storing the data of way O by 7 data of L K *, ways 1, 2, . Give the clock again and store each data for 0 and way 3
Since only the clock is clocked by the first IN signal, the value set at that time remains as is, and 4
All way data can be stored.

In this way, before decoding an address, the same data is first written in all registers, and then data is written in other registers according to the decoding result, resulting in the necessary data being written in all registers quickly. be able to.

(7) Effects of the Invention As mentioned above, in conventional circuits, the length of the decoding time of the decoder affects the system clock. In contrast, in the present invention, the set clock can be generated quickly regardless of the decoding time of the decoder, and is therefore not affected by the cycle (speed) of the system clock. As a result, reliable operation is possible even when the system clock is connected, and the circuit configuration is simplified because a special circuit to synchronize with the system clock is not required. Even if there is a change in the system clock cycle, the circuit of the present invention can follow the change.

[Brief explanation of drawings]

The first IQ is a principle diagram to which the present invention is applied, and the second diagram is a circuit #I3 that realizes a data transfer method according to the prior art.
Figure 2 explains the operation of the circuit shown in Figure 4.
Figure 5: Circuit for data transfer method t*m by Takaaki Hiromoto
This is a tie zeta diagram explaining the operation of Figure 4. (In the diagram) 11 delay circuits, 12 Hiro data, 18. 16U Nant gate, 14.20 wire Noah gate, 17 company J-, 7 lip flops, 18 its, 2゛ sister inverter, 21111 and gate, 22 company inverter are shown respectively.

Claims (1)

[Claims] In the time-sharing data transfer method, in which data is transferred and stored by specifying an arbitrary address and then changing the regular KJI next address, the first time-sharing data transferred is transferred to multiple addresses regardless of those addresses. It is characterized in that the clocks are completely synchronized by temporarily storing the data in a register, and then storing the second and subsequent data in a superimposed manner on each data stored in the register first according to their addresses. Data transfer method.