JPH0837522A - Simplex device - Google Patents

Abstract

PURPOSE:To normally store data without being affected by a phase difference by receiving each clock signal from the side of a duplex device and changing a switching control signal in synchronism with a clock at the switching destination of a system. CONSTITUTION:The output of a switching control signal 3 is commonly inputted to F/F 151 and 152, the F/F 151 normalizes that output with the clock received from a system '0' and the F/F 152 normalizes it with the clock received from a system '1'. Therefore, their Q outputs can be provided as waveforms 7 and 7'. Those waveforms 7 and 7' are respectively applied as one input signal of AND gates 154 and 155 and the other input signals are respectively the output signal of an inverter 153 and the switching control signal 3. Therefore, when the switching control signal 3 is at an L level, the output of the AND gate 154 is validized and when it is at an H level, the output of the AND gate 155 is validized so that output signals 8 and 8' can be obtained. These signals 8 and 8' are applied to an OR gate 156 and a corrected switching control signal 3' is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simplex device, and more particularly to a simplex device for selecting an output signal of a duplexer based on a system selection signal.

As shown in FIG. 6, a duplexer is a device 2 which constitutes two systems of 0 system / 1 system, one of which is in an ACT state (operating state) and the other is in an SBY (standby state). -1, 2-2 (may be collectively referred to by the code "2")
The single device 1 refers to a device that operates only in the ACT state.

The duplexer 1 connected to these duplexers 2-1 and 2-2 needs to accurately switch the output signals of the duplexers 2-1 and 2-2 based on the system selection signal. is there.

[0004]

2. Description of the Related Art FIG. 7 shows a configuration of a conventional example of the simplex device 1 shown in FIG. 6, and the simplex device 1 is connected to the duplexer 2 from which side of 0 system / 1 system. The system selection signal (ACT / ACT /
SBY information) is sent from the 0 system / 1 system to the unification device 1 side.

On the side of the unifying device 1, this system selection signal,
On the basis of the above, the system selection section 11 generates a system selection signal based on the predetermined system selection logic shown in Table 1 and FIG.

[0006]

[Table 1] That is, when the system selection signals from the 0 system and the 1 system match, the system indicated by the system selection signal is selected, and when the system selection signals do not match, the previous value is held.

The relationship between the clock / frame clock / data / system selection signal received from the 0 system and the clock / frame clock / data / system selection signal received from the 1 system is shown in the time chart of FIG. And

Here, as shown in the figure, the 0-system and 1-system clock phases are not exactly the same, but generally have a slight phase difference. This is because the duplexer 2 and the duplexer 1 are usually connected by a cable, but the cable length is different because the cable route is different.

In this way, the system selection unit 11 generates a switching control signal for selecting the received signal from the 0 system / 1 system based on the system selection signal, and the selector (SEL) 1
2 to 14 are commonly given.

Upon receiving the switching control signal, the selectors 12 to 14 select the reception signal from the 0 system / 1 system as shown in FIG. Of these, the selector 12 outputs the selected clock, the selector 13 outputs the selected frame clock, and the selector 14 outputs the selected data.

Here, the data is taken into the elastic store memory ES by the selected clock and frame clock.

A conceptual diagram of the operation of the elastic store memory ES is shown in FIG. 10. For example, the data portion 0 ₀ received from the 0 system shown in FIG. 9 is a write frame clock FW and a write clock CW. The address counter WAC indicates that the data should be written in the address 0 of the elastic store memory ES, and the input data is written in order thereafter.

The elastic store memory E
The S is read from the address 0 sequentially by the read address counter RAC which receives the read frame clock FR and the read clock CR generated in the unifying device 1.

[0014]

Here, the time shown in FIG.
Focusing on the data in the chart, the data "0
₂Is written at address 2 of the elastic store memory ES
After the switching control signal is switched,
"1₂Is the 3rd location of the elastic store memory ES
Written in, and then "1₃Is an elastic store
It has been written to address 4 of memory ES,
The elastic store memory ES to be written
It is written in an address that is different from the dress by one address.
I understand that

This is because in the clock after selection, the elastic store memory E is generated because a thin pulse indicated by a star is generated immediately after the switching control signal is switched.
This is because the write address counter WAC to S has been incremented by +1.

On the other hand, Japanese Patent Application Laid-Open No. 3-280740 can be cited as a conventional example in which the 0-system / 1-system clock is normally switched. In this conventional example, the receiving circuits for the respective systems and the outputs of these receiving circuits are provided. The "NOR gate 4" to which the clock signals "a" and "b" are input, the "F / F5" that latches the asynchronous receiving circuit switching signal "c" using the output signal of this "NOR gate 4" as a clock, and this "F / F5" It is composed of a "switching circuit 3" that selects either the clock signal "a" or "b" by the output signal "d" of the F / F5 ".

However, in the case of this conventional example, in FIG. 2 thereof, the phase difference "t" between the clock "a" and the clock "b" is t = τ / 2 (τ: clock "a"). , And the cycle of the clock “b”), the output of “NOR4” is fixed at the “L” level, so the clock input of the “D flip-flop circuit 5” is not input, and the switching signal “d” Is "L"
There is a defect that the level or “H” level is fixed.

Therefore, an object of the present invention is to generate a switching control signal for controlling a selector based on a predetermined system selection logic by a system selection unit which receives a system selection signal received from the duplexer side and outputs one of the duplexers. In a single device that selects the output signal of the device and applies it to the elastic store memory,
The purpose is to correct the switching control signal in order to continue the normal write operation to the elastic store memory.

[0019]

The problem with the prior art is that
From the system selection signals received from each system / system 1,
Based on the system selection logic (see Table 1), the internal selector 12
In the "system selection unit 11" that generates the switching control signal for switching between ~ 14, the phase difference between the 0-system clock and the 1-system clock is not considered at all.

Therefore, in the unifying device 1 according to the present invention,
A signal that absorbs this phase difference is generated to generate selectors 12-1.
A "system selection correction unit 15" for correcting the output signal from the system selection unit 11 in order to switch 4 is provided as shown in FIG.

In FIG. 1, the system selection correction unit 15 is
The switching control signal output from the conventional system selection unit 11 is used as an input signal, and the received clock from the 0 system and the received clock from the 1 system are taken in to output a corrected signal ', which is output by the selector 12 to. 14 is used as a new switching control signal.

[0022]

The time chart of the present invention is shown in FIG. 2, and as shown in the figure, in the case of this example, the output signal of the system selecting section 11 is synchronized with the clock of the one system which is the switching destination of the system. Then, the clock after being selected by the selectors 12 to 14 becomes a waveform synchronized with the 1-system clock instead of the 0-system clock before switching as shown in FIG. It can be seen that the indicated pulse of * is removed.

In this case, the elastic store memory ES is sequentially written with "0 ₂ " at address ₂ , "1 ₃ " at address ₃ , "1 ₄ " at address 4, and so on. Can be implemented.

[0024]

FIG. 3 shows a circuit embodiment of the unifying device 1 according to the present invention shown in FIG. 1. In this embodiment, in particular, the system selection / correction unit 15 uses the 0-system clock and the 1-system clock. And F / F (D-flip-flops) 151 and 152 for commonly inputting the output signal (switching control signal) of the system selection unit 11 to the data input terminal D.
An inverter 153 for inverting the switching control signal, and F /
AND gate 154 that inputs the output signal of F151 and the output signal of inverter 153, and AND gate 1 that inputs the output signal of F / F152 'and the switching control signal
55 and the output signals of the AND gates 154 and 155,
It is configured with an OR gate 156 which inputs “input and outputs a corrected switching control signal”.

The operation of the system selection correction unit 15 will be described below. In the example of FIG. 2, the case where the 0 system is switched to the 1 system has been described. However, in the opposite case, that is, the 1 system is switched to the 0 system. Since the same phenomenon can occur in each case, each case will be described.

(1) Case 1 (system is switched from 0 system to 1 system)
In the case of different cases) The operation of the system selection correction unit 15 in this case will be described with reference to the time chart of FIG. 4. First, the output of the switching control signal in FIG. 3 is input to the F / Fs 151 and 152 in common. , F / F 151 is normalized by the clock received from the 0 system, and F / F 152 is normalized by the clock received from the 1 system. Therefore, its Q output is obtained as a waveform, '.

Here, these waveforms, 'are given as one input signal to the AND gates 154 and 155, respectively, and the other input signal is respectively to the inverter 153.
Output signal and switching control signal. Therefore, when the switching control signal is at the L level, the output of the AND gate 154 becomes valid, and when the switching control signal is at the H level, the output of the AND gate 155 becomes valid, so that the output signal, 'is obtained.

Next, these output signals, 'are given to the OR gate 156, and as a result of the output, a corrected switching control signal' is obtained.

Here, as is clear from the figure, 0 system ⇒ 1
When the system is switched to the system, the correction switching control signal 'can be switched in synchronization with the rising edge of the clock of the 1st system, so that the pulse shown by the star in FIG. 9 is not generated. The selectors 12 to 14 can be switched.

(2) Case 2 (system is switched from 1 system to 0 system)
In the case of other cases) The operation of the system selection correction unit 15 in this case will be described with reference to the time chart of FIG.

First, the switching control signal is input to the F / Fs 151 and 152, the F / F 151 is normalized by the clock received from the 0 system, and the F / F 152 is normalized by the clock received from the 1st system. Therefore, its output is a waveform, '
Obtained as.

Here, these waveforms, 'are AND gates 154, 1 in the same manner as in the case 1.
Given to 55. Since the output signal of the inverter 153 and the switching control signal are also applied to the AND gates 154 and 155, respectively, the output of the AND gate 154 is valid when the switching control signal is at the L level, and the output of the AND gate 155 when it is at the H level. Is valid, the signal, 'is obtained. Next, these signals, 'are O
The corrected switching control signal 'is input to each of the R gates 156 and the output thereof is corrected.

Here, as is clear from the figure, 1 system ⇒ 0
When the system is switched to the system, the correction switching control signal 'can also be switched in synchronization with the rising edge of the clock of the 0 system, and the pulse shown by the star in FIG. 9 is not generated. It is possible to switch the selectors 12 to 14.

[0034]

As described above, according to the simplex device of the present invention, a switching control signal for controlling the selector is generated based on the system selection signal received from the redundant device side to generate one of the redundant devices. A single device for selecting an output signal of the device and giving it to an elastic store memory is configured to receive each clock signal from the redundant device side and change the switching control signal in synchronism with a clock of a system switching destination. Therefore, even if there is a phase difference between the 0-system and 1-system clocks, the data can be normally stored in the elastic store memory without being affected by the phase difference, and the reliability of the system can be improved. It will be possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing in principle the configuration of a simplex device according to the present invention.

FIG. 2 is a time chart diagram for explaining the operation of the unifying device according to the present invention.

FIG. 3 is a circuit diagram showing an embodiment of a simplex device according to the present invention.

FIG. 4 is a time chart diagram for explaining an operation (case 1) of the embodiment of the simplex device according to the present invention.

FIG. 5 is a time chart diagram for explaining an operation (case 2) of the embodiment of the simplex device according to the present invention.

FIG. 6 is a block diagram showing a connection relationship between a single device and a dual device.

FIG. 7 is a block diagram showing a configuration of a conventional simplex device.

FIG. 8 is a time chart showing the relationship between a system selection signal and a system selection logic.

FIG. 9 is a time chart diagram for explaining the operation of the conventional simplex device.

FIG. 10 is a conceptual configuration diagram of a general elastic store memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Simplex device 2 (2-1, 2-2) Duplex device 11 System selection part 12-14 Selector 15 System selection correction part ES elastic store memory In the figure, the same code | symbol shows the same or corresponding part.

Claims (3)

[Claims] 1. A system selection unit which receives a system selection signal received from the duplexer generates a switching control signal for controlling a selector based on a predetermined system selection logic, and outputs an output signal of any one of the duplexers. In the single device for selecting and providing to the elastic store memory, a system selection correction unit for receiving each clock signal from the duplicating device side and changing the switching control signal in synchronization with the clock of the system switching destination is provided. The unification device characterized by. 2. The duplexer according to claim 1, wherein the output signals of the duplexer are a clock signal, a frame clock, and a data signal. 3. The first and second flip-flops, wherein the system selection correction unit inputs the 0-system clock and the 1-system clock respectively and commonly inputs the switching control signal from the system selection unit, and the switching control. An inverter for inverting a signal, and the first
AND gate for inputting the output signal of the flip-flop and the output signal of the inverter, a second AND gate for inputting the output signal of the second flip-flop and the switching control signal, and both AND gates 3. The simplex device according to claim 1, further comprising an OR gate that inputs a gate output signal and outputs a corrected switching control signal.