JPH10145344A - Bit phase synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To follow up a phase in wide range with respect to the phase fluctuation of an input signal by providing a means for selecting one of plural systems of phase synchronizing means and serial-parallel conversion means, and a means for switching these systems. SOLUTION: Two phase synchronizing circuits consisting of phase judging circuits 101 and 102, control circuits 111 and 112, and a variable delay circuit 120 follow up the phase of a delay clock with respect to the input signal whose phase fluctuates hourly. A synchronizing pattern detecting circuit 13X (X is 1 or 2) detects the synchronizing pattern of a transferring signal, and a serial- parallel conversion circuit 14X divides the frequency of the delay clock outputted from the circuit 120 to generate a slow clock and makes an input signal a parallel signal synchronizing with the slow clock to output. A system selection control circuit 150 outputs a switching signal for switching a nonselected system to a selected system to a system selecting circuit 151 at the time of recognizing that the failure of the phase following up of the selected system is near, from the output signals of the circuits 111 and 112 and the outputs of the circuits 101 and 102.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit phase synchronization circuit, and is particularly suitable for a serial interface of a communication system.

[0002]

2. Description of the Related Art In a communication system, as a method of adjusting a phase difference generated between a transmitted input signal and an input clock, for example, there is a method disclosed in Japanese Patent Application Laid-Open No. 4-293332.

In this method, an input signal is delayed stepwise by a variable delay circuit in which delay elements are cascaded with respect to the input signal, and a phase at which the input signal can be correctly latched based on a clock supplied from a system. The selected input signal is selected from the variable delay circuit. This makes it possible to adjust the phase difference between the clock signal and the clock signal caused by the phase fluctuation of the input signal.

[0004]

However, in the circuit having the above configuration, since the variable delay circuit is formed by cascade connection of delay elements, the phase follow-up range is finite, and the phase fluctuation of the input signal is variable delay. When the allowable delay range of the circuit is exceeded, there is a problem that the phase tracking is broken.

[0005] In addition, there is a type in which a multi-phase input signal (or input clock) different by a predetermined phase is formed by using a circuit other than a variable delay circuit. In such a circuit, a signal of each phase is formed. The portion is composed of a finite number of components, and has the same problem as when the above-described variable delay circuit is applied.

[0006] Accordingly, it has been desired to realize a wide range of phase tracking for the phase fluctuation of the input signal.

[0007]

In order to solve the above-mentioned problems, a bit phase synchronization circuit according to the present invention has the following features. (1) By shifting one of an input signal and an input clock in accordance with a phase difference between them. A plurality of phase synchronizing means for synchronizing the phase of an input signal and an input clock; and (2) generating a low-speed clock by dividing the frequency of an input clock from the corresponding phase synchronizing means. A plurality of serial / parallel conversion means corresponding to each of the plurality of phase synchronization means for converting an input signal into a parallel signal synchronized with the low speed clock; and (3) a plurality of phase synchronization means and serial / parallel conversion means. To output the parallel signal and the low-speed clock, and to determine the position of the input signal and the input clock by the phase synchronization means of the selected system. Synchronization when they close collapse, and having a system switching means for outputting the parallel signals and low-speed clock of other systems.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

(A) Embodiment Hereinafter, an embodiment of a bit phase synchronization circuit according to the present invention will be described in detail with reference to the drawings.

(A-1) Configuration of the Embodiment FIG. 1 is a functional configuration diagram of the embodiment. In FIG. 1, the bit phase synchronization circuit of this embodiment includes a phase determination circuit 101, 102, control circuits 111, 112, a variable delay circuit 120, a synchronization pattern detection circuit 131,
32, serial-parallel conversion circuits 141 and 142,
The system includes a system selection control circuit 150, a system selection circuit 151, and a phase adjustment circuit 152.

Here, the phase determination circuit 101 and the control circuit 1
11, variable delay circuit 120, and synchronous pattern detection circuit 13
1 and a serial / parallel conversion circuit 141, and a system including a phase determination circuit 102, a control circuit 112, a variable delay circuit 120, a synchronization pattern detection circuit 132, and a serial / parallel conversion circuit 142. Is called a second system. Further, in this embodiment, either the first system output signal or the second system output signal is selected by a system selection control circuit 150 described later. Here, a system that outputs a signal selected by the system selection control circuit 150 is called a selection system, and other systems are called non-selection systems.

Hereinafter, the function of each part constituting the bit phase synchronization circuit of this embodiment will be described in detail.

The variable delay circuit 120 has a plurality of delay elements, and reduces the input clock to at least 1 in the entire variable delay circuit.
It is possible to delay by more than the clock cycle, and a delay element whose input clock phase is delayed is selected according to a phase control signal output from the control circuits 111 and 112 to be described later. The signals are output to the corresponding phase determination circuits 101 and 102. Note that 2 selected by the variable delay circuit 120
The two delayed clocks originate from the same clock,
The phases are different but the frequencies are the same.
The two delayed clocks are individually selected by the phase control signals output from the control circuits 111 and 112, respectively.

The phase determination circuit 10x (x is 1 or 2)
Compares the phase of the input signal with the phase of the delayed clock output from the variable delay circuit 120 and outputs a phase difference signal representing the phase difference between the input signal and the delayed clock to the control circuit 11.
x, and synchronizes the input signal with the delay clock output from the variable delay circuit 120, and synchronizes the synchronized signal with the synchronization pattern detection circuit 13x and the serial / parallel conversion circuit 1.
4x.

The control circuits 111 and 112 select the variable delay circuit 120 based on the phase difference signals output from the corresponding phase determination circuits 101 and 102 in order to make the delayed clock follow the phase of the input signal. A delay element to be determined is determined and output to the variable delay circuit 120 as a phase control signal. Specifically, the control circuit 1
Reference numerals 11 and 112 denote phase difference signals output from the phase determination circuits 101 and 102, a system switching signal output from a system selection control circuit 150 described later, and control circuits 111 and 11.
2. Control circuits 112 and 11 of other systems having the same function as
The phase control signal output from 1 is an input signal. When the phase of the input signal is advanced with respect to the phase of the delayed clock, the control circuits 111 and 112 operate the variable delay circuit 1 to make the delayed clock more advanced.
At 20, a phase control signal for selecting a delay element having a shorter delay time is output, and when the phase of the input signal is delayed with respect to the phase of the delay clock, the control circuits 111 and 112 output the phase control signal having a smaller phase. The variable delay circuit 120 has a function of outputting a phase control signal for selecting a delay element having a longer delay time to the variable delay circuit 120 in order to use a delayed clock.

When the system including the control circuits 111 and 112 is a non-selection system, the other control circuits 112 and 111 are controlled by the phase control signals output from the other control circuits 112 and 111 as the selection system. , 111 selects the limit delay element (a state in which there is no delay element that becomes a delayed clock whose phase is advanced or delayed), the control circuit 111 Reference numerals 111 and 112 are delay clocks having a phase difference of one clock or less from the delay clocks selected by the other control circuits 112 and 111 in addition to the above functions for establishing bit phase synchronization. The phase control signal is supplied to the variable delay circuit 12 so as to select a delay clock having a phase other than the phase of the delay clock selected by the circuits 112 and 111.
It also has the function of outputting to 0.

The delayed clocks reselected by the control circuits 111 and 112 are again applied to the phase determination circuits 101 and 10.
2, the phase with the input signal is determined. Therefore, the phase determination circuits 101 and 102 and the control circuits 111 and 112
And the variable delay circuit 120 have a function of causing the phase of the delay clock to follow the input signal whose phase varies with time.

The synchronization pattern detection circuit 13x detects a synchronization pattern inserted in the transfer signal.
Usually, a transfer signal transmitted and received in a communication system has a specific format. Then, in order to establish word synchronization in the receiving device, a specific synchronization pattern is inserted in the transfer signal.

The serial / parallel conversion circuit 14x divides the frequency of the delayed clock output from the variable delay circuit 120,
This is output as a low-speed clock, and based on the pattern detection signal output from the synchronization pattern detection circuit 13x,
The input signal, which is a serial signal, is developed into a parallel signal synchronized with a low-speed clock and output.

The system selection control circuit 150 determines the phase tracking of the selected system from the phase control signals output from the selected control circuits 111 and 112 and the phase difference signals output from the selected phase determining circuits 101 and 102. Is broken (hereinafter, this is referred to as a critical point) (that is, when it is recognized that the phase selection cannot be further followed in the selection system), the synchronization pattern detection circuits 132 and 131 of the non-selection system
Is to output a switching signal to the system selection circuit 151 so as to switch the non-selected system to the selected system when the synchronization pattern is first detected. Note that the critical point does not indicate a state in which bit phase synchronization is broken, but indicates a state in which bit phase synchronization is barely established.

The system selection circuit 151 includes a system selection control circuit 15.
In accordance with the system switching signal output from 0, the phase adjustment circuit 1 converts the parallel signal output from the serial / parallel conversion circuits 141 and 142 of the system indicated by the switching signal and the low-speed clock into one.
52. Since the system switching is performed by the system selection circuit 151, it is sufficiently possible to perform the system switching within the stable time of the data of the parallel signal and the low-speed clock, and critical timing control is not required.

The phase adjustment circuit 152 includes a system selection circuit 151
When the system is switched by the system selection circuit 151, the parallel signal before switching and the parallel signal after switching are output from the system selection circuit 151 when the parallel signal, the low-speed clock, and the system clock are input signals. And converts the parallel signal according to the low-speed clock into a parallel signal according to the system clock, and outputs it as an output signal. Note that the system selection circuit 1
The phase difference of the parallel signal generated when the system is switched by 51 is shorter than one clock cycle of the delayed clock before the frequency division. Therefore, the minute phase fluctuation of the parallel signal caused by the switching can be sufficiently absorbed by the phase adjustment circuit 152. Therefore, a continuous parallel signal synchronized with the system clock is finally obtained.

The function of each part constituting the bit phase synchronization circuit of this embodiment has been described above in detail. In the following, however, the phase determination circuits 101, 1 constituting this embodiment will be described.
02, the variable delay circuit 120, and the system selection circuit 151 are shown in detail. FIG. 2 is a detailed diagram specifically showing the circuit configuration of each of the above circuits in FIG. 1 showing the functional configuration of this embodiment.

Since the functions of the circuits constituting this embodiment have been described above, only the circuit configuration of each of the above circuits and the function of each circuit based on the configured circuit will be described below.

In FIG. 1, the control circuits 111, 1
12 can be realized by applying a so-called up / down counter. Therefore, in FIG. 2, the control circuits 111 and 112 are respectively provided with counter circuits 601 and 602
Expressed as Then, the counter circuits 601, 602
Are the delay elements (201 to 20n) of the variable delay circuit 120
Is output as a phase control signal. Further, a serial / parallel conversion circuit 1 also having a clock frequency dividing function
Reference numeral 41 denotes a serial / parallel conversion circuit 410 and a frequency dividing circuit 411 for dividing the frequency of the clock, which are shown in FIG. The same applies to the serial / parallel conversion circuit 142. Further, the function of the system selection circuit 151 can be realized by an elastic store memory.
Then, the system selection circuit 151 is connected to the elastic storage memory 7.
01.

The variable delay circuit 120 includes delay elements 201 to 20n (n is an integer of 2 or more), which are delay elements, and clock selection circuits 210 and 211. The delay elements 201 to 20n are connected in cascade with respect to the input clock, and delay the input clock step by step with the resolution of the delay time of each element. Each delayed clock output by each element is
Input to clock selection circuits 210 and 211. The clock selection circuits 210 and 211 select clocks corresponding to the address values specified by the counter circuits 601 and 602, respectively, and use the phase determination circuits 101 and 211 as delay clocks.
The data is output to 102.

The phase determining circuit 101 includes a fixed delay circuit 30
1, 302, and DFF circuits 303 to 3 as latch circuits
05 and an exclusive NOR circuit (EXNOR circuit) 30
6, 307 and AND circuits (AND circuits) 308, 30
9. Fixed delay circuits 301 and 302
Is to delay the phase of the input signal stepwise.
Each of the DFF circuits 303 to 305 receives an input signal and a signal output from the fixed delay circuits 301 and 302 as input, latches the input signal with a delayed clock output from the clock selection circuit 210, and uses the input signal as a latch signal. Output. In particular, the latch signal output from the DFF circuit 304 is an output signal of the phase determination circuit 101. The EXNOR circuit 306 calculates the exclusive NOR of the latch signals output from the DFF circuits 303 and 304, inverts the operation result to the AND circuit 308, and inverts the operation result to the AND circuit 309. The EXNOR circuit 307 calculates the exclusive NOR of the latch signals output from the DFF circuits 304 and 305, and inverts the calculation result to the AND circuit 308. , And the AND circuit 309 outputs the operation result as it is.

The AND circuits 308 and 309 are provided by EXNOR.
The logical product of the signals output from the circuits 306 and 307 is calculated, and the calculation result is output as a phase difference signal.

When the outputs of the DFF circuits 303 and 304 are the same and only the output of the DFF circuit 305 is different (the phase of the signal output from the fixed delay circuit 301 is different from the phase of the delayed clock output from the clock selection circuit 210). If the output level of the AND circuit 308 is HIGH, the outputs of the DFF circuits 304 and 305 are the same and only the output of the DFF circuit 303 is different (the phase of the input signal is Selection circuit 21
0), the logical level of the output of the AND circuit 309 is H.
It becomes IGH. When the outputs of the DFF circuits 303 to 305 are all the same (based on the delay clock output from the clock selection circuit 210, the latch circuit DFF circuit 303
305 when the input signal and the signals output from the fixed delay circuits 301 and 302 are correctly latched), the outputs of the AND circuits 308 and 309 both become LOW level.

The phase determination circuit 102 is a fixed delay circuit 31
0, 311 and DFF circuits 312-3 which are latch circuits
14 and an exclusive NOR circuit (EXNOR circuit) 31
5, 316 and AND circuits (AND circuits) 317, 31
8. Note that the functions of each of the above circuits are the same as those of the phase determination circuit 101, and a description thereof will be omitted.

The system selection circuit 151 includes a system selection selector 51.
0, 511. The system selection selector 510 outputs the serial / parallel conversion circuits 410 and 412 according to the system switching signal output from the system selection control circuit 150.
Out of the parallel signals output from the ESC memory 152 to the elastic store memory 152. The system selection selector 511 outputs a low-speed clock (clock synchronized with a parallel signal) output from the frequency dividers 411 and 413 according to a system switching signal output from the system selection control circuit 150.
Is output to the elastic store memory 701.

The elastic store memory 701 writes the parallel signal output from the system selection selector 510 into the memory in synchronization with the low-speed clock output from the system selection selector 511, and synchronizes with the system clock. Is read out and output to an external system.

(A-2) Operation of the Embodiment The operation of the bit phase locked loop circuit of this embodiment having the above configuration will be described below. Note that, in order to describe the operation of each circuit constituting this embodiment in detail, the description will be given here with reference to FIG. 2 described above. The serial / parallel conversion circuit converts the signal into an 8-bit parallel signal.

First, the first system is a selection system, and bit phase synchronization has been established by the first system. An input signal, fixed delay circuits 301 and 302 are input by a delayed clock output from the clock selection circuit 210. The operation in the case where the signal output from the device is securely latched will be described. FIG. 3 shows an input signal, fixed delay circuits 301 and 302, a clock selection circuit 210, a DFF circuit 304, and an AND circuit 30.
8, 309, synchronous pattern detecting circuit 131, frequency dividing circuit 4
11 shows a time chart of the output signal of the serial / parallel conversion circuit 410. This will be described below with reference to FIGS.

The input signal is delayed by a fixed delay circuit 301 by a delay amount PH 1,
The delay is delayed by the delay amount PH2 (= PH × 2).
As shown in the time chart, since the delayed clock output from the clock selection circuit 210 rises within the same bit of the input signal and the signal output from the fixed delay circuits 301 and 302 (for example, in FIG. These signals input to the DFF circuits 303 to 305 are reliably latched by the delay clock. Therefore, the latch signals output from the DFF circuits 303 to 305 all match, and both the phase difference signals output from the AND circuits 308 and 309 are at the LOW level. Therefore,
The counter circuit 601 to which the phase difference signal is input maintains the current phase control signal (that is, the address value of the clock selection circuit 210). Further, the latch signal output from the DDF circuit 304 is synchronized with the delayed clock output from the clock selection circuit 210 (for example, in FIG. 3,
t1), indicating that bit phase synchronization has been established.

The latch signal output from the DFF circuit 304 is input to the synchronous pattern detection circuit 131 and the serial / parallel conversion circuit 410. The synchronization pattern detection circuit 131 detects the synchronization pattern inserted in the latch signal, and when the synchronization pattern is detected, the synchronization pattern detection signal output from the synchronization pattern detection circuit 131 becomes HIGH level. In this operation example, it is assumed that a synchronization pattern is inserted into the # 7 bit (see t2 in FIG. 3). On the other hand, the delayed clock input to the frequency dividing circuit 411 divides the frequency of the clock by 8, and outputs a low-speed clock.

The serial / parallel conversion circuit 410 establishes word synchronization based on the fact that the synchronization pattern detection signal output from the synchronization pattern detection circuit 131 has gone high, and uses the serial signal output from the circuit DFF circuit 304 Bits # 0 to # 7 of a certain latch signal are converted into 8-bit parallel signals according to the low-speed clock output from the frequency dividing circuit 411.

The parallel signal and the low-speed clock output from the serial / parallel conversion circuit 141 and the frequency dividing circuit 411 are input to the elastic store memory 701 via the system selection selectors 510 and 511, respectively.

The elastic store memory 701 writes an 8-bit parallel signal in the memory in synchronization with the low-speed clock, and stores the parallel signal written in the memory in synchronization with the externally input system clock. Read and output this to an external system.

Next, the first system is the selection system, and although the bit phase synchronization has been established by the first system, the phase of the signal output from the fixed delay circuit 301 is output from the clock selection circuit 210. The operation when the clock selection circuit 210 of the variable delay circuit 120 selects an input signal that has not been subjected to delay processing when the phase is advanced from the phase of the delayed clock that has been performed will be described.

FIG. 4 shows an input signal, first system fixed delay circuits 301 and 302, a clock selection circuit 210, a latch circuit 304, AND circuits 308 and 309, and a frequency dividing circuit 41.
1, serial / parallel conversion circuit 410, second system clock selection circuit 211, latch circuit 313, synchronization pattern detection circuit 132, frequency division circuit 413, serial / parallel conversion circuit 412, system selection control circuit 150, system selection selector 510, 9 is a time chart of an output signal of the system selection selector 511. Note that the output signals of the fixed delay circuits 310 and 311 of the second system are fixed delay circuits 301 and
302. This will be described below with reference to FIGS.

The input signal is delayed by a fixed delay circuit 301 by an amount of delay PH1.
The delay is delayed by the delay amount PH2 (PH1 × 2).

In the input signal and the signals output from the fixed delay circuits 301 and 302, the fixed delay circuits 301 and 30
As for the signal output from No. 2, the delayed clock output from the clock selection circuit 210 rises within the same bit. However, with respect to the input signal, the delay clock rises in an undefined region which is a bit boundary of the input signal (see, for example, t3 in FIG. 4). Therefore, DF
F circuits 303 to 305 are input signals, fixed delay circuit 30
When the signals output from the fixed delay circuits 301 and 302 are latched by the delayed clock, the signals output from the fixed delay circuits 301 and 302 can be accurately latched. Can not do it. Here, the DFF circuits 303 to 30
5 among the latch signals output from the DFF circuit 303
It is assumed that only the latch signal output from the other does not match the other signals. In this case, only the phase difference signal output from the AND circuit 309 becomes HIGH level. At this stage,
Although the latch signal output from the fixed delay circuit 301 has only a phase margin of PH3 with respect to the delay clock, the latch signal output from the fixed delay circuit 301 is the first latch signal.
Therefore, the bit phase synchronization is in an established state.

The counter circuit 601, which recognizes that the phase of the input signal has advanced by the phase difference signal, determines if the clock selection circuit 210 has an address value corresponding to the delayed clock whose phase has advanced (that is, if the address value is greater than that). If there is a delay element capable of advancing the phase of the delay clock, the address value is output to the clock selection circuit 210, and the phase of the delay clock output from the clock selection circuit 210 is advanced. However, in this case, since the clock selection circuit 210 of the variable delay circuit 120 selects the input signal that has not been subjected to the delay processing, the counter circuit 601
Cannot output the address value of the clock selection circuit 210 for eliminating the phase difference PH3 between the latch signal and the delay clock.

On the other hand, the second system counter circuit 602 for controlling the clock selection circuit 211
Control signal (clock selection circuit 210)
The variable control circuit 120 recognizes that the input signal to which the delay processing has not been performed (that is, the signal having no delayed clock whose phase is further advanced) is selected from the At the time when the system switching signal output from 150 recognizes that the second system to which it belongs is a non-selection system, based on the phase difference signals output from AND circuits 317 and 318, DFF circuits 312 to An address value corresponding to a delay clock other than the delay clock selected by the counter circuit 601 (for example, a delay clock corresponding to the delay element 204) is selected as a delay clock such that all outputs of 314 can be reliably latched. Output to the circuit 211.

As shown in the time chart, the phase of the delayed clock output from the clock selection circuit 211 is
The phase of the delayed clock output from the clock selection circuit 210 is advanced by about 180 degrees. That is, since the delayed clock output from the clock selection circuit 211 rises within the same bit of the input signal and the signal output from the fixed delay circuits 310 and 311 (see, for example, t4 in FIG. 4), the second system Is in a state where bit phase synchronization has been established.

The system control circuit 150, which recognizes that the first system has reached the critical point, based on the phase control signals output from the counter circuits 601 and 602 and the phase difference signal output from the phase determination circuit 101, At the time when the synchronization pattern is detected by the synchronization pattern detection circuit 132 of the second system (t5 in FIG. 4), the output signal is set to make the first system a non-selection system and the second system a selection system. From HIGH level to L
Switch to the OW level, and set the system switching signal to the system selection selector 5
10, 511 and the counter circuits 601, 602.

System selection selectors 510 and 511 select a parallel signal output from the second system and a low-speed clock according to the system switching signal output from system selection control circuit 150 and output the selected signal to elastic store memory 701. I do.
By this switching, the system selection selectors 510, 511
The phase of the serial signal and the phase of the low-speed clock output from the
(Approximately 1/2 clock cycle).

The elastic store memory 701 absorbs the phase fluctuation (in FIG. 4, the phase fluctuation of PH4) of the parallel signal caused by the switching operation of the system selection selectors 510 and 511, and puts the parallel signal on the system clock. Instead, it is output as an output signal. Note that the above-described phase fluctuation of the parallel signal has a phase difference within one clock cycle of the serial clock, so that the phase difference can be sufficiently absorbed by the elastic store memory 701.

(A-3) Effect of Embodiment The effect of the bit phase locked loop circuit of this embodiment having the above configuration will be described below.

In this embodiment, the first system and the second system follow an input signal by a delay clock having a different phase, and switch to another system immediately before the phase following by one system fails. Even if a variable delay circuit having a plurality of delay elements is used, a wide range of phase tracking can be realized with respect to the phase fluctuation of the input signal.

Further, in this embodiment, the latch signal, which is a serial signal output from the phase determination circuit, is converted into a parallel signal by the serial / parallel conversion circuit. Therefore, when the system is switched in the system selection circuit 151 at the subsequent stage, Occurs only within one clock cycle of the serial clock. Therefore, the phase difference can be easily absorbed by the phase adjustment circuit 152.

Further, the serial / parallel conversion circuit converts a serial signal into a parallel signal when a synchronous pattern is detected. Therefore, since the parallel signal is output from the serial / parallel conversion circuit in a state where the word synchronization is established, there is no need to rearrange the parallel signals in the subsequent stage.

(B) Other Embodiments In this embodiment, a variable delay circuit having a plurality of delay elements is used in order to obtain a multi-phase clock (a delayed clock in the above embodiment) of an input clock. The present invention can also be applied to those to which other multi-phase clock forming methods are applied.

Further, in the embodiment, for the non-selection system,
Regardless of whether the control circuit of the selection system reaches the critical point or not, it has the function of always performing the bit phase synchronization operation, but it is in a standby state until the control circuit of the selection system reaches the critical point, and the control circuit of the selection system May be a function of starting a bit phase synchronization operation at the time point of reaching a critical point.

Further, in the embodiment, in order to simultaneously establish the word synchronization as well as the bit phase synchronization,
Although the synchronization pattern is detected by the synchronization pattern detection circuit, the frame synchronization pattern may be detected by the synchronization pattern detection circuit in order to establish the frame synchronization together with the bit phase synchronization, or a configuration including the synchronization pattern detection circuit You don't have to.

Furthermore, in the embodiment, switching of the system is performed when the bit phase synchronization of the selected system reaches the critical point. However, the condition for switching the system is not limited to reaching the critical point. Therefore, the system may be switched before the bit phase synchronization of the selected system reaches the critical point.

In the above-described embodiment, the case where two systems each including the phase determination circuit, the control circuit, the variable delay circuit, the synchronous pattern detection circuit, and the serial / parallel conversion circuit are used has been described. A bit phase synchronization circuit may be configured using three or more. In this case, when the system selection control circuit recognizes that the phase tracking of the selection system reaches a critical point, the control logic of the system selection control circuit may, for example, best track the phase of the input signal at that time. The system that outputs the delayed clock that is being performed may be selected. In this way, by making changes to the control logic,
One or more bit phase synchronization circuits can be configured.

Further, in the above-described embodiment, the method of selecting an input clock which can be reliably latched for an input signal by the variable delay circuit has been described. A method may be used in which an input signal is input to a delay circuit, and a delayed input clock that can be reliably latched with respect to the input clock is selected by a variable delay circuit.

[0059]

As described above, according to the present invention, when the phase synchronization between the input signal and the input clock by the phase synchronizing means of the selected system is about to break, the input by the phase synchronizing means of the other system is almost complete. By synchronizing the phase of the signal with the input clock and outputting the input signal and the input clock by the phase synchronizing means of another system, it is possible to realize a wide range of phase following the phase fluctuation of the input signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a functional configuration of an embodiment.

FIG. 2 is a block diagram showing a functional configuration of the embodiment in detail.

FIG. 3 is a time chart for explaining the operation of the embodiment.

FIG. 4 is a time chart for explaining the features of the operation of the embodiment.

[Explanation of symbols]

101: phase determination circuit, 102: phase determination circuit, 111
... Control circuit, 112 ... Control circuit, 131 ... Synchronous pattern detection circuit, 132 ... Synchronous pattern detection circuit, 141 ... Serial / parallel conversion circuit, 142 ... Serial / parallel conversion circuit, 150 ... System selection control circuit, 151 ... System selection circuit 152 ... Phase adjustment circuit.

Claims (5)

[Claims] 1. A plurality of phase synchronization means for phase-locking an input signal and an input clock by shifting one of an input signal and an input clock in accordance with a phase difference between them, and the corresponding phase synchronization means A frequency corresponding to each of the plurality of phase synchronizing means is generated by dividing an input clock from the phase synchronizing means to generate a low-speed clock and converting an input signal from the corresponding phase synchronizing means into a parallel signal synchronized with the low-speed clock. Serial-parallel conversion means, and one of the plurality of phase synchronization means and serial-parallel conversion means is selected to output a parallel signal and a low-speed clock. System switching means for outputting a parallel signal of another system and a low-speed clock when the phase synchronization with the input clock is about to fail. Bit phase synchronizing circuit, characterized in that. 2. The apparatus according to claim 1, further comprising: a phase adjusting unit that switches a parallel signal from the system switching unit to an external clock having the same frequency as the low-speed clock, at a stage subsequent to the switching unit. Item 2. The bit phase synchronization circuit according to Item 1. 3. Each of the phase synchronization means includes: a variable delay circuit for delaying an input signal or input clock by an amount of delay based on a given phase control signal; and an input signal or input clock from the variable delay circuit. When,
A phase determining circuit that detects a phase difference from the other input clock or the input signal; and a phase control circuit that forms the phase control signal based on the phase difference detected by the phase determining circuit. The bit phase synchronization circuit according to claim 1. 4. The bit phase synchronization circuit according to claim 3, wherein a common variable delay circuit is applied as a variable delay circuit of each of the phase synchronization means. 5. The phase control circuit in a non-selected state, wherein the phase control circuit has a phase different from a phase of an input signal or an input clock delayed by a phase synchronization unit in a selected state immediately before switching of a selected system or constantly. 4. The bit phase synchronization circuit according to claim 3, wherein a phase control signal for delaying an input signal or an input clock is formed.