JPH07336337A - Duplex/simplex switching system - Google Patents

Abstract

PURPOSE:To prevent the omission of data at the ti.me of changeover by extracting and comparing respective act signals for respectively indicating the operating states of systems from respective data signals from a duplex device and switching the data signals by changeover signals generated from the respective systems. CONSTITUTION:In data sampling circuits 21 and 22, the respective act signals ACT0 and ACT1 multiplexed on the data DATA0 and DATA1 from respective 0-system device 1A and 1-system device 1B are extracted and transmitted to an ACT changeover timing part 23. The timing part 23 compares the respective acts and generates the changeover signals CG based on frame pulse signals FP0 and FP1. A selector 25 performs the changeover from a clock CLK0 and the clock CLK1 to the clock CLK2 by the changeover signals CG. Also, the selector 26 selects the data DATA0 and DATA1 by the signals CG and outputs them to a line L as the data DATA2. In such a manner, since the changeover is performed at the time position of respective frame pattern signals generated by a DTI device 2 at the time of the changeover of the systems, data omission at the time of system changeover is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DTI (Digital Transmission I) of a digital trunk, which is a simplex device, for a signal from a host device which is a duplexer.
The present invention relates to a duplex / single switching method in which switching is performed by an interface device and output to a digital line.

[0002]

2. Description of the Related Art Generally, in this type of host device having two systems, an active system (ACT system; 0 system) and a standby system (SBY system; 1 system), the same signal from both systems is sent to the DTI device. Is output. On the other hand, in the DTI device, the signal from the operating system of the host device is always output to the digital line, but when a failure occurs in the operating system, the signal is switched to the signal from the standby system and output to the digital line. Conventionally, this type of system switching is performed at such a timing that data on the digital line side is not affected as much as possible.

[0003]

However, in the conventional system switching method, since the phases of the signals from the two systems are different, it is impossible to completely prevent data loss, data garbling, etc. during system switching. Therefore, there has been a demand for a highly reliable switching device in which data loss does not occur during system switching.

Therefore, it is an object of the present invention to prevent data loss during system switching and improve the reliability of the device.

[0005]

In order to solve such a problem, the present invention provides a duplexer having two systems of 0 system and 1 system, and inputs each data signal from each system. When a single device is provided that outputs to the digital line as a data signal from one system, and each data signal from the duplexer is switched and output by the single device, the operation status of the system is selected from each data signal. Extraction means for extracting each act signal shown, a system switching timing unit that compares each extracted act signal and generates a system switching signal based on a frame pulse signal from each system, and a data signal and clock from each system A selector unit that switches signals based on the system switching signal, and a frame pattern is inserted into the data signal switched by the selector unit based on the frame pulse signal from each system. A frame pattern inserting means that but on the single apparatus. Also, a counter control unit that generates a counter load signal based on a system switching signal and a frame pulse signal from each system, a counter that outputs a predetermined value based on the counter load signal and a clock signal from any system, and a selector unit. The unifying device is provided with means for inserting a frame pattern when the counter outputs a predetermined value to the data signal switched by the above.

[0006]

When each data signal from the duplexer is switched and output by the single device, each act signal indicating the operating state of the system is extracted from each data signal, and
The extracted act signals are compared with each other, a system switching signal is generated based on the frame pulse signal from each system, and the data signal is switched by this system switching signal. As a result, the data switching is switched at the time position where the data is switched to the next data by each frame pulse, and this time position is the time position where the frame pattern irrelevant to the data is inserted. No data loss occurs at the time of switching, and thus a highly reliable system switching system can be realized. Also, a counter load signal is generated based on the system switching signal and the frame pulse signal from each system, and when the counter outputs a predetermined value based on the generated counter load signal and the clock signal from any system, the switching is performed. A frame pattern is inserted into the acquired data signal. As a result, the frame pattern can be added to the data signal output from the simplex device to the digital line at an appropriate time position.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, reference numeral 1 is a higher-level device, which is a duplexer including a 0-system device 1A and a 1-system device 1B. Further, 2 is a DTI device which is a simplex device, and the DTI device 2 inputs the data output from each device of the 0 system device 1A and the 1 system device 1B and selects the data from one of the devices. Output to digital line L.

Here, the DTI device includes data extracting circuits 21 and 22, an ACT switching timing unit 23, a counter control unit 24, selectors 25 and 26, and an internal operation counter 2.
7, a frame pattern generator 28, and a data insertion circuit 29.

That is, the data sampling circuits 21 and 22 are
Data DAT from 0-system device 1A and 1-system device 1B, respectively
The act signals ACT0 and ACT1 multiplexed in A0 and DATA1 and indicating the states of the respective systems are extracted. Further, the ACT switching timing unit 23 detects the extracted act signals ACT0, ACT1 and the 0-system device 1 from each other.
Frame pulses FP0 and FP from the A and 1 system devices 1B
1 to generate the system switching signal CG.

Further, the selectors 25 are respectively 0-system devices 1A.
And clocks CLK0 and CLK1 from the 1-system device 1B
Is selected based on the system switching signal CG and is output to the digital line L as the clock CLK2. The selector 26 selects the data DATA0 and DATA1 from the 0-system device 1A and 1-system device 1B, respectively, based on the system switching signal CG, and outputs them to the digital line L as data DATA2.

Further, the counter control unit 24 is the 0-system device 1
Frame pulses FP0 and F from the A and 1 system devices 1B
A counter load signal LD to the internal operation counter 27 is generated by P1 and the system switching signal CG from the ACT switching timing unit 23. When the counter load signal LD is input, the internal operation counter 27 sets the value to “0” by the clock CLK2 from the selector 25. The frame pattern generator 28 operates to generate a frame pattern when the value of the internal operation counter 27 is "0". Then, the generated frame pattern is stored in the data insertion circuit 29.
As a result, it is inserted into the data DATA2 output from the selector 26 to the digital line L.

Next, detailed operation of the DTI device configured as described above will be described in detail with reference to the timing chart of FIG. From the 0-system device 1A, the frame pulse F
Signals P0, clock CLK0, data DATA0, and act signal ACT0 are shown in FIG.
DTI device 2 at each timing of (b), (c), and (d)
It has been entered in. Also, from the 1-system device 1B, the respective signals of the frame pulse FP1, the clock CLK1, the data DATA1, and the act signal ACT1 are delayed from the respective signals from the 0-system device 1A, respectively (e) of FIG.
DTI device 2 at each timing of (f), (g), (h)
It has been entered in. That is, in FIG. 2, each signal from the 0-system device 1A is transmitted to the DTI device 2 first, and
An example is shown in which the signal from the system device 1B is transmitted to the DTI device 2 with a delay.

By the way, the DTI device 2 normally DATs the data DATA0 from the 0-system device 1A to the digital line L.
It is output as A2. When a failure or the like occurs in the 0-system device 1A, the data DATA1 from the 1-system device 1B is output to the digital line L as data DATA2.
At this time, data loss or the like occurs. Here, FIG.
Data DATA0 and data DATA of (c) and (g)
The frame pattern signal F included in 1 is the DTI device 2
The signal F is a bit unrelated to the data (Don't Care) when viewed from the host device 1 side.

In the present invention, this frame pattern signal F
Paying attention to the time position of, the switching timing of the data input from each system is set at the time of this signal F so that the loss of the data at the time of switching the system can be prevented. That is, first, in the data sampling circuits 21 and 22, the act signals ACT0 and ACT0 of FIGS. 2 (d) and 2 (h) multiplexed with the data DATA0 and DATA1 from the 0-system device 1A and the 1-system device 1B, respectively.
ACT1 is extracted and sent to the ACT switching timing unit 23.

In this case, the ACT switching timing section 23 compares the act signals ACT0 and ACT1 and generates the system switching signal CG shown in FIG. 2 (i) based on the frame pulse signals FP0 and FP1. That is, in the example of FIG. 2, the act signal ACT0 from the 0-system device 1A is at the “L” level to indicate an operating state, and the act signal ACT1 from the 1-system device 1B is at the “H” level and is not high. Since the operating state is shown, the ACT switching timing unit 23 switches the system at the intermediate time position of the frame pulse FP1 of the device in the non-operating state. With this system switching signal CG, the selector 25 switches the clock CLK2 shown in FIG. 2 (k) from the clock CLK0 to the clock CLK1. Further, the selector 26 converts the data DATA2 to the digital line L shown in FIG.
Switch to TA1.

In this way, when the system is switched, it is possible to switch at the time position of each frame pattern signal F generated by the DTI device 2, so that the loss of data at the time of system switching is prevented. Further, since the above-mentioned internal operation counter 27 malfunctions due to cracking or phase shift of each clock signal at the time of system switching, the counter control unit 24 causes the counter load signal L to be given to the internal operation counter 27.
Generate D as follows. That is, in the counter control unit 24, the system switching signal C from the ACT switching timing unit 23
2 based on G and the frame pulses FP0 and FP1.
The "H" level counter load signal LD shown in (j) is generated. In other words, the frame pulse FP0 previously transmitted to the DTI device 2 brings it to the “H” level, and the frame pulse FP1 from the system to be switched to “L” level.
The counter load signal LD which becomes the level is generated.

The counter load signal LD is sent to the internal operation counter 27. Counter 27 for internal operation
Now, when this counter load signal LD is input, as shown in FIG.
As shown in (k) and (m), the value is set to "0" at the rising edge of the clock CLK2 output from the selector 25. Then, even when the next clock CLK2 rises, the counter load signal LD is at the “H” level, and therefore the counter value remains “0”. After that, the counter load signal LD becomes "L" level, and finally the counter value becomes "1" at the next rising edge of the clock CLK2.
Becomes Here, while the value of the internal operation counter 27 holds "0", the frame pattern generator 2
8 generates a frame pattern. Data insertion circuit 29
2 inserts this frame pattern from the selector 26 into the digital line L in the DATA 2 shown in FIG. 2L and outputs it to the digital line L.

In this way, the 0-system device 1A to the 1-system device 1
To switch the system to B, this DTI device 2
Switching is performed at the time position of the frame pattern to be inserted into TA0 and DATA1, and the frame pattern is inserted into the data DATA2 from the selector 26 to the digital line L when the value of the internal operation counter 27 is "0". It was done. As a result, it is possible to reliably prevent data loss and the like during system switching.

Next, FIG. 3 is a timing chart showing the operation of another embodiment of the DTI device 2. In this example, each signal from the 1-system device 1B is transmitted to the DTI device first, and then each signal from the 0-system device 1A is transmitted to the DTI device 2. Even in such a case, the ACT switching timing unit 23 compares the act signals ACT0 and ACT1 extracted from the data DATA0 and DATA1 and, based on the frame pulses FP0 and FP1, the same FIG. The system switching signal CG shown in (i) is generated.
That is, the ACT switching timing unit 23 is switched 1
The system switching signal CG is generated at an intermediate point of the frame pulse FP1 from the system device 1B to switch the system.

Then, the counter control unit 24 based on the system switching signal CG and the frame pulses FP0 and FP1.
Generates the "H" level counter load signal LD shown in FIG. That is, the counter control unit 24 is
In the same manner as in the above example, a counter load signal LD is generated which becomes “H” level by the frame pulse previously input to the DTI device 2 and becomes “L” level by the frame pulse from the system to be switched. When the counter 27 for internal operation receives the "H" level counter load signal LD, the value thereof becomes "0" at the rising edge of the clock signal CLK2, as in the example of FIG. Then, when the counter load signal LD becomes "L" level, the next clock CLK
At the rising edge of 2, the value is set to "1", and the value "0" is held during this period.

Thereafter, as in the example of FIG. 2, while the value of the internal operation counter 27 is "0", the frame pattern generator 2
8 generates a frame pattern, and the generated frame pattern is generated by the data insertion circuit 29 from the selector 26 to the digital line L and the data D shown in FIG.
The frame pattern F is inserted into the ATA2.

[0022]

As described above, according to the present invention, when each data signal from the duplexer is switched and output by the single device, each act signal indicating the operating state of the system is selected from each data signal. Along with extracting the act, the extracted act signals are compared and a system switching signal is generated based on the frame pulse signal from each system, and the data signal is switched by this system switching signal. Switching is performed at the time position where the data is switched to the next data by each frame pulse, and this time position is the time position where a frame pattern irrelevant to the data is inserted. Therefore, it is possible to realize a highly reliable system switching system. Also, a counter load signal is generated based on the system switching signal and the frame pulse signal from each system, and when the counter outputs a predetermined value based on the generated counter load signal and the clock signal from any system, the switching is performed. Since the frame pattern is inserted for the data signal that is obtained,
A frame pattern can be added to the data signal output from the simplex device to the digital line at an appropriate time position.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the timing of each part of the apparatus of the above embodiment.

FIG. 3 is a timing chart showing another timing example of the apparatus of the above embodiment.

[Explanation of symbols]

1 ... Host device, 1A ... 0 system device, 1B ... 1 system device, 2 ...
DTI device (single device) 21, 22 ... Data sampling circuit, 23 ... ACT switching timing unit, 24 ... Counter control unit, 25, 26 ... Selector, 27 ... Internal operation counter, 28 ... Frame pattern generating unit, 29 … Data insertion circuit, L… Digital line.

Claims (2)

[Claims] 1. A duplexer having two systems, a 0 system and a 1 system, and a single system for inputting each data signal from each system, selecting a data signal from any one system, and outputting to a digital line. In the duplex / single switching method in which each data signal of the duplexer is switched and output by the duplexer, each act indicating the operating state of the system from each data signal transmitted from each system. Extraction means for extracting a signal, a system switching timing section for comparing each extracted act signal and generating a system switching signal based on a frame pulse signal from each system, a data signal and a clock signal from each system A selector unit that switches based on the system switching signal, and a frame pattern is inserted into the data signal switched by the selector unit based on the frame pulse signal from each system. That the frame pattern inserting means provided on the single apparatus, switched redundant-unification switching mode and outputs the data signal to the digital line. 2. The duplex / single switching method according to claim 1, further comprising: a counter controller that generates a counter load signal based on the system switching signal and a frame pulse signal from each system.
The unification device is provided with a counter that outputs a predetermined value based on the counter load signal and a clock signal from any one of the systems, and the frame pattern insertion means is provided for the counter for the data signal switched by the selector unit. A duplex / single switching method characterized by inserting a frame pattern when a predetermined value is output.