JPH01176197A - Time division multiple access exchange system - Google Patents

Abstract

PURPOSE:To attain time division exchange of a multiple access signal while preserving timewise sequence in a frame by using a channel frame for two frames even if there is a difference in the frame phase between the input and output. CONSTITUTION:When the frame phase between the input and output is not coincident, it is possible to read a signal of one preceding frame before an input signal is written in the phase from the head of the frame of an output signal till the end of the frame of the input signal. Thus, the time switch applies control to read a signal written in one preceding frame in a multiple access signal required for exchange between time slots in the phase from the head of the frame of the output signal till the end of the frame of the input signal to preserve timewise sequence of the multiple access signal in the frame. Thus, the time switch acts like a frame aligner when the frame phase between the input and output highways differs.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a time division exchange system for exchanging multiple signals.

(Prior art) When exchanging multiple signals that collectively use a capacity that is an integral multiple of the basic bearer speed, which is a unit of communication capacity, using a time switch, it is necessary to exchange multiple basic bearer signals that make up the multiple signal. The order must match on the human power side and the output side. For this reason, a conventional method has been known in which the frame phases of time-division multiplexed signals on the input/output highway are matched and exchanged using two-sided communication path memory. Regarding the time shifter using conventional technology, see Nikkei Electronics Magazine, 1987, March 3.
The one described in the May 9th issue, pages 96 to 98 is known.

FIG. 5 is a block diagram showing the configuration of a time switch according to the prior art. The time division switching circuit includes an input highway 301, a demultiplexer 302 whose input is connected to the highway 301, and a first channel memory 304 whose data input DI is connected to a first output of the demultiplexer 302. a second channel memory 305 whose data input DI is connected to a second output of the demultiplexer 302;
The first input is the data output Do of the communication path memory 304,
A second human power is connected to the multiplexer 306 connected to the data output DO of the communication path memory 305, and a human power is connected to the highway 3
01, a control input is connected to the output of the frame detection circuit 309, the most significant bit output MSB is connected to the control input of the demultiplexer 302, and the output is the channel memory 304.

A counter 310 is connected to the write address input WA of 305, and the input is the highest focus output M of the counter 310.
an inverting circuit 311 connected to SB and having an output connected to a control input of multiplexer 306; and a control circuit 320.
The data manual DI and the write address WA are in the control circuit 32.
The read address manual RA is output from the counter 310 at the output of 0.
The data output DO is connected to the output of the call memory 304.
, 305 and a control memory 321 connected to the read address manual RA.

In FIG. 5, a case will be described in which multiplexed speech signals (a, d) multiplexed into time slots 1 and 4 on input highway 301 are output to time slots 1 and 2 on output highway 308. FIG. 6 is a time chart showing the operating state of the time shifter shown in FIG.

First, the counter 310 that controls the overall operation timing is
It is reset by the frame detection circuit 309 at the beginning of the frame phase of the speech signal multiplexed on the input highway. The output of this counter 310 is used as the address for the speech signal a1 on the input highway.

a, a2, d2 as the address # of the communication path memory 304
1, #4, address #L of communication path memory 305 #4
Write each.

On the other hand, in order to output the multiple call signals (a, d) multiplexed into time slots 1 and 4 on the input highway to time slots 1 and 2 on the output highway,
The control circuit 320 writes 1 in advance to address #1 and 4 to address #2.

The speech signal written in the speech path memory is read out in accordance with the control memory in the next frame written from the speech memory opposite to the speech path memory currently being written. That is, in time slots 1 and 2 of frame F2, call signals ae and do are read from addresses #1 and #4 of call path memory 304, respectively.

In this way, the speech signals multiplexed into all the time slots are stored in the speech memory for one frame and then outputted, thereby creating the speech signal a1' dl r a2pd.
can be output to time slots 1 and 2 of the output highway while maintaining their order.

(Problems to be Solved by the Invention) In the time switch according to the prior art shown in FIG. , it is necessary to match the frame phase between the input and output highways. Therefore, when the frame phase of the human output highway is determined in advance, such as in a T-8-T exchange configured by connecting time switches (T) and space switches (S) in multiple stages, first-in-first-out ( It is necessary to align the frame phases of the input/output highway of the time switch using a frame aligner using a FIFO (FIFO) memory or the like, which leads to an increase in hardware.

(Means for solving the problem) According to the present invention, it has a communication path memory for two frames,
When the time-division multiplexed signals multiplexed on the input highway are written into the channel memory two frames at a time, and the multiplexed input/output time slots of the multiple signals to be connected are made to correspond in the order of time slot numbers. , at least one set of a manual time slot into which a multiplex signal to be exchanged and an output time slot corresponding to the input time slot are arranged, both of which extend from the beginning of a frame on the output time division multiplex signal to the frame on the input time division multiplex signal. If it is in the phase up to the end of the output signal frame, the signal written in the input frame immediately before the frame written at the beginning of the frame of the output signal is A time division multiple exchange method is obtained in which the input signal of the frame written at the beginning is read out from the channel memory according to the correspondence relationship.

(Function) If the frame phases between input and output do not match, read the signal of the previous frame before writing the input signal in the phase from the beginning of the frame of the output signal to the end of the frame of the input signal. there is a possibility. Therefore, there is a possibility that the time order among the plurality of signals forming the multi-signal cannot be preserved. Therefore, in the time switch according to the present invention, the multiple signals that require exchanging between time slots in phase from the beginning of the frame of the output signal to the end of the frame of the input signal are the signals written in the previous frame. The time order of multiple signals within a frame is preserved by controlling the readout of the signals.

This allows the time switch to operate not only as a phase conversion switch but also as a frame aligner when the frame phases between input and output highways are different.

(Example) The time switch of the present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. 1st
According to the figure, embodiments of the present invention provide input highway 101
, a demultiplexer 102 whose input is connected to the highway 101, and a data input DI connected to the demultiplexer 10.
a first channel memory 104 connected to a first output of 2;
and a second channel memory 105 whose data input DI is connected to the second output of the demultiplexer 102, whose first input is connected to the data output DO of the channel memory 104 and whose second input is connected to the channel memory 104. A multiplexer 106 connected to the data output DO of 105, a frame detection circuit 109 connected to the highway 101, a control circuit connected to the output of the frame detection circuit 109, and a most significant bit output MSB of the demultiplexer 102. For the control input, the output is the write address input W of the communication path memory 104, 105.
A counter 110 connected to A, a control circuit 120,
The counter 112 and the human power input the output of the counter 112 to M
The SB input is connected to the MSB output of the counter 112, the latch pulse input is connected to the output of the frame detection circuit 109, and the latch 113 whose output is connected to the input of the control circuit 120, the data input DI and the write address input WA are controlled. At the output of the circuit 120, a read address input RA is connected to the output of the counter 112, a control memory 121 whose data output Do is connected to the read address input RA of the call memory 104.105, and a first input of the counter 112. The second human power inputs the control memory 12 to the most significant bit output MSB.
an exclusive OR circuit 1 connected to the frame control signal output of 1 and whose output is connected to the control input of the multiplexer 106;
It consists of 11.

In FIG. 1, a case will be described in which multiplexed speech signals (a, d) multiplexed into time slots 1 and 4 on input highway 101 are output to time slots 1 and 2 on output highway 108. FIG. 2 is a time chart showing the operating state of the time switch shown in FIG. In this case, it is assumed that the frame phase between input and output is shifted by two time slots. Furthermore, this information is stored in the counter 11
2 can be provided to the control circuit 120 by launching it at the beginning of the input frame.

First, the counter 11 controls the write timing of the input signal.
0 is reset once every two frames at the beginning of the frame FI of the speech signal multiplexed on the human-powered highway by the frame detection circuit 109. This counter 11
0 as the address and call signal a1.0 on the input highway. d0. a2. d2 to address #1 of the communication path memory 104. #4 and addresses #1 and #4 of the communication path memory 105 are respectively written.

On the other hand, in order to output the multiple call signals (a, d) multiplexed into time slots 1 and 4 on the input highway to time slots 1 and 2 on the output highway, the control circuit 120
address #1 of the control memory 121. Write 1 and 4 to #2, respectively. Furthermore, the control memory is provided with one more bit of the address of the channel memory and a frame control signal. In this case, since there is a frame phase difference of 2 between input and output, input time slot 4 and output time slot 2
are in the same phase, and it is necessary to shift the writing and reading of signals by one frame. Therefore, address #1. 1 is written in the #2 frame control signal.

The call signals written in the call path memories 104 and 105 are read out according to the control memory 121. At this time, if the frame control signal in the control memory 121 is 1, the signal written in the input frame immediately before the frame written at the beginning of the frame of the output signal will be changed if the frame control signal is 0. In this case, the signal written at the beginning of the output signal frame is read out. This results in
As shown in Figure 6, time slot 1 of frame FO2
Then, the speech signal a1 of the previous frame is read from address #1 of the speech path memory 104, and
Now, the call signal d is sent from address #4 of the call path memory 104.
0 is read.

In this embodiment, counter 1 for counter 110
The case where the delay of 12 is within 1 frame has been explained, but if it is between 1 frame and 2 frames, the result of latching the MSB of counter 112 with latch 113 is O.
The control circuit detects this, inverts the frame control signal, and writes it into the control memory 121. In addition, the operation described in this embodiment can be performed regardless of the delay of the counter 112 with respect to the up counter 110.

In this way, the call signals a, d1. a2. d2 can be output to time slots 1 and 2 of the output highway while maintaining their order within the frame.

In the embodiment shown in FIG. 1, the case of 4-multiplexing has been explained, but an example that occurs when the degree of multiplication is large will be explained with reference to FIG. 3. FIG. 3 schematically represents the signals on the input highway and the output highway. Here, the multiplexed signal A (AI, A2. A3) has the second time slot from the beginning of the frame on the output time-division multiplexed signal with diagonal lines to the end of the frame on the input time-division multiplexed signal. FOl preserves the time order of the multiple call within the frame by reading the signal written in FIo. In this case, the delay time is the longest when Alo is exchanged from the first time slot of FIo to the last time slot of the hatched portion of FO. However, even this longest delay time does not exceed two frames, as can be seen from FIG.

On the other hand, for multiple signal B (B□, B2), only the first time slot of the output has a phase from the beginning of the frame on the output time division multiplexed signal with diagonal lines to the end of the frame on the input time division multiplexed signal. Since it is only in FO□, FI,
Read the signal written in. In this case, the human signal is F
Since the output is stored before the beginning of O□ and the output is read after the beginning of FO, the time order of the multi-party call can be preserved within the frame. Conversely, if B2□ is read from FOo, the delay will exceed two frames.

As shown in this embodiment, by reading only a specific multi-party call from the information written one frame before, even if the frame phase of the input/output highway is shifted, the multi-party call can be made using two frames worth of channel memory. can be exchanged while preserving the temporal order within the frame.

Next, a second embodiment will be described with reference to FIG.

In this embodiment, the hardware operation is exactly the same as that in FIG. This embodiment differs from the first embodiment only in how frame control information is determined. FIG. 4(a) shows the output time slot number of the signal plus the manual time slot number at the beginning of the frame of the output signal;
This corresponds to the input time slot number.

For multiple signals A (A1, A2), the sum of the output time slot number of the signal and the input time slot number at the beginning of the frame of the output signal is greater than the input time slot number, so 0 is written in the frame control signal of the control memory 121. As a result, Figure 4 (b
), the signal written to the memory by the FI engineer is FO.
It is read with l.

On the other hand, in multi-signal B (B, B2), the number 7, which is the sum of the output time slot number of the B2 signal and the input time slot number at the beginning of the frame of the output signal, is greater than the input time slot number 8, and this is actually When information is read based on the relationship, information from two frames before is read. Therefore, 1 is written in the frame control signal of the control memory 121 in FIG. 1, and as shown in FIG. 4(b), the signal written in the memory in the F process is read out in the FO process.

As described above, even in the second embodiment, the time order of multiple calls can be exchanged while preserving the time order within the frame using two frames worth of communication path memory.

In the two embodiments shown individually, an example of sequential write/random read has been described, but similar operation can be obtained by random write/sequential read.

(Effects of the Invention) As described above, according to the present invention, even when there is a difference in frame phase between input and output, the time order within the frame is preserved and the multi-channel signal is Time division exchange can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
3 is a time chart showing the operating state of the embodiment shown in FIG. 1, FIG. 3 is a time chart showing multiple exchange when the highway multiplicity is large, and FIG. 4 (a). (b) is a time chart showing multiple exchange when the highway multiplicity is large in the second embodiment of the present invention;
FIG. 6 is a block diagram showing the configuration of a time switch according to the prior art, and FIG. 6 is a time chart showing the operating state of the time switch shown in FIG. In the figure, 102.302 is a demultiplexer, 10
4°105, 304.305 is a communication path memory, 106.
306 is a multiplexer, and 121 and 321 are control memories, respectively.

Claims (3)

[Claims] (1) It has a communication path memory for 2 frames and a control memory that stores 1 bit of frame control information in the bit direction in addition to the read address of the communication path memory for 1 frame, and the content of the frame control information is Determined for each call setting according to the frame phase delay amount of the output as seen from the input and the correspondence between the input and output of a plurality of time slots accommodating a multi-party call, and reading out information from the two frames of communication path memory. A time division multiple exchange system characterized in that memory is determined according to the frame control information. (2) When the multiplexed input/output time slots of the multiple signals to be connected are made to correspond in order of time slot numbers from the beginning of the frame of each input/output signal, the input time slot into which the multiple signals to be exchanged enters. and at least one set of output time slots corresponding to the input time slots,
If both are in phase from the beginning of the frame on the output time-division multiplexed signal to the end of the frame on the input time-division multiplexed signal, one frame before the input frame being written at the beginning of the frame of the output signal. a read address so as to read the input signal written in a frame, or in the case of other multi-component signals, the input signal of the frame written at the beginning of the frame of the output signal from the channel memory according to the correspondence relationship; The time division multiple switching system according to claim 1, characterized in that frame control information is determined. (3) When the multiplexed input/output time slots of the multiple signals to be connected are made to correspond in order of time slot numbers from the beginning of the frame of each input/output signal, the output time slot into which the multiple signals to be exchanged enters. If the sum of the number and the input time slot number at the beginning of the frame of the output signal is smaller than the input time slot number corresponding to the output time slot number, then at the beginning of the frame of the output signal. The input signal written in the frame immediately before the input frame being written is changed to the input signal of the frame written at the beginning of the frame of the output signal in the case of other multi-dimensional signals. 2. The time division multiple exchange system according to claim 1, wherein the read address and frame control information are determined to be read from the channel memory according to the relationship.