JPS62194797A - Multiple access time switch - Google Patents

Abstract

PURPOSE:To suppress the exchange delay to a required minimum value by applying the data write to both sides of time switches depending on the necessity of the sequence of the data of a single frame for one side each or for both sides simultaneously. CONSTITUTION:Input information D is given to switches 1, 2 and written in synchronism with a counter 7 of 2-frame period. A control signal represented whether each time slot data calls for the sequence or not is stored in a write control memory 5 and a write control circuit 3 applies the write control of information D based on the control signal and the frame member of the counter 7. That is, the data requiring the sequence at a frame number '0' applies write to the switch 1, the data requiring the sequence in the frame 1 applies write to the switch 2 and the data not requiring the sequence applies write to both the switches 1, 2 at each frame. The written data is outputted via a selection circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time division switch, and more particularly to a multi-time switch that handles complex traffic.

[Conventional technology]

When performing time division exchange, assuming that the time slot numbers on one frame are arranged in ascending order on the time axis, data of any time slot number on any frame is transferred to a time slot with a higher number than the own time slot number. , it is possible to replace it with the corresponding slot on the same frame, but when replacing it with a timeslot with a smaller number than the own time slot number, it is possible to replace it with the corresponding time slot on the same frame. has passed, ta is inserted into the corresponding time slot on the subsequent frame.
will be replaced. Time slot numbers m and n (m.

When n is both positive and the data of m (in the relationship of n) is replaced with each time slot number m-1, n+j (both i and j are positive divisors), the following is shown in Figure 4. As such, the data of time slot number n on the gl frame is replaced with time slot number n + j on the same frame, but the data of the t-th
The data of time slot number m on the frame is replaced with time slot number m −i of the subsequent t+1th frame, so the order of the data is reversed. When a series of data spanning multiple time slots in the same frame has a single meaning, "C" In order to solve the above drawback, conventional methods have been able to store data from all time slots in one frame, as shown in Figure 3. The IL system consists of two parallel memories 31 and 32, a selection circuit 34 and a control memory 33 in which one side is input and the other side is output for each frame, and all time slots of an arbitrary frame are processed. The above data is accumulated in the memory of one side, and then the data of all time slots of the subsequent frame is accumulated in the memory of the other side, while the data is transferred from the memory of the previous side according to instructions from the control unit. This method ensures the order of a series of data in multiple time slots in the same frame.

[Problem that the invention seeks to solve]

In the conventional method described above, the data on all time slots of all frames is always temporarily stored in the memory of the time switch and read out in the next frame, so there is no need to preserve the order of time slots. There is also a problem in that a systematic delay of one frame or more and two frames or less always occurs even for a bandwidth call.

[Failure to solve the problem]

The multidimensional time switch of the present invention includes a two-sided time switch and two
It has a frame period timing circuit, a selection circuit that selects the output of the two-sided time switches, and a write control circuit for the two-sided time switches.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes a two-sided time switch, a time switch 11, a time switch 2, a selection circuit 4 for selecting its output, and a selection circuit 4 for controlling data readout from the time switch. a control memory 6, a 2-frame period counter 7 used to specify the input time slot and output time slot of the time switch, a write control memory 5 that outputs write control information of the time switch according to the value of the counter 7, and It is constituted by a write control circuit 3 that controls writing in synchronization with the output of the write control memory 5.

The input information to the time switch is given to both the time switch 1 and the time switch 2, and is written to the time switch in synchronization with the counter 7 with a two-frame period. The write control memory 5 outputs a write control signal indicating whether the time slot data is data that requires order or does not require order, in accordance with the time slot number of the counter 7. . The write control circuit 3 transfers the data required to have the jiI order to the time switch 1 in 7 frames 1 based on the output of the write control memory 5 and the frame number indicated by the counter 7 with a 2-frame period. Data that requires order is written to time switch 2, and data that does not require order is written to time switches 1 and 2 for each frame. The data written to the time switch is outputted to the time switch based on the address outputted from the control memory 6 in accordance with the time slot of the counter 7. For the data output from the time switch, the selection aid 1 path 4 selects the output of the time switch 2 in frame 0 and the output of the time switch 1 in frame 1 according to the frame number of the counter 7.

FIG. 2 is a timing chart showing the flow of data in this time switch. Among the input signals of the time switch, a indicates a signal that requires order, and b indicates a signal that does not require order. .

The frame of the input signal to the time switch at the time when the frame number indicated by the counter 7 is 0 is 7, the frame is frame t, and the input time slot is m.

m, , m, output time slot “l + J +
``3, m, to n, hem2 to n2, m, to n, (t, ml, mz, m8.
n, , n, , n3 are positive integers and n+<”+<mz<”s
The relationship is <n2<na. ) data a on frame L
I+a2 is written to time switch 1, data b is written to both time switch 1gt and time switch 20, and the above data a! +a4 is data b to time switch 2.

is written to both time switch l and time switch 2. Time switch 1 and time switch 2 output data at the address indicated by the control memory in accordance with the time slot of the counter.

Due to the phase relationship of the time slots, data,a,is transferred to frame /,+1 of time switch 1 and frame L+2,
Data a2 is transferred to frame t+1 and frame t+1, and data a is transferred to frame t+1 and frame t of time switch 2.
+2, data a4 is sent to frame t+1 and frame t+
2, the data b, , b, , b, are the frames t, t of time switch 1 and time switch 2.
+1, 1 and 2 respectively.

The outputs of time switch 1 and time switch 2 are selected by the selection circuit 4 according to the frame number of the counter 7. At frame number O, that is, frame t, the output of time switch 2 is selected, and at frame number 1, that is, frame t+1, the output of time switch 2 is selected by the selection circuit 4. 1 is selected, and the output of the time switch guarantees order for data that requires order, such as data a□+"t+"M..., and data b, , b2, etc., which do not require order, can be output with a delay of one frame or less.

〔Effect of the invention〕

As explained above, the present invention includes a two-sided time switch,
By providing a selection circuit that selects the output, and a write control circuit that writes data that requires order to the time switch on one side at a time, and writes data that does not require a floatability to the memories on both sides at the same time, multiple Data t that requires preservation of order over time slots has the effect of preserving order, and data that does not require preservation of order has the effect of minimizing the exchange delay.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 shows a timing chart for the embodiment shown in Fig. 1, Fig. 3 is a block diagram showing a conventional example, and Fig. 4 shows a time switch with a one-sided configuration. This is a timing chart. 1...Time switch, 2...Time switch, 3...Write control circuit, 4...
・Selection circuit, 5...Heating control memory, 6.
...Control memory, 7...Counter. Agent: Benkei Uchihara T? ',,. ′! 5 l Figure 3

Claims (1)

[Claims] In a multi-time switch in a time division exchange, the first
a time switch, a second time switch, a counter with a two-frame period, and in synchronization with the output of the counter, in the first frame, the data read from the second time switch is selected, and in the next frame, the data read out from the second time switch is selected; , a selection circuit that selects the data read from the first one-time switch, and control data that indicates whether the time slot contains data that requires order or data that does not require order. The write control memory to be held and the data that requires order based on the data in the write control memory are synchronized with the output of the counter, and in the first frame,
Write to the switch for the first hour, and in the next frame,
A multi-dimensional time switch characterized by comprising a write control circuit that writes data to the second time switch and writes data that does not require order to both the first time switch and the second time switch in each frame.