JPH024070A - System for controlling communication data destination - Google Patents

Abstract

PURPOSE:To correctly execute the destination control of data for each time slot by executing the destination control of the data of each time slot in an input data signal based on destination control data held in a control register unit to be impressed to a selector. CONSTITUTION:A selector 1 select-outputs input data signals DT11-DT1m for executing the destination control. Destination control data DATCNT for each time slot are held once by a buffer register unit 4. The destination control data DATCNT held in the buffer register unit 4 are simultaneously held in a control register unit 3 based on data write signal DATWR. A timing control circuit 2 outputs a control data output signal CDOUT synchronizing to the time slot of the input data signal to the control register unit 3, and the destination control data of the time slot are impressed from the control register 3 to the selector 1 in synchronizing to the time slot.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for controlling the destination of communication data, it is possible to control the destination with accurate timing and also to control the destination of data for each time slot of each input signal. This is a communication data destination control method that controls the destination of an input data signal having data assigned to a time slot in each frame via a selector based on destination control data. a buffer register unit that holds destination control data; a control register unit that simultaneously holds destination control data of all time slots held in the buffer register unit based on a data write signal; and a frame of the input data signal. and a timing control circuit that outputs a control data output signal synchronized with the time slot,
Destination control data held in the control register unit is applied to the selector in response to a control data output signal synchronized with a time slot from the timing control circuit, and the data of each time slot in the input data signal is applied to the The destination is controlled based on destination control data held in the control register unit applied to the selector.

[Industrial application field]

The present invention relates to a communication data destination control method in a communication system, and particularly to a communication data destination control method for controlling the destination of data for each time slot at accurate timing.

The communication data destination control method of the present invention is suitably used for destination control in a communication system that performs high-speed data transmission, such as broadband 15DN.

[Conventional technology]

Figure 8 shows two types of input signals D T in the communication control device.
A circuit for controlling the destination of r + and D T r 2 via a selector 1 is shown. Input signal DTr+, D'rr□
As shown in FIGS. 9(a) and 9(b), data is set in three time slots for each frame.

The circuit of FIG. 8 outputs the second output data as the destination output data DTOUT for each frame, as shown in FIG.
Destination control data D A TCTI so that the input signal, the first input signal, and the second input signal of
, DATCT2, and outputs the 8 outputs to the selector 1.

This causes the destination control data DATCTI.

Output data DTOLIT is output from selector 1 based on D A TCT2.

Destination control data D A TCTI, D A TCT□
If the output is performed for each time slot in each frame, the destination of the input signal can be controlled for each time slot.

[Problem to be solved by the invention]

Destination control data is normally written to the control register unit by a computer in the communication control device that detects the source and destination (destination) of the data. is performing other control processing.

In this case, if a timing difference occurs between the writing of destination control data and the output timing from the control register unit and the timing of applying the input signal to selector 1,
As shown in Figure (C) (d), in frame 1, the second input signal, 2+1' 212213, in frame 2, the first input signal 22. .

22□, 2□3, second input signal 2 in frame 3
3+'232'23'3 should be output, but in reality, in frame 1, 111'212'
2 +3, 2° at frame 2, ・1°2112
3. In frame 3, 13□, 13□, and 233 are output.

In particular, when the input signal becomes high-speed, such as in a wideband 15DN, the timing difference between the write and output timing of destination control data and the application timing of the input signal, that is, the application timing of each frame signal of the input signal, becomes large. There is a problem that the destination cannot be controlled.

In addition, in wideband 15ON, etc., it is desired to control the destination of each slot data within a frame, but in this case, the above timing difference must not exist, and the circuit shown in Fig. 8 does not meet this demand. It cannot be realized.

In view of the above problems, it is an object of the present invention to realize a communication data destination control method that can accurately control the destination of data not only for each frame but also for each time slot.

[Means to solve the problem]

As shown in the principle block diagram of the communication data destination control method of the present invention in FIG.
Selector 1 for selectively outputting T, r- to control destination
and destination control data DATCNT for each time slot.
a buffer register unit 4 that temporarily holds the destination control data DA held in the buffer register unit;
TC) has a control register unit 3 that holds one TC simultaneously based on a data write signal DATwi. Furthermore, the communication data destination control method of the present invention provides a control data output signal CD0U synchronized with the time slot of the input data signal.
The timing control circuit 2 is configured to output T to a control register unit 3 and apply destination control data of a corresponding time slot from the control register unit 3 to the selector 1 in synchronization with the time slot.

FIG. 1 generally shows m series of input data signals D T I
A case is shown in which data I to D T I- are input to the selector 1 and the destination is controlled as n series of output data signals DTo+ to D T , . The circuit of FIG. 1, for example, outputs multiple series of output data signals DToI-DT from one series of input data D T r +. , , when controlling the destination, conversely, multiple series of input data D T I+~D
One series of output data signals DT from T+-. , and any combination thereof.

[For production]

With reference to FIGS. 2(a) to 2(f), a case will be described in which the destination of data for each frame is controlled.

In order to simplify the explanation, two series of input data signals DT++ 5DT+□ are input to the selector 1, each having 3 slots of data in each frame, and the output data DTout whose destination is controlled is 1. Let's discuss the case where it is a series.

Destination control data DATcNt (FIG. 2(C)) is applied to the buffer register unit 4 and held there.

Destination control data DATCMT instructs destination control for each time slot and is composed of three types of data, each of which indicates each time slot of the second input data signal.
20.2□, 23 data. Destination control data DA
TC)IT may be intermittently applied to the buffer register unit 4 as shown by the solid line in FIG. 2(C),
The buffer register unit 4 is connected continuously as shown by the broken line.
may be applied. The destination control data DATcNy once held in the buffer register unit 4 is the data write signal D that is output after the last one of the destination control data DATCNT is held in the buffer register unit 4.
The data are written in the control register unit 3 all at once by the ATWR (FIG. 2(d)). On the other hand, the timing control circuit 2 applies a control data output signal CD0UT synchronized with the time slot within the frame to the control register unit 3 based on the frame signal FLM (FIG. 2(e)), and writes the control data output signal CD0UT to the control register unit 3. The selected destination control data DATCNT is sequentially outputted to the selector 1 in correspondence with the time slots.

A control data output signal CD0UT synchronized with the time slot is sequentially output from the timing control circuit 2 to the control register unit 3 (FIG. 2(e)), but as shown in FIG.
The control data output signals after the seventh in e) are as shown in Fig. 2 (C
Destination control data DATC) I set as shown in )
T is sequentially output to selector 1. This allows the second
Timing of the seventh and subsequent control data output signals in Figure (e) and destination control data DATCII output at that time
The input data signal D applied to selector 1 according to the value of
Tr+.

D T r 2 is selected and output by selector 1 to control the destination. In this example, the first input data signal D
A T r + to the second input data signal D A T
All data of frame 3 is switched to r2 (destination control).

It is preferable that the data write signal DATwi is provided as a pulsed signal in the frame before the frame in which the destination control is to be changed. In addition, the control data output signal CD0
A pulse signal is also preferable for UT.

According to the above, for example, the CPU that outputs the destination control data DATCNT can output the destination control data without considering the output timing of the destination control data DATCNT. Furthermore, even if the bit rate of the input data signal becomes high and the CPU is no longer able to output destination control data in synchronization with frames or time slots as in the past, the buffer register shown in FIG. By controlling the selector 1 by cooperating the unit 4, the control register unit 3, and the timing control circuit 2, accurate destination control is possible.

Next, with reference to FIGS. 3(a) to 3(f), a case will be described in which the destination of data for each time slot within one frame is controlled. As described above, the communication data destination control method shown in FIG. 1 basically enables destination control for each time slot. Therefore, in this case, simply set the destination control data DATCN to 11 as shown in FIG. 3(C).
, 22.13, and output at the timing shown by the solid line or broken line, the output data DATOUT of frame 3 will be output at the timing of the seventh and subsequent control data output signals CD0UT shown in FIG. 3(e). , the first input data signal D T + in the first time slot
+ first time slot data I31 in the third frame
, the second time slot data 232 in the third frame of the second input data signal D T I 2 in the second time slot, the second time slot data 232 in the third frame of the first input data signal DTI+ in the third time slot Three time slot data 133 are output respectively.

〔Example〕

FIG. 4 shows a circuit diagram of a communication data destination control system according to an embodiment of the present invention.

In FIG. 4, the control register unit 3 in FIG.
The timing control circuit 2a is realized by a timing extraction circuit 21 and a decoder 22. The decoder 22 is a time slot counter 22
1 and a selector 222. Further, the buffer register unit 4 in FIG. 1 corresponds to the RAM 4a, and the selector 1 in FIG. 1 is an equivalent selector 1a.

The embodiment of FIG.
A case is shown in which one output data signal DTOUT is output by controlling the destination of Tr+ and DTI2.

The number of memories in the RAM 4a is sufficient to store destination control data. Destination control data is provided by a CPU (not shown)
etc. is output from. RA of destination control data DATCNT
Writing to M4a is performed using the write control signal WR from the CPU.
It is carried out based on c. In this case, as shown in FIG. 2(C) or FIG. 3(C), the necessary destination control data D A
It is preferable for the CPU to write the TCNTs one after another or all at once. This is because there is no need to consider timing at all. The data once written to RAM 4a is applied to registers 31 and 32 based on successive control signal RDc. This successive control signal RDc may be the same as the first pulse of the data write signal DATWR to the registers 31 and 32. This will be discussed later.

The destination control data DATCIIT is shown in Figure 2 (C).
For the example, the first and second control data DCNT,.

It consists of DCNT2, and each is set as follows.

DCNT, ,=0, 0, 0DCNT2
"i '2' -3 Here, 0 indicates that the input data is not selected and output. On the other hand, 1 of DCNT2
．． 2.3 indicates that the data of time slots 1 and 2.3 of the first person's data signal are selectively output.

Therefore, in the example of FIG. 3(C), the control data DCNT
,, DCNT2 are set as follows.

[)Il'NT, =1.0.3 DCNT2=0.2,0 The number of bits of each control data is 3 (number of time slots is 5)
X2 (binary number 11 representing time slot S, however,
S=2'-1).

Registers 31 and 32 contain these control data DCNT, .
Input DCNT2. Therefore, - for boat fishing, selector 1
When the number of input data signals of a is m, m registers are provided in parallel. The number of bits in each register is (number of time slots in one frame s) x β, where S = 2'-
1. In this embodiment, s=3, so the number of bits in each register is 3×2=6 bits. RAM 4
Control data DCNTI and DCNT2 stored in RAiA4a are read from RAiA4a, and simultaneously transferred and stored in corresponding registers 31 and 32 by data write pulse DATwR, respectively. The successive control signal RDC of the RAM 4a is the first pulse of the data write pulse DATwn.

The timing control circuit 2a extracts each time slot in the timing control circuit 21. A time slot counter 221 counts the extracted time slot signals, and a selector 222 outputs a signal corresponding to the counted value.

Each register 31 and 32 receives a control data output signal CD0LIT corresponding to the time slot from the selector 222.
RO, RO9 are output to the selector 1a, respectively, based on the control data of the corresponding time slots 7).

For selector 1a, the contents of control data RO1 and RO2 are '0'.
”, the time slot data of the input data signal is not output, and if it is other than “0”, the time slot data of the corresponding input data signal is output.
Destination control is performed as shown in FIG. 2(f) or FIG. 3(f).

The above has described the case where m=2 among the cases in which m input data signals are used as one output data signal to control the destination of boat fishing. However, if two input data signals are used for destination control as one output data signal, the circuit shown in FIG. 5 may be used.

Since the circuit in FIG. 5 has two inputs, the selector 1b is
Since it is only necessary to select either one, the destination control data D
ATC) IT, in the case of FIG. 2(C), DATCIIT = ], 1.1, and in the case of FIG. 3(C), DATcM'r = 0 ' 1 ' 0. Here, "0" indicates that the first input data signal is selectively output, and "1" indicates that the second input data signal is selectively output. Destination control data DATCNT is 3 bits,
In other words, it is the length of the number of time slots.

The control register unit 3b consists of an OR gate 34 and one register 35. Register 35 is a shift type register and has a length of 3 bits. The register 35 is
The destination control data read from the RAM 4a is sequentially inputted using the data write pulse DATwR as a shift pulse.

The timing control circuit 2b counts the time slot signal extracted by the timing extraction circuit 21 with a 1-bit time slot counter 221' and outputs it as a control data output signal CDoua.

This control data output signal CD0UT is also connected to the OR gate 34.
as a shift pulse of register 35 through register 3
5. As a result, the destination control data DATC)IT is sequentially applied bit by bit from the register 35 to the selector 1b. Selector 1b receives input data signal D
Either one of the corresponding time slot data of Tr+ and DTI2 is selectively output.

The embodiments shown in FIGS. 4 and 5 show the case where the destination is controlled from the two-person data signal to the one-output data signal.
As shown in FIG. 7 and FIG.
The same holds true when controlling the destination of the output data signal. In this case, selectors lc and ld each have one input terminal,
It has two output terminals, and each outputs a single person data signal to the corresponding output terminal based on destination control data. The other circuits are the same as those in FIGS. 4 and 5.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to control the destination of communication data with accurate timing.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the communication data destination control method of the present invention, Fig. 2 (a) to (f), and Fig. 3 (a) to (f).
is an explanatory diagram of the operation of the communication data destination control method in Fig. 1, and Fig. 4
7 to 7 are circuit diagrams of a communication data destination control method according to an embodiment of the present invention, FIG. 8 is a circuit diagram of a conventional communication data destination control method, and FIGS. 9(a) to (d). (Explanation of symbols) 1... Selector, 2... Control register unit, 4... Buffer register unit 21... Timing extraction circuit, 22a, 22b-... Decoder, 31, 32 ...Register, 221...Time slot 222...Selector. is the operation explanatory diagram of FIG. 8, is the aiming control circuit, and g is the first principle block of the communication data destination control system of the present invention.
Times 1... 2... 3... 4... Selector timing control circuit controls Nostauninotobanofaresostauninot DT, ~DTIITl... Input data DT01~D
T□n” 'Output data FLY...Frame signal DATwRo...Data write signal DATCNT-°-Control data

Claims (1)

[Claims] 1. Input data signals (DT_I_1 to DT_I
__m) via a selector (1) based on destination control data (DAT_C_N_T), the communication data destination control method comprises a buffer register unit (4) that holds destination control data for each time slot; , the destination control data of all time slots held in the buffer register unit is sent to the data write signal (DAT_W_
A control register unit (
3) and a control data output signal (CD_O_U_T) synchronized with the frame of the input data signal and the time slot.
and a timing control circuit (2) that outputs the destination control data held in the control register unit is applied to the selector in response to a control data output signal synchronized with a time slot from the timing control circuit. , wherein the communication data destination is configured such that data in each time slot in the input data signal is destination controlled based on destination control data held in the control register unit applied to the selector. control method.