JP2825093B2 - Communication data destination control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a method for controlling the destination of communication data, it is possible to control the destination at an accurate timing and to control the destination for data of each time slot of each input signal. A communication data destination control method for controlling an input data signal having data allocated to a time slot in each frame via a selector based on destination control data. A buffer register unit for holding destination control data, a control register unit for simultaneously holding destination control data of all time slots held in the buffer register unit based on a data write signal, and a frame of the input data signal. And a timing system for outputting a control data output signal synchronized with the time slot. A destination control data held in the control register unit is applied to the selector in response to a control data output signal synchronized with a time slot from the timing control circuit, and each of the input data signals The time slot data is configured to be controlled based on the destination control data held in the control register unit applied to the selector.

[Industrial applications]

The present invention relates to a communication data destination control method in a communication system, and more particularly to a communication data destination control method for controlling the destination of data for each time slot at an accurate timing.

The communication data destination control method of the present invention is suitably used for destination control in a communication system that performs high-speed data transmission such as broadband ISDN.

[Conventional technology]

FIG. 8 shows two types of input signals D in the communication control device.
1 shows a circuit for controlling destinations of T _I1 and DTI ₂ via a selector 1. The input signals _DTI1 and _DTI2 are respectively shown in FIG.
As shown in (b), data is set in three time slots for each frame. As shown in FIGS. 9 (c) and 9 (d), the circuit shown in FIG. 8 includes a second input signal, a first input signal, and a second input signal as destination output data DT _OUT for each frame. A control register unit 3 'comprising registers 31' and 32 'for temporarily storing destination control data DTA _CT1 and DAT _CT2 , respectively, and outputting the output to selector 1 is provided.

As a result, the output data DT _OUT is output from the selector 1 based on the destination control data DAT _CT1 and DAT _CT2 .

If the output of destination control data DAT _CT1 and DAT _CT2 is performed for each time slot in each frame, the destination of the input signal can be controlled for each time slot.

[Problems to be solved by the invention]

Writing of destination control data to the control register unit is usually performed by a computer in the communication control device detecting the source and destination (destination) of the data. Other control processing is being performed.

In this case, if a timing difference occurs between the writing timing of the destination control data and the output timing from the control register unit and the application timing of the input signal to the selector 1, as shown in FIGS. , The second input signal at 2 ₁₁ , 2 ₁₂ , 2 ₁₃ ,
Input signals 2 ₂₁ , 2 ₂₂ , and 2 ₂₃ , and second input signals 2 ₃₁ , 2 ₃₂ , and 2 ₃₃ in frame 3 should be output, but in practice, 1 ₁₁ , 2 ₁₂ , and 2 _{13 in} frame 1 , so that 1 _31, 1 _32, 2 ₃₃ in 2 _21, 1 _22, 1 _23, frame 3 in the frame 2 is outputted.

In particular, when the input signal becomes faster, such as in a broadband ISDN, the timing difference between the timing of writing and outputting the destination control data and the timing of applying the input signal, that is, the timing of applying each frame signal of the input signal increases, and the accurate There is a problem that destination control becomes impossible.

In addition, in wideband ISDN, etc., it is required to control the destination of each slot data in a frame. In this case, the timing difference must not be present.
The circuit of FIG. 8 cannot fulfill such a demand.

In view of the above problems, an object of the present invention is to realize a communication data destination control method capable of accurately controlling destinations not only for each frame but also for each time slot.

[Means for solving the problem]

Communication data destination control method of the present invention, as shown the principle block diagram in FIG. 1, the input data signal DT _I1 to DT _Im
Selector 1 for selecting and outputting destination control data, buffer register unit 4 for temporarily storing destination control data DAT _CNT for each time slot, and data writing for destination control data DAT _CNT stored in the buffer register unit. It has a control register unit 3 that holds simultaneously based on the signal DAT _WR . Further, in the communication data destination control method of the present invention, the control data output signal CD _OUT synchronized with the time slot of the input data signal is output to the control register unit 3, and the control register unit 3 responds to the selector 1 in synchronization with the time slot. And a timing control circuit 2 for applying destination control data of a time slot to be executed.

FIG. 1 generally shows m-sequence input data signals DT _{I1 to} DT
_Im is input to the selector 1 and an n-series output data signal DT
_The case where destination control is performed as _{O1 to} DT _On is shown.
Circuit of FIG. 1, for example, when controlling the destination from the input data DT _I1 of 1-series as the output data signal DT _O1 to DT _On a plurality of sequences, conversely, from the input data DT _I1 to DT _Im a plurality of sequences 1
When controlling the destination as the output data signal DT _O1 series, and is applicable for any combination between them.

(Operation)

With reference to FIGS. 2A to 2F, a description will be given of a case where destination control is performed on data for each frame. For simplicity of explanation, two series of input data signals DT _I1 and DT _I2 are input to the selector 1, each of which has three slots of data in each frame. _The case where _OUT is one line will be described.

Destination control data DAT _CNT (FIG. 2 (c)) is applied to the buffer register unit 4 and held. Since the destination control data DAT _CNT is to instruct the destination control for each time slot, it consists of three data, indicated by each time slot of the respective second input data signals, 2 _1, 2 _2, 2 ₃ data It is. The destination control data DAT _CNT is intermittently stored in the buffer register unit 4 as shown by the solid line in FIG.
And may be continuously applied to the buffer register unit 4 as shown by a broken line. Destination control data DA once held in buffer register unit 4
T _CNT is the last one of the destination control data DAT _CNT the write is to the control register unit 3 collectively by the data write signal DAT _WR output after being held in the buffer register unit 4 (FIG. 2 (d )). On the other hand, the timing control circuit 2 applies the control data output signal CD _OUT synchronized with the time slot in the frame to the control register unit 3 based on the frame signal FLM (FIG. 2 (e)), and writes it in the control register unit 3. The inserted destination control data DAT _CNT is sequentially output to the selector 1 in correspondence with the time slot.

The control data output signal CD _OUT synchronized with the time slot is sequentially output from the timing control circuit 2 to the control register unit 3 (FIG. 2 (e)). The control data output signal causes the selector 1 to sequentially output the destination control data DAT _CNT set as shown in FIG. 2 (c). As a result, the input data signals DT _I1 and DT _I2 applied to the selector 1 in accordance with the timing of the seventh and subsequent control data output signals in FIG. _{2E and} the value of the destination control data DAT _CNT output at that time.
Are selected and output by the selector 1 and row-controlled. In this example, switching of all data of frame 3 from the first input data signal DAT _I1 to the second input data signal DAT _I2 (destination control) is performed.

The data write signal DAT _WR is preferably provided as a pulse signal in a frame before the frame in which the destination control is to be changed. Also, the control data output signal CD _OUT is preferably a pulse signal.

According to the above, the destination control data DAT _CNT is output. For example, the CPU can output the destination control data without considering the output timing of the destination control data DAT _CNT at all. In addition, even if the bit rate of the input data signal becomes high and the CPU cannot output the destination control data in synchronization with the frame or time slot as in the related art, the buffer register shown in FIG. By controlling the selector 1 in cooperation with the unit 4, the control register unit 3, and the timing control circuit 2, accurate destination control is possible.

Next, a case where destination control is performed on data for each time slot in one frame will be described with reference to FIGS. As described above, the communication data destination control method of FIG. 1 basically enables destination control for each time slot. Therefore, in this case, simply, as illustrated destination control data DAT _CNT in FIG. 3 _{(c), 1 1, 2} 2, 1 3 and set, by outputting a solid line or broken line of the timing, the third At the timing of the seventh and subsequent control data output signals CD _OUT shown in FIG.
AT _OUT, the first third frame of the input data signal DT third frame in the first time slot data 1 ₃₁ of the _I1, the second second in a time slot of the input data signal DT _I2 in the first time slot a second time slot data 2 ₃₂ of the first input data signal third frame in the third DT _I1 of time slot data 1 ₃₃ are output in the third time slot.

〔Example〕

FIG. 4 is a circuit diagram of a communication data destination control system according to an embodiment of the present invention.

In FIG. 4, the control register unit 3 of FIG. 1 is a control register unit 3a comprising two registers 31, 32.
The timing control circuit 2a is realized by the timing extraction circuit 21 and the decoder 22.
The decoder 22 includes a time slot counter 221 and a selector 222. The buffer register unit 4 in FIG. 1 corresponds to the RAM 4a, and the selector 1 in FIG. 1 is an equivalent selector 1a.

The embodiment of FIG. 4 shows first and second input data signals DT.
A case where one output data signal DT _OUT is output by controlling destinations of _I1 and DT _I2 is shown.

The number of memories of the RAM 4a is a capacity enough to store the destination control data. Destination control data is output from a CPU (not shown) or the like. Writing to RAM4a destination control data DAT _CNT is performed based on the write control signal WR _c from CPU. In this case, as shown in FIG. 2 (c) or FIG. 3 (c),
It is preferable for the CPU side to write the necessary destination control data DAT _CNT continuously or collectively.
This is because there is no need to consider timing at all. RAM4
Once the write data into a is applied to the register 31 based on the read control signal RD _c. The read control signal RD _c may the same as the first pulse of the data write signal DAT _WR to the register 31. This will be described later.

In the case of the example of FIG. 2 (c), the destination control data DAT _CNT includes first and second control data DCNT ₁ and DCNT ₂ , which are set as follows.

DCNT ₁ = 0,0,0 DCNT ₂ = 1,2,3 Here, 0 indicates that the input data is not selected and output. On the other hand, 1, ₂ , and 3 of DCNT ₂ indicate that the data of time slots 1, ₂ , and 3 of the first input data signal are selectively output.

Therefore, in the case of the example of FIG. 3 (c), the control data DCNT ₁ ,
DCNT ₂ is set as follows.

DCNT ₁ = 1,0,3 DCNT ₂ = 0,2,0 The number of bits of each control data is 3 (time slot number S)
× 2 (a binary number 1 representing a time slot S, where S =
2 ^l -1).

The registers 31 and 32 receive these control data DCNT ₁ and DCNT ₂ . Therefore, in general, when the number of input data signals of the selector 1a exceeds m, m registers are provided in parallel. The number of bits in each register is (the number of time slots in one frame S) × 1, where S = 2 ^l −1. In this embodiment, since S = 3, the number of bits of each register is 3 ×
2 = 6 bits. Control data DCN stored in RAM 4a
T ₁ and DCNT ₂ are read from the RAM 4a and are simultaneously transferred to and stored in the corresponding registers 31 and 32 by the data write pulse DAT _WR . Read control signal RD _c of RAM4a is the first pulse of the data write pulse DAT _WR.

The timing control circuit 2a extracts each time slot in the timing extraction circuit 21. The extracted time slot signal is counted by the time slot counter 221, and a signal corresponding to the counted value is output from the selector 222.

Each of the registers 31, 32 outputs the control data of the corresponding time slot, RO ₁ and RO _2, to the selector 1a based on the control data output signal CD _OUT corresponding to the time slot from the selector 222.

The selector 1a does not output the time slot data of the input data signal when the contents of the control data RO ₁ and RO ₂ are “0”, and outputs the time slot data of the corresponding input data signal when the content is not “0”. I do. Thus, FIG. 2 (f)
Alternatively, destination control is performed as shown in FIG.

The foregoing has generally described the case where m = 2 in the case where destination control is performed with m input data signals as one output data signal. However, if two input data signals are input, 1
When destination control is performed as one output data signal, the circuit shown in FIG. 5 may be used.

Since the circuit of FIG. 5 has two inputs, the selector 1b
Since either one may be selected, the destination control data DA
As the T _CNT , DAT _CNT = 1,1,1 in the case of FIG. 2 (c), and DAT _CNT = 0,1,0 in the case of FIG. 3 (c). Here, "0" indicates that the first input data signal is selectively output, and "1" indicates that the second input data signal is selectively output. Destination control data DAT _CNT is 3 bits,
That is, the length is the number of time slots.

The control register unit 3b includes an OR gate 34 and one register 35. The register 35 is a shift type register and has a 3-bit length. The register 35 sequentially inputs the destination control data read from the RAM 4a using the data write pulse DAT _WR as a shift pulse.

The timing control circuit 2b counts the time slot signal extracted by the timing extraction circuit 21 with a 1-bit time slot counter 221 ', and outputs a control data output signal CD
Output as _OUT .

This control data output signal CD _OUT is also applied to the register 35 as a shift pulse of the register 35 via the OR gate 34. Thereby, from the register 35, one bit at a time,
Destination control data DAT _CNT is applied to selector 1b. Selector 1b selects outputs any of the corresponding time slot data of the input data signal DT _I1, DT _I2.

4 and 5 show the case where the destination control is performed from two input data signals to one output data signal. However, as shown in FIGS. 6 and 7, two output signals from one input data signal are output. The same applies to the case where destination control is performed on a data signal. In this case, each of the selectors 1c and 1d has one input terminal and two output terminals, and outputs one input data signal to the corresponding output terminal based on the destination control data. Other circuits are the same as those shown in FIGS.

〔The invention's effect〕

As described above, according to the present invention, it is possible to control the destination of communication data at accurate timing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of a communication data destination control method according to the present invention. FIGS. 2 (a) to (f) and FIGS. 3 (a) to (f) show the communication data destination control method of FIG. 4 to 7 are circuit diagrams of a communication data destination control method according to an embodiment of the present invention, FIG. 8 is a circuit diagram of a conventional communication data destination control method, and FIGS. 9 (a) to (a). d) is an explanatory diagram of the operation in FIG. (Explanation of symbols) 1 ... selector 2 ... timing control circuit 3 ... control register unit 4 ... buffer register unit 21 ... timing extraction circuit 22a, 22b ... decoder 31,31 Register, 221 ... Time slot counter, 222 ... Selector.

Continuing from the front page (72) Inventor Kazuo Iguchi 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Tetsuo Soejima 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) Reference Document JP-A-61-189098 (JP, A) JP-A-55-50799 (JP, A) JP-A-59-39192 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 12/50

Claims (1)

(57) [Claims] 1. An input data signal having data allocated to a time slot in each frame (DT _{I1 to} DT _Im ).
Based on the destination control data (DAT _CNT )
And a destination register control system for controlling destinations via a buffer register unit (4) for holding destination control data for each time slot, and destination control data for all time slots held in the buffer register unit. A control register unit (3) for simultaneously holding based on a data write signal (DAT _WR ); and a timing control for outputting a control data output signal (CD _OUT ) synchronized with the frame of the input data signal and the time slot. Wherein the destination control data held in the control register unit is applied to the selector in response to a control data output signal synchronized with a time slot from the timing control circuit, and the input data signal The data of each time slot in the control register unit applied to the selector Characterized by being configured to be controlled destination based on the lifting has been destination control data, communication data destination control method.