JPH03181298A - Time division exchange - Google Patents

Abstract

PURPOSE:To ensure a time sequence in time division exchange by providing a one-frame delay section, a delay speech memory and an output highway selection section. CONSTITUTION:Time division information not delayed from a speech memory 12 and time division information delayed by one frame at a one-frame delay section 18 from a delay speech memory 19 are inputted simultaneously to an output highway selection section 20. The output highway selection section 20 uses a normal/delay switching signal so as to allow time division information exchange to delay time division information of an output time slot number n2 by one-frame and the result is outputted to an output highway 16 thereby enabling exchange securing time sequence. Thus, the time division signal delayed by one frame and the time division signal without delay are outputted selectively to attain time division exchange while securing time sequence.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a time division exchange system for exchanging time division information such as voice or data between terminals used in digital electronic exchanges, digital key telephone main units, etc. Regarding equipment.

BACKGROUND OF THE INVENTION FIG. 4 shows the configuration of a time division switching device used in a conventional digital electronic exchange or the like.

In FIG. 4, 1 is an input highway, and time-sharing information transmitted through input highway 1 is addressed using its highway number (physical location) and time slot number (temporal location). , call memory 2
accumulated within. 3 is "2f, % IJ? Yes, digital 27. Telephone exchange, etc. Exchange connection information from the main control circuit 4 that controls the overall call processing of the entire device is stored through the external interface section 5. Exchange connection The information instructs which time slot number of which highway number of the output highway 6 the time division information stored in the call memory 2 is to be outputted to.Based on this exchange connection information, a specific output timing is determined. As a result, the time-sharing information stored in the call memory 2 is output to the output highway 6. 7 is the input highway 1 and the output highway 6.
This is a clock◆frame signal generation unit that synchronizes the above time division information as well as the holding memory 3 and the call memory 2.

Next, the operation of the above conventional example will be explained. As shown in FIG. 5, the time division information on the input highway 1 includes each time slot number T S 1 of the input highway number 1,
On T S 2 , T S 3 ・= T S n,
Time division data AO, BO, Co-20 and each time slot TSI, TS2, TS3- of input highway number 2
Time division data Al, B1, C1...zl on TSn
Suppose that each exists. This time-sharing data AO,
BO, Co...20SAl.

81, CI...zl, as shown in FIG. 6, is generated by the clock frame signal generation unit 7 in the call memory 2 where the lower part of the address corresponds to the highway number and the upper part to the time slot number. It is accumulated sequentially in synchronization with the input timing.

Now, as shown in FIG. 7, the lower part of the address corresponds to the output highway number, and the upper part corresponds to the time slot number. Assume that a number has been written. Now, when the output highway number (lower) and time slot number (upper) are output as read addresses to the holding memory 3 according to the output timing from the clock frame signal generation section 7, the pulley stored in the holding memory 3 As shown in FIG. 5, the stored time-sharing information is in a different order than on input highway 1, namely BO, Bl, Al...
・Output to output highway 6 at Dl, AO, CI, EO...CO.

In this way, even in the conventional time division switching device described above, the main control circuit 4 rewrites the stored data (input highway number, time slot number) in the holding memory 3 through the external interface unit 5 based on call control information from the terminal. From this point, time-sharing information can be freely exchanged.

Problems to be Solved by the Invention However, in the conventional time division switching device described above, time division information (ISD) that has meaning across multiple time slots is
There is a problem in that when exchanging HO channels (N HO channels, etc.), time ordering cannot be ensured. This will be explained using FIGS. 8 and 9. FIG. 8 shows a case where the time order of the time division information is ensured, and FIG. 9 shows a case where the time order is not ensured. In FIGS. 8 and 9, the input highway time slot) no,
It is assumed that the time-sharing information Al and A2 on nt are meaningful data together within the same frame (time). As shown in FIG. 8, the order relationship of the time slots of the input highway and the output highway is no<7112. nl<
In the case of 778, time ordering is ensured. However, as shown in FIG. 9, the order relationship of the time slots is n
o < 77g, /71> /) In the case of II, since the data of A2 is 77t>72a, the output timing (read timing of the call memory) of time slot n3 of the output highway is the same as the time slot n of the input highway.
Since the input timing (timing for writing into the call memory) is earlier than the input timing of 1 (the writing timing of the call memory), the time-sharing information A2 in the same frame cannot be exchanged, and the time-sharing information A2-1 in the previous frame cannot be exchanged.
are exchanged and output, making it impossible to ensure time order.

The present invention is intended to solve such conventional problems, and aims to provide an excellent time division exchange device that can ensure time order in time division exchange.

Means for Solving the Problems In order to achieve the above-mentioned object, the present invention includes a one-frame delay section and a delayed speech memory that stores time-sharing information delayed by one frame in parallel to the line leading from the input highway to the speech memory. In addition, a normal/delay switching flag is provided in the holding memory to determine the necessity of ensuring time order, and an output highway selection section is provided between the call memory and delayed call memory and the output highway. The normal and one-frame delayed time-sharing information output from the delayed call memory are selected by the output highway selection section using a signal based on the normal/delay switching flag in the holding memory and output to the output highway. be.

Effects The present invention has the following effects due to the above structure. That is, in parallel to the line from the input highway to the call memory in the time division switching device, there is provided a one-frame delay section and a delay call memory connected in series thereto for storing time-sharing information delayed by one frame. Therefore, when time-sharing information cannot be exchanged within the same frame, that is, when multiple pieces of time-sharing information that have been exchanged cannot ensure continuity in the same frame, the previously exchanged time-sharing information is delayed by one frame. It can be time-divided and temporarily stored. In addition, by providing an output highway selection section between the call memory and delayed call memory and the output highway, normal time-sharing information from the call memory and time-sharing information delayed by one frame from the delayed call memory are selected. In this way, time-sharing information can be output to the output highway while ensuring time order.

The switching signal of the output highway selection section is generated based on the normal/delay switching flag provided in the holding memory. The normal/delay switching signal based on this flag is output from the holding memory to the output highway selection section in synchronization with the timing of reading data from the holding memory (timing of outputting the read address to the call memory).

Embodiment FIG. 1 is a schematic block diagram showing the configuration of an embodiment of the present invention. In Figure 1, 11 is an input highway;
Reference numeral 2 denotes a call memory that temporarily stores time-sharing information sent from the input highway 11 for exchange connection, and 13 stores exchange connection information that changes the order of the time-share information stored in the call memory 12. It is a holding memory and has a normal/delay switching flag in the memory. 14 is a main control circuit for controlling the exchange of time-sharing information; 15 is an external interface unit for transmitting exchange connection information from the main control circuit 14 to the holding memory 14; 16 is an output highway; 17
is the time-sharing information on the input highway 11 and the output highway 16, as well as the holding memory 13 and the call memory 1.
This is a clock frame signal generation unit that provides synchronization to the clock frame signal generator 2. Reference numeral 18 denotes a one-frame delay unit that delays the time-sharing information on the input highway 11 by one frame. 19 is the input highway number (physical location) like the call memory 12
and a time slot number (temporal position) as an address, and is a delay call memory that stores time-sharing information outputted from the one frame delay unit 18 and delayed by one frame. Reference numeral 20 denotes an output highway selection section, which selects the respective time-sharing information simultaneously output from the call memory 12 and the delayed call memory 19 at the output timing based on the normal/delay switching signal 21 and outputs the selected information to the output highway 16. It is a part. The normal/delay switching signal 21 is a signal created based on the normal/delay switching flag provided in the holding memory 13.

Next, in the operation of the above embodiment, a process in which time-sharing information is exchanged while ensuring time order will be described. The exchange connection information written from the main control unit 14 to the holding memory 13 using the output highway number and time slot number as addresses includes the normal/delay switching flag in addition to the input highway number and time slot number, as shown in FIG. shall have. The normal/delay switching flag is output from the holding memory 13 at the time of outputting the time division information, and a normal/delay switching signal is generated. It is indicated by a source of ordinal information, such as that the input timeslot value is greater than the output timeslot value.

At the output timing, normal time-sharing information that is not delayed from the call memory 12 and 1 from the delayed call memory 19 are output.
The time-sharing information delayed by one frame by the frame delay unit 18 is simultaneously input to the output highway selection unit 20. In the output highway selection unit 20, the normal/delay switching signal causes the exchange of time-sharing information, for which time ordering cannot be ensured in the conventional example shown in FIG. 9, to be performed at the output time slot number n2, as shown in FIG. By delaying the division information by one frame and outputting it to the output highway 16, exchange can be performed while ensuring time order. That is, the ninth
In the conventional example shown in the figure, since the output time slot number n3 is smaller than the input time slot number n1, the time division information A2-1 of -1 in the previous frame is the time division information of the current frame. By entering the information after the information A1, the time order is disrupted, but in this embodiment, the time-sharing information A1-1 of -1 is also entered in the previous frame, which is the same as A2-1, in the current frame. Time order is ensured by capturing the data into frames. As a result, both Al and A2 on the communication memory are sent to the next frame, so that in the next ◆1 frame, A1 and A2 are output while maintaining their temporal order.

According to the embodiment described above, the time-sharing information exchanged in advance in time is delayed by one frame by the one-frame delay unit 18 and stored in the delayed call memory 19.
In response to the normal/delay switching signal from the holding memory 14, the output highway selection unit 20 selects the undelayed time division information and the delayed time division information, and outputs the output highway 1.
6, it is possible to output a plurality of pieces of time-sharing information while ensuring time order.

Effects of the Invention As is clear from the embodiments described above, the present invention provides a one-frame delay section, a delay call memory, and an output highway selection section in the time division switching device, and also solves the need to ensure time order in the holding memory. A normal/delayed switching flag is provided for determining the normal/delayed switching flag, and the output highway selection section selects between time-sharing information delayed by one frame and time-sharing information without delay based on the signal based on this normal/delayed switching flag. By outputting the information, it is possible to exchange time-sharing information that requires time-ordering while ensuring time-ordering.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a time division exchange device according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a holding memory in the same device, and FIG. 4 is a schematic block diagram of a conventional time division switching device, and FIG. 5 is a diagram showing time division data of the same device,
FIG. 6 is a diagram showing the configuration of the call memory in the same device, FIG. 7 is a diagram showing the configuration of the holding memory in the same device, and FIG. 8 is a diagram showing the configuration of the holding memory in the same device.
This figure shows a mode of time-sharing data exchange in the same device, and FIG. 9 is a diagram showing another mode of time-sharing data exchange in the same device. 11... Input highway, 12... Call memory, 1
3... Holding memory, 14... Main control circuit, 15...
- External interface section, 16... output highway,
17... Clock/frame signal generation section, 18...
1 frame delay section, 19...delay call memory, 20.
. . . Output highway selection section, 21 . . . Normal/delay switching signal.

Claims (1)

[Claims] A communication memory provided between the input highway and the holding memory, a normal/delay switching flag provided in the holding memory for determining the necessity of ensuring time order, and between the input highway and the holding memory. A one-frame delay unit and a delayed call memory are provided in series in the memory, and normal and one-frame delayed time division information are inputted from the call memory and the delayed call memory, and these time division information are transferred to the normal time division information in the holding memory. /A time division switching device comprising: an output highway selection unit that selects a signal based on a delay switching flag and outputs the selected output highway to the output highway;