JPS6157137A - Signal processor - Google Patents

Abstract

PURPOSE:to read a desired time division frame among stored signals by applying independently write of a signal possible for change in the unit of time division frame and read of the stored signal. CONSTITUTION:A counter circuit 1 is initialized by a multi-frame time division frame time division frame synchronizing signal MFS, counts a time division frame synchronizing signal FS to form write address information ADdelta1 of storage circutis 7, 8 storing a signal DA1 changing it in the unit of time division frame by storage circuits 7, 8. the count circuit 2 is initialized by the control signal CT1 from the output side B, counts the control signal CT2 to form read address information AD2 of the circuits 7, 8. A selection signal SL from an FF5 using the signal MFS as a toggle signal repeats 1, 0 at each multiple time division frame. When the level of the signal SL is logical 1, a selection circuit 3 selects the information AD1, the circuit 7 writes the signal DA1, the selection circuit 4 selects the information AD2, the circuit 8 is brought into the read state and the signal DA2 is outputted to the B side. When the signal SL is logical 0, the circuit 7 is in read state and the circuit 8 is in the write state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to pulse code modulated time division multiple access (PCM-T
The present invention relates to a signal processing device suitable for a (DMA) communication device. In particular, the present invention relates to a signal processing device for use in a circuit that operates in a plurality of time-division frame periods of a signal that is output from a circuit that operates in a time-division frame period and that can change in time-division frame units.

[Conventional technology]

FIG. 2 is a configuration diagram of a multiple access time division frame. Second
In the pulse code modulation time-division multiple access communication system that performs communication using a group of time-division frames configured as shown in the figure, the equipment for this communication system includes a circuit that operates in cycles of time-division frames and a multi-channel There is a circuit that operates on a cycle of divided frames (a plurality of time-divided frames), which establishes the operation of this device as a whole.

The signal DA outputted from the circuit operating on a time-division frame basis as described above is a signal that can be changed in units of time-division frames. The above signal DA.

When used in circuit B that operates in cycles of multiple time division frames, circuit B inputs the above signal DAB asynchronously to the operation of circuit A at a desired timing within one multiple time division frame. there's a possibility that. Of the signals DAI that are required in circuit B in real time, the latest signals need to be input at the required timing. However, if the signal OA+ is required as a signal in units of one multi-time division frame in circuit B, a signal that can be changed in units of time division frames is accumulated for one multi-time division frame, and the circuit It is necessary to input all the signals for one multi-time division frame or the signals in a desired time-division frame in one multi-time division frame at the timing required in B.

Conventionally, as a method for connecting signals between circuit A and circuit B as described above, FI F O (first in f
irstout) Prepare the required number of stages of buffer circuits such as memories, and write and accumulate the signal OA, which can be changed in time-division frame units, in the buffer circuits using the activation signal of the time-division frame. When necessary, a means is used to read out and utilize the accumulated signals from the buffer circuit at a timing independent of the write timing.

[Problem that the invention seeks to solve]

However, when a buffer circuit such as a FIFO memory as described above is used, the stored signals are always read out from the buffer circuit in the order in which the signals are input into the buffer circuit, and the signals are stored in the desired order. It is not possible to read out the signal that has been detected. For example, even if only the signal in the last time-division frame in one multi-time division frame is required, it is necessary to read out all the signals written before the writing of the required signal in the buffer circuit. There is a drawback that only signals in a desired time-division frame cannot be read out. In addition, a signal once read out from a buffer circuit such as a FIFO memory does not exist in the buffer circuit after being read out, and if there is a possibility that this signal is needed even after being read out, this buffer circuit There were also drawbacks, such as the need to write this signal in a memory other than the conventional one.

The present invention improves the above-mentioned drawbacks by making it possible to read only the signal in a desired time-division frame within the signals accumulated for one multi-time division frame, and until the next signal is written. It is an object of the present invention to provide a signal processing device that can hold this accumulated signal.

[Means for solving problems]

The present invention provides a means for inputting a signal arriving in time series from an input side circuit in time-division frame units, and a means for inputting a signal arriving in time-series in units of time-division frames, and a means for inputting the signal by n times the time-division frame (n is the number of time-division frames constituting one multiframe). ) during pulse code modulation, comprising a memory means for temporarily holding information of the above frames, and means for transmitting the information read from the memory means to an output side circuit in a multi-frame configuration including n time-division frames. In a signal processing device for a division multiple access communication device, the memory means includes two storage circuits each capable of temporarily holding information of frames n times as many as the time division frame, and each of the storage circuits a selection circuit whose output is connected to an address input terminal; and first and second counting circuits each connected to two input terminals of the selection circuit and generating an address signal for the storage circuit; The counting circuit is configured to be initialized every n time division frame periods of the signal arriving from the input side circuit and count the time division frames, and the second counting circuit is configured to count the time division frames of the signal arriving from the output side circuit. initialized by the incoming first control signal and configured to count the same (second control signal coming from the output side circuit); At every frame period, the above two memory circuits are controlled to be in the write state and the read state alternately, and the parallel output of the above first counting circuit is connected to the address input of the memory circuit in the four-way state, and the read state is controlled. The present invention is characterized by comprising means for controlling the selection circuit so as to connect the parallel output of the second counting circuit to the address input of the storage circuit located at point !.

[For production]

In the present invention, address information for G is created in a first counting circuit that is initialized every n time-division frame periods of a signal arriving from an input side circuit and counts the time-division frames, and the output side circuit Address information for reading is created by a second counting circuit which is initialized by a first control signal arriving from the output side circuit and counts a second control signal also arriving from the output side circuit. The control means controls the two memory circuits so that they are alternately in the write state and the read state every n time-division frame periods, and the memory circuit in the write state is controlled by the first counting circuit. By controlling the selection circuit so that write address information is input to the memory circuit in the read state, and read address information is input to the memory circuit in the read state, data is read from the input side circuit in time-series in time-division frame units. A signal composed of a desired time-division frame can be outputted at a desired timing from an incoming signal to an output-side circuit that operates in n time-division frame periods.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a signal processing device according to an embodiment of the present invention. In FIG. 1, a time-division frame synchronization signal FS and a multi-time division frame synchronization signal MFS from a frame synchronization signal generation circuit (not shown) are connected to a clock input and a clear input of a counting circuit 1, respectively. Control signals CT, CTZ from an output side circuit B (not shown) are connected to the clear input and clock input of the counting circuit 2, respectively. The output address information flap of the counting circuit 1 is the selection circuit 3.4
The input r.

The output address information ADZ of the counting circuit 2 is connected to the input I2 of the selection circuit 3.4. The multi-time division frame synchronization signal MPS is branched off and connected to the toggle signal input T of the toggle flip-flop 5. The selection signal SL from the output Q of the toggle flip-flop 5 is connected to the selection input of the selection circuit 3, and the selection circuit 3 selects one of the address information ADI, ADZ and sets the address of the storage circuit 7 as the address information ADz. Connected to input. Further, the selection signal SL is connected to the selection input of the selection circuit 4 via the inversion circuit 6, and the selection circuit 4 selects one of the address information AD, , ADZ and sets the address of the storage circuit 8 as the address information AD 4 . Connected to input. The time-division frame synchronization signal FS is branched and connected to the input of the switching circuit 10 via the inversion circuit 9, and the control signal SL is connected to the select input.

The timing signal TM from the output 01 of the switching circuit 10 is connected to the write 1-inhibit input of the storage circuit 7, and the switching circuit 10
The timing signal needle 2 is connected from the output 02 of the memory circuit 8 to the write inhibit input of the memory circuit 8. A timing signal RO from a circuit B (not shown) is connected to the input of the switching circuit 11, and a selection signal S
is connected to the select input.

The timing signal TM from the output O1 of the switching circuit 11 is connected to the read inhibit input of the storage circuit 8, and the timing signal TM4 from the output 02 of the switching circuit 11 is connected to the read inhibit input of the storage circuit 8. a circuit 7
Connected to read inhibit input. Input side circuit A not shown
The signal DAI from the 3-state buffer circuit 12.13
are connected to the inputs of each. The selection signal SL is connected to the output control input of the 3-step buffer circuit 12, and the output of the 3-step buffer circuit 12 is connected to the data input/output of the memory circuit 7. The selection signal SL is connected to the output control input of the three-state buffer circuit 13 via the inverting circuit 14, and the output of the three-state buffer circuit 13 is connected to the data input/output of the memory circuit 8. The data input and output of the storage circuit 7.8 are also connected to the inputs t+ and rz of the selection circuit 15, respectively. The selection signal SL is connected to the selection input of the selection circuit 15, and the output signal D/h of the selection circuit 15 is connected to a circuit B (not shown).

The operation of the signal processing device having such a configuration will be explained. Counting circuit 1 receives multi-time division frame synchronization signal MFS.
The memory circuit 7 is initialized by , executes counting using the time-division frame synchronization signal FS as a clock source, and stores the signal in the write state.
．． Address information atO for 8 is created. The counting circuit 2 is initialized by a stop signal CT from a circuit B which operates in a multi-time division frame period (not shown). This circuit B is a signal DA output by this signal processing device.
This is a circuit that uses Z for processing. Counting circuit 2 receives control signal CT.

Counting is performed using Ant as a clock source, and address information Ant for the storage circuit 7.8 of the read state of the accumulated signals.
Create. The selection circuit 3.4 selects the address information 〇, , ADz from the counting circuit 1.2, and writes the corresponding address information to the corresponding memory circuit 7.8 depending on whether it is in the write state or the read state. Into:+,
An is selected and supplied.

The selection information SL is a multi-time division frame synchronization signal MFS.
is output from the toggle flip-flop 5 which uses the toggle signal as a toggle signal, and repeats "1" and "0" for each multi-time division frame. Therefore, when the selection information SL is rlJ, the selection circuit 3 selectively outputs the address information ADI,
On the other hand, selection circuit 4 selects! Address information ADZ is selectively output using a signal obtained by inverting selection information SL. The memory circuit 7.8 stores a signal OA that can be changed in units of one time-division frame.
, can be stored for one multi-time division frame. The two memory circuits 7 and 8 alternately apply and read the signal DAI every multi-segmentation frame.

For example, in a desired multi-time division frame, when the memory circuit 7 is in the writing state of the signal DA+, the memory circuit 8 is in the state where the already written signal is being read. ” The switching circuit 10 is for switching the supply destination (memory circuit 7 or 8) of the write timing of the signal DA to the memory circuit 7.8. The switching circuit 11 supplies the write timing signal TM of D^1 and does not supply this write timing signal TM to the memory circuit in the read state.
This is for switching the supply destination of the read timing signal RD of the accumulated signal from the memory circuit 7.8, and supplies the read timing signal Iura of the accumulated signal to the memory circuit in the read state, This read timing signal RD is not supplied to the memory circuit in the write state.

The three-state buffer circuits 12 and 13 are buffer circuits for the write signal DAI for the memory circuit 7 and the memory circuit 8, respectively, and can set the output to a high impedance state depending on the state of the output control terminal. That is, when the memory circuit 7.8 is in the write state, the input signal OA
, is outputted as is, and when it is in the read state, it is brought into the output livestock impedance state and the connection with the memory circuit 7.8 is equivalently disconnected.

The selection circuit 15 is for selectively outputting the output signal from the storage circuit 7.8 in the read state.

The case where the selection signal SL output from the toggle flip-flop 5 is "1" will be explained. In FIG. 1, each selection circuit 3.4.15 selectively inputs the input 11 when the selection signal SL is "1", and inputs the input 11 when the selection signal SL is "1".
2 shall be selected and input.

Furthermore, in each switching circuit 10.11, when the selection signal SL is "1", the input signal is output from the output 01, the output 02 holds rlJ, and this selection signal SL is "0". In this case, the input signal is output from output 02, and output 01 holds "1".

In addition, in each 3-step buffer circuit 12.13,
When the selection signal SL, which is an output control signal, is "1", the input signal is output, and when the selection signal SL is "0", a high impedance state is output.

When the selection signal SL is rlJ, the memory circuit 7 is in the write state and the memory circuit 8 is in the read state.

In the storage circuit 7, the multi-time division frame synchronization signal MFS
The signal DA is written at the timing of the write timing signal TM into the area addressed by the address information ADl initialized by the time-division frame synchronization signal FS and updated by the time-division frame synchronization signal FS. While the selection signal SL is "1", the memory circuit 7 repeats writing of the signal DA+ as described above for each time division frame. On the other hand, in the memory circuit 8, the control signal C
At the timing of the read timing signal T gate 3, the accumulated signal is read out from the area addressed by the address information DAZ initialized by the control signal CT2 and updated by the control signal CT2 and outputted to the outside. Here, since the output of the three-state buffer circuit 13 is in a high impedance state, the signal output from the memory circuit 8 is added to the input I+ of the selection circuit 14 and selectively output.

When the selection signal SL is "0", the memory circuit 7 is in a read state and the memory circuit 8 is in a write state, which is the opposite state to that when the selection signal SL is "1", and the respective operations are executed. . As mentioned above, two states B (selection signal SL
``1'' state and ``0'' state) are alternately executed for each multi-time division frame.

With the operation described above, the writing operation of a signal that can be changed in units of time-division frames and the operation of successively writing accumulated signals can be executed independently, and the desired signal can be written out of the accumulated signals of one multi-time division frame. It is possible to read out the time-division frame signal of 1, and it is also possible to read out the same information any number of times as long as it is in the continuous output state.

〔Effect of the invention〕

As explained above, the present invention has the excellent effect of being able to input signals at a desired location at a desired timing even if the signals are from circuits that operate at different cycles. Therefore, when applied to a pulse code modulation time division multiple access communication device, a signal at a desired time position can be extracted, and this signal can be repeatedly read out, which is an extremely excellent effect. In addition, if a microprocessor is used in the circuit that uses the output signal, this circuit can be directly connected to the address bus and data bus of the microprocessor, so this signal processing device can be It has the advantage that it can be treated as an additional circuit in the same way as normal memory in a processor.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a signal processing device according to an embodiment of the present invention. FIG. 2 is a configuration diagram of a multiple access time division frame. 1.2... Counting circuit, 3.4.15... Selection circuit,
5...Toggle flip-flop, 6.9.14...
・Inversion circuit, 7.8...Memory circuit, 10.1...
Switching circuit, 12.13...3-step buffer circuit,
AD...address information, BCT...burst signal,
CT...control signal, DA...signal, FS...time division frame synchronization signal, MFS...multiple time division frame synchronization signal, I? D...Read timing signal, SL
... selection signal, TM, , TM2 ... write timing signal, TMz, TM4 ... read timing signal.

Claims (1)

[Claims] (1) A means for inputting signals that arrive in time series from an input side circuit in time-division frame units, and multiplying the signal by n times the time-division frame (n is the number of time-division frames constituting one multiframe) Pulse code modulation time division comprising memory means for temporarily holding the information of the above frames, and means for sending out the information read from the memory means to the output side circuit in a multi-frame configuration including n time division frames. In the signal processing device of the multiple access communication device, the memory means includes two memory circuits each capable of temporarily holding information of frames n times as many as the time division frame, and an address input of each of the memory circuits. The first counting circuit comprises a selection circuit whose output is connected to a terminal, and first and second counting circuits each connected to two input terminals of the selection circuit and generating an address signal for the storage circuit. is initialized every n time-division frame periods of the signal arriving from the input circuit and is configured to count the time-division frames, and the second counting circuit is configured to count the time-division frames of the signal arriving from the output circuit. It is configured to count a second control signal that is initialized by the first control signal and also arrives from the output side circuit; Then, the above two memory circuits are controlled to be in a write state and a read state alternately, and the parallel output of the above first counting circuit is connected to the address input of the memory circuit in the write state, and the memory circuit in the read state is controlled. A signal processing device for a pulse code modulation time division multiple access communication device, comprising means for controlling the selection circuit so as to connect the parallel output of the second counting circuit to the address input of the pulse code modulation time division multiple access communication device.