JPH02312328A - Data branching circuit - Google Patents

Abstract

PURPOSE:To constitute random bit arrangement independently of periodicity and continuity of bits to improve the efficiency of data multiplexing by providing a double buffer memory to arbitrarily set the read address of a control circuit. CONSTITUTION:The data branching circuit consists of a serial/parallel converting circuit (S/P circuit) 11, a latch circuit 12, a parallel/serial converting circuit (P/S circuit) 13, buffer memory circuits 14 and 15, and a control circuit 16. Read/write to double buffer memory circuits 14 and 15 are alternately and periodically performed; and at the time of read, the control circuit 16 reads out serial data at random in accordance with a prescribed read address and outputs prescribed bits and branches prescribed data. Thus, data (bits) on serial data are branched at random to improve the efficiency of data multiplexing.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a branching circuit for branching multiplexed serial data, and more particularly to a branching circuit for branching serial data in a predetermined or random manner. .

[Conventional technology]

Conventionally, in a branch circuit for branching multiplexed serial data, when branching a predetermined bit on the serial data, a timing signal for latching a predetermined bit on the serial data is generated and the timing signal is Based on this, data is held, and then this held data is branched.

[Problem to be solved by the invention] By the way, in the case of the above-mentioned branch circuit, the timing signal is required to have periodicity for the data to be branched, and as a result, the data (bits on the serial data) are completely periodic. It is not possible to randomly branch data (bits) on serial data. Therefore, data multiplexing efficiency cannot be improved.

An object of the present invention is to provide a branching circuit that can randomly branch all data on serial data.

[Means to solve all problems]

According to the present invention, multiple pieces of data are multiplexed.

In a data branch circuit for branching predetermined data from serially transmitted multiplex data.

Serial converting the multiplexed data into parallel data.
A parallel conversion circuit, a latch circuit that periodically selects a predetermined L bit (an integer of L≧1) from the parallel data, and a parallel-serial conversion that converts the latched L bit data into serial data. A double buffer 1 memory circuit in which the serial data is written sequentially, and a control circuit that controls reading of the double buffer memory circuit.

The double buffer 1 memory circuit is alternately written and read at a predetermined period, and during the read, the control circuit randomly reads the serial data according to a predetermined read address and outputs a predetermined bit'. Thus, a data branching circuit is obtained, which is characterized in that it branches predetermined data.

〔Example〕

Next, the present invention will be explained with reference to examples.

As shown in Fig. 2, rLJ (an integer with L≧1) bits is taken as one unit (one time slot), and the bit stream obtained by collecting this time slot 'trMJ (an integer with M≧2) time slots is treated as one frame of data. A frame is constructed, and one multiframe is constructed by collecting N (an integer of N22) data frames.

Here, referring to FIG. 1, serial data 51Vi serial/parallel conversion circuit (S
/P circuit) 11 converts it into a parallel state every time slot, and provides it to the latch circuit 12. The latch circuit 12 latches predetermined L bits (that is, predetermined time slots) from these parallel data for each frame. In other words, the latch period of the launch circuit 12 is N
If all frames are collected, the configuration shown in Figure 3 will occur once per frame, and as a result, the latch circuit 1
2 outputs the data shown in FIG. 5 for N frames in parallel.

The above latched parallel data is transferred to the parallel to serial conversion circuit (p
/s circuit) 13 converts the data into serial again. As a result, serial data of L×N) bits for N frames is obtained.

buffer memory circuits 14 and 15 (buffer memory circuits 14 and 15 are collectively referred to as double buffer memory circuits 14 and 15).
J circuit toiu).

When serial data is written into the buffer memory circuits 14 and 15, it is sequentially written into the back 1 memory circuits 14 and 15 according to the sequential address.

Writing and reading are performed alternately in these buffer memory circuits 14 and 15 in accordance with the multi-frame period.

On the other hand, read control of the buffer 1 memory circuits 14 and 15 is performed by a control circuit 16.

The control circuit 16 specifies, for example, a sequential address when writing branch data bits indicated by zZ marks in FIG. 3. As a result, data in the buffer memory circuits 14 and 15 is read out alternately in a multi-frame period. That is, by changing the read address of the control circuit 16 using the clock on the 1-branch output side, data S2 is branched in units of bits corresponding to an arbitrary speed (clock) from the multiplexed serial data.

Souichi (Effects of the Invention) As explained above, in the present invention, by providing one double buffer memory and arbitrarily setting the read address of the control circuit, it is possible to limit the periodicity to continuity of bits. As a result, a random bit arrangement can be configured without
This has the effect of increasing data multiplexing efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data branching circuit according to the present invention, FIG. 2 is a block diagram showing an example of the structure of a frame, and FIG.
The figure shows an example of the configuration of a bitmap. 11...Serial-parallel switching circuit (S/P circuit)
, 12... Latch circuit, 16... Parallel-serial exchange circuit (P/S circuit), 14... Buffer memory circuit, 15... Backer memory circuit, 16... (Read) control circuit, sl...multiplexed serial data input, s2...output data. Figure 1

Claims (1)

[Claims] 1. In a data branching circuit for branching predetermined data from multiplexed data that is multiplexed and transmitted serially, a serial-parallel conversion circuit that converts the multiplexed data into parallel data, and the parallel data A latch circuit that periodically selects a predetermined L bit (an integer with L≧1) from among them, a parallel-to-serial conversion circuit that converts the latched L bit data into serial data, and a The double buffer memory circuit includes a double buffer memory circuit in which data is written, and a control circuit that controls reading from the double buffer memory circuit, and the double buffer memory circuit is alternately written and read at a predetermined period, and upon reading, A data branch circuit characterized in that the control circuit reads the serial data according to a predetermined read address and outputs and branches the predetermined data.