JPH01195429A - Optical time-division multiplexed modem circuit - Google Patents

Abstract

PURPOSE:To cope with a high-speed signal by using optical memory elements which can be controlled independently for writing and reading out and performing all signal processing with the optical memory elements. CONSTITUTION:The output of a counter 8 driven at a period T/4 is impressed up[on the readout controlling terminal of each optical memory element 7 and optical signals are read out. The optical signals are time-divisoin multiplex modulated after the are coupled by means of an optical star coupler 9 and time-division multiplex signals are outputted to an output port SO in an optical state. The output of the counter 8 is impressed upon and signals are written in the write controlling terminal W of each optical memory element 7. The counter 8 is constituted in such a way that outputs can respectively appear at the four output terminals of the counter 8 at the moments when 1-4 clocks are counted and each bit of the input signals are successively written in each optical memory element 7. Then time-division separated signals are outputted to an output port R# in an optical state. Therefore, the function of super-high speed time-division multiplex MODEM system of about 10GHz can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transmission device using an optical fiber as a medium, and particularly to a time division multiplexing modulation/demodulation circuit using an optical film in the transmission frame.

[Conventional technology]

FIG. 5 is an explanatory diagram of the functions of time division multiplexing and demultiplexing, in which (1) is modulation and (2) is demodulation. In the figure, SO is the input, S
l is the output, RO is the input, R1 is the output, and T is the period (seconds). (Hereinafter, rxJ and "-X" indicating each element will be omitted except when specifically specifying an individual element.) The following will all be explained using 4:1 time division multiplexing as an example. Figure 5 (1)
In this time division multiplex modulation circuit, when a time slot signal with an information rate of 1/IT (bits/second) is inputted, the input SO from the four input ports has a time width of 1 second as a result of time division multiplexing. Input SO signal into T/4
A time division multiplexed output S1 arranged in units of (seconds) on the time axis is obtained. Since FIG. 5(2) shows a time division multiplex demodulation circuit, the input/output relationship is reversed from FIG. 5(11).

FIG. 6 is a block diagram of a time division multiplex modulation circuit in a conventional electric circuit. In the figure, 1 is an AND gate, 2 is an O
R gate, 3 is a flip-flop, 4 is a gate, S# is an input, SO is an output, s[) is a data load, and SC is a clock pulse. The signal of each input signal S# is applied to the data input terminal of the flip-flop 3 via the AND gate 1 and the OR gate 2 by the data load pulse sD. After that, each flip-flop 3 takes in the signal S# by the clock pulse sC, and then the clock pulse S
C, each flip-flop 3 operates as a shift register via a gate 4, and time-division multiplex modulation signals are sequentially outputted to the output sO.

FIG. 7 is a block diagram of a time division multiplex demodulation circuit using a conventional electric circuit. In the figure, 5.6 is a flip-flop, rI is an input, r# is an output, rC is a clock pulse, r
R is a read pulse. The flip-flop 5 is driven by a clock pulse rC with a period of T/4 (seconds) and constitutes a shift register, and the time-division multiplexed signal from the input rl is developed in parallel in 4-bit units, and is output every period T (seconds). Then, data is latched in the flip-flop 6 by a read pulse rR, and an output r# is output.

[Problem to be solved by the invention]

As explained above, in the conventional configuration mainly based on electric circuits, flip-flops are often used in the signal path, so the information rate and frequency are up to about IGHz. As the speed of information increases, it becomes difficult to realize this in hardware. SUMMARY OF THE INVENTION An object of the present invention is to provide means that can realize the functions of a time division multiplex modulation/demodulation system that can handle high-speed signals.

[Means to solve the problem]

The present invention uses a first nonlinear element and an optical star coupler to perform time division multiplex modulation/demodulation signal processing on an optical film, thereby realizing the function of a time division multiplex modulation/demodulation system that can handle high-speed signals.

〔Example〕

FIG. 1 is a block diagram of an optical time division multiplexing modulation circuit of the present invention. In the figure, 7 is an optical memory element, 8 is a counter,
9 is an optical star coupler, S# is an optical signal, SO is an output port, C is a clock, and D is a data load pulse. Each input signal S# of the optical signal is input to the optical memory element 7 via an optical fiber in the optical state. A signal is written to each optical memory element 7 at the time when the data load pulse D is applied to the write control terminal W of each optical memory element 7. An optical memory element with an output of about 1 mW can be obtained, for example, by constructing a bistable semiconductor laser including a saturable absorber and adding layers for controlling the light absorption rate with a voltage before and after the bistable semiconductor laser. Next, the output of the counter 8 driven at a period of T/4 (seconds) is applied to the readout control terminal R of each optical memory element 7, and the optical signal is read out. By configuring the four output terminals of the counter 8 to output the clocks when 12, 3, and 4 clocks have been counted, the output of each optical memory element 7 is sequentially read out, and the output is sent to the optical star coupler 9. The time division multiplexed signal is subjected to time division multiplex modulation and is outputted to the output port SO in an optical state.

FIG. 2 is a block diagram of another optical time division multiplexing modulation circuit of the present invention. In the figure, 9' is an optical switch, and other symbols use the preceding ones. It has a configuration in which the optical coupler 9 in the configuration shown in FIG. 1 is replaced with an optical space division switch 9'.
The configuration is such that the optical memory element 7 connected to the output port SO is selected under the control of the counter 8. According to this configuration, the extinction ratio of light (the ratio of the light when the optical switch is at "1" and the leaked light when the optical switch is at "0") can be improved compared to the configuration using the optical star coupler 9.

FIG. 3 is a block diagram of an optical time division multiplexing demodulation circuit according to the present invention. In the figure, R# is the output, R1 is the input port, and R
is the read clock, and other symbols use their predecessors. The signal at the input port R2 is split into four optical signals by the optical star coupler 9 and input to the optical memory element 7 via the optical fiber. The output of the counter 8 driven at a cycle of T/4 (seconds) is applied to the write control terminal W of each optical memory element 7, and a signal is written therein. Each bit of the input signal is sequentially written into each optical memory element 7 by configuring the counter 8 to output an output at the time when 1, 2, 3, and 4 clocks have been counted, respectively, to the four output terminals of the counter 8. By simultaneously applying the read clock R to each optical memory element 7, a time-division separated signal is outputted to the output port R# in an optical state.

FIG. 4 is a block diagram of another optical time division multiplexing demodulation circuit according to the present invention. Use the preceding symbol.

The optical coupler 9 with the configuration shown in FIG. 3 is connected to the optical space division degree switch 9'
The configuration is such that the optical memory element 7 connected to the input port is selected under the control of the counter 8. As an example of such a space-division type optical switch.

Switching is possible with a loss of several dB using a LiNbO waveguide type. According to this configuration, the extinction ratio of light can be improved by the configuration using the optical star coupler 9.

In the embodiments of the present invention shown in FIGS. 1, 2, 3, and 4, the only electric circuit that requires high-speed operation is the counter 8, which is just a delay if the clock frequency is fixed. Since it can be constructed using lines, the overall operating speed is limited only by the speed of the optical memory element 7. In addition, by combining these two functions and changing the phase of the data load pulse D, it is possible to change the time slot, and it can also be applied to time division exchange.

〔Effect of the invention〕

As explained above, according to the present invention, all signal processing can be performed by optical elements using optical memory elements whose writing and reading can be controlled independently. On the other hand, because it is an optical element, it has achieved ultra-high-speed time division multiplexing modulation and demodulation functions of approximately 10 GHz.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an optical time division multiplexing modulation circuit of the present invention,
FIG. 2 is a block diagram of another optical time division multiplexing modulation circuit of the present invention, FIG. 3 is a block diagram of an optical time division multiplexing demodulation circuit of the present invention, and FIG. 4 is a block diagram of another optical time division multiplexing demodulation circuit of the present invention. A block diagram of the circuit, Fig. 5 is an explanatory diagram of the time division multiplexing and demultiplexing function, Fig. 6 is a block diagram of the circuit.
The figure is a block diagram of a time division multiplex modulation circuit using a conventional electric circuit, and FIG. 7 is a block diagram of a time division multiplex demodulation circuit using a conventional electric circuit. 1 is an AND gate, 2 is an OR gate, 3 is a flip-flop, 4 is a gate, 5.6 is a flip-flop, 7 is an optical memory element, 8 is a counter, 9 is an optical star coupler, 9゛ is an optical switch, SO is human power , Sl is the output, RO is the input,
R1 is the output, T is the period (seconds), S# is the optical signal, SO is the output port, C is the clock, D is the data load pulse, R
I is input port, R# is output, R is read clock,
S# is input, SO is output, rl is human power, r# is output, s
D is data load, sC is clock pulse, rC is clock pulse, rR is read pulse. Patent Applicant Nippon Telegraph and Telephone Corporation Agent Patent Attorney Tamamushi Kugobe (2 others) Time division ul[t11 circuit blocking factor in the present invention
3 Figure Other poem divisions of the present invention 1 (Bronx figure of 31st key U3 way Figure 4 #<B 0 Q) 1 + Morning Tsune T (1) 7I! L Modulation time division multiplexing - mth - (2) Demodulation function explanatory diagram 5

Claims (1)

[Claims] N optical memory elements whose write and read timings can be independently set using electrical signals are arranged in parallel, and each of the optical memory elements is connected to N branch ports of a 1:N optical star coupler or an optical switch, An optical time division multiplexing modulation/demodulation circuit characterized in that writing and reading timing signals are applied to the N optical memory elements at fixed time intervals in accordance with the order of their parallel arrangement.