SU801100A1 - Multistable clocked d-element - Google Patents

Description

one

The invention relates to automation and computing technology and is intended to implement the functions of v storing several states.

Known D-trigger, performed on the six binary elements And-HB, on the basis of which mezhet be built ksogostabilny 0-element 13.

A disadvantage of the known device is the use of a large number of binary AND-NOT binary elements.

There is a known D-flip-flop, filled in with AND-NOT elements (OR-NOT where one input of the first and second elements is connected to the clock signal bus, the second input of the first element to the data bus, and the second input of the second element to the output of the first element, the outputs of the first and second elements are connected respectively to the inputs of the third and fourth elements with cross-links, the outputs of which are the outputs of the 0-flip-flop 27.

A disadvantage of the known device is that the multistable O-element, made on its basis, also contains a large number of NAND (OR) elements. To increase the number of stable states of a known device, an additional number of binary AND-NOT elements (OR-NOT) is required to provide communication between the D-trigger groups, which leads to an increase in hardware costs, proportional to the number of stable o-element states, as well as incomplete use of the total number of binary NAND (NO) elements when constructing an O-element with an odd number of stable states.

The purpose of the invention is to increase the number of stable conditions and simplify the device.

five

The goal is achieved by the fact that in a multistable clocked D-element containing m groups, where, the first group of which contains i subgroups of AND-NOT elements, the first input of the first AND-NOT element of each i-th subgroup is connected to the information signal bus O and the second input of the first AND element of each i-th subgroup and each m-th group is connected to the clock signal bus T, the output of the first AND-NOT element in each subgroup and group is connected to the input of the second AND-NE element of the same subgroup and groups out

0 second elements AND-NOT of each subgroup and group are connected respectively to the outputs of the D-element and the inputs of the second elements AND-NOT of another subgroup and group, the output of each of the first element AND-NOT of all subgroups of the first group is connected to a separate corresponding input of the first element AND-NOT each m-th group and one of the inputs of every second element of the NAND of all subgroups and groups is connected to the corresponding bus of the setting signals. The drawing shows a multistable D-element electrical circuit. In the scheme, the first group 1 contains i subgroups of the AND-NOT elements, the t-group of 2 elements, the output of the first element 3 AND-NOT in each subgroup and group are connected to the input of the second element 4 AND-NOT of the same subgroup and group, the first input element 3 of each i-th subgroup is connected to the information signal bus D 5, and the second input of element 3 of each i-subgroup and each t-th group is connected to bus 6 of the clock signal T, the outputs of elements 4 of each subgroup and group are connected respectively to the outputs of the 7 D-element and the inputs of the elements 4 of another subgroup and group, o Each element 3 of all subgroups of the first group 1 is connected to a separate corresponding input of the first element 3 of each m-th group; one of the inputs of each element 4 of all subgroups and groups is connected to the corresponding bus 8 of the setting signals. The device works as follows. As follows from the state table, a two-group 0-element can be in one of four stable states AO (1,1,1), 1,1), A; (1,0,1) and A (1,1,0), which are formed at its outputs. The Ap state (1,1,1) can exist only when dialing 16 24 32 35 4S St Sr 55 bSG With a clock signal T-1 and an informational D-1, the level of a logical zero is formed at the output of element 3 of the first subgroup of the first group. The last, arriving at the inputs of element 4 of the first subgroup of the first group and element of the 3rd group, simultaneously blocks the O-element and translates it from :: A to (A, 0, 1, 1) with the installation sets ZZZZ .Z }, t 9-il 56 3r i9 4S S2 Si S5 °°, a, A, -. (1,0,1) when setting dix sets to state A (1,1,0) with setting sets, v (147 or AO (I, I, I) with setting sets and Z ,. With clock signal T -1 and the information element 3 of the first subgroup will remain closed, will open (the element of the 3rd m-th group in case of absence of the information signal flj, while the element 3 of the i-th subgroup of the first group will also remain closed and the level of logical zero generated at the output of element 3 of the t-group, the D-element will be switched to the state A (0,1,1) with the setting sets Z "Z ,, ZjJi from the state AJ (1,0,1) with us Tanning sets The D-element works similarly when the information signal flj is received; the element 3 of the first subgroup of the first group and the T-1 clock signal. At the output of this element a logical zero level is formed. Last received at the input of element 4 of the i-th subgroup the first group and the element of the 3rd group of the third group, at the same time blocking it, translates the D-element from the state A | , Z ,, ZjgZ42Z Z4 and the state of the joint-stock company (1,1,1) with the setting set Zfg or to the state A (0,1,1) when setting the set 2 .. or in Stay A, (1,1,0) when set in cue sets With a clock signal T-1 and informational flj-O element 3 of the i-th subgroup of the first group will remain closed, element 3 of the m-th group will open if there is no information signal D , while element 3 of the first subgroup of the first group will also remain closed, and the logic zero level, formed at the output of element 3 of the m-th group, will translate the D-element into the state of the AO (1,1,1) with the setting sets and Z or state A (0,1,1) when setting Zjy and Zjg, or livagadih sets Z to state A ((1,0,1Т when I set sets. When the clock signal T-G and information at the output of elements 3 of the first and i-and subgroups of the first group, the level of logical zero is formed. The latter, entering the inputs of the elements of the 4 corresponding subgroups and the first element of the 3th group, simultaneously blocks them and translates the O-element from state A (0,1,1) with the setting sets Z, ZZ, 2 3 24 9 and ZjjB the state A ((1,1,1) with the setting sets Z or to the state A (1,1,0} with the setting sets Z. езВ similar states 1,1,1) and A, „(1,1 , 0) the D-element is transferred from the state A, (1,0,1) with the same setup kits. A clockable D-element containing m groups, the first group of which contains i subgroups, gives a decrease in instrumental costs 2- i -m dvoT1ChNYH AND-NOT (NOR) in Cf.-nenii with the circuit comprising m D-TjM Gere. Due to the functionality expansion clocked

D-element, it can be used in equipment with multi-channel structure.

Table continuation

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Claims (2)

0/1 1 The invention formula Multistable clocked D-element, containing m groups, where, the first group of which contains i subgroups of AND-NOT elements, and the first input of the first AND-NE element every 1st subgroup is connected to the information bus signal D, and the second input of the first IS element of each i-th subgroup and each m-group is connected to the clock signal bus T, the output of the first IS-NOT element in each subgroup and group is connected to the input of the second AND-NOT element of this the same subgroups and groups, the outputs of the second AND elements of each subgroup and group n Connected, respectively, to the outputs of the D-element and the inputs of the second AND-NOT elements of another subgroup and group, differing from that. The continuation of the table is that, in order to increase the number of stable states and simplify the device, the output of each first element IS-NOT of all subgroups of the first group is connected to a separate corresponding input of the first element AND-NOT of each m-group and one of the inputs of each second element AND Not all subgroups and groups are connected to the corresponding bus of setting signals. Sources of information taken into account during the examination 1. B. Kagan. and Kanevsky M.I. Digital computers and cHCTeNtJ. M., Energie, 1973, p. 177-178, fig. 3-35. 2. Bukreev I.K., Mansurov B.M. and Gorchev V.I. Microelectronic circuits of digital devices. M., Sov.radio, 1973, p. 55-56.