JPH0813022B2 - Data branch circuit - Google Patents

Description

The present invention relates to a branch circuit for branching a multiplexed serial date, and more particularly to a branch circuit for randomly branching a predetermined bit of serial data. .

[Conventional technology]

Conventionally, when a branch circuit for branching multiplexed serial data branches a predetermined bit on the serial data, a timing signal for latching a predetermined bit on the serial data is generated and the timing signal is generated. Data is held based on the signal, and then the held data is branched.

[Problems to be Solved by the Invention] In the case of the branch circuit described above, the timing signal requires periodicity for the branched data, and as a result, the data (bit) on the serial data is periodically branched. Can only do that, data (bit) on serial data
Cannot be randomly branched. Therefore, the data multiplexing efficiency cannot be improved.

An object of the present invention is to provide a branch circuit that can randomly branch data on serial data.

[Means for solving problems]

According to the present invention, in a data branching circuit for branching predetermined data from multiplexed data in which a plurality of data are multiplexed and transmitted serially, a serial-parallel conversion circuit for converting the multiplexed data into parallel data, ,
A latch circuit that periodically selects a predetermined L (L is an integer of 1 or more) bits from the serial-parallel data, and a parallel-serial conversion circuit that converts the latched L-bit data to serial data. A double buffer memory circuit in which the serial data is written according to a sequential address, and a control circuit for controlling reading of the double buffer memory circuit, wherein the double buffer memory circuit alternately performs writing and reading at a predetermined cycle, At the time of the reading, the control circuit reads the serial data according to the sequential address at the time of the writing, and branches and outputs the predetermined data. Thus, a data branching circuit is obtained.

〔Example〕

 Next, the present invention will be described with reference to examples.

As shown in FIG. 2, “L” (L ≧ 1 integer) bits are set as one unit (1 time slot), and this time slot is collected in “M” (M ≧ 2 integer) time slots. A data frame is configured as one frame, and N (integer of N ≧ 2) frames are collected from this data frame to configure one multiframe.

Here, referring to FIG. 1, the serial data S1 multiplexed and serially transmitted is a serial / parallel conversion circuit (S / P).
It is converted into a parallel state by the circuit 11 every time slot and is given to the latch circuit 12. Latch circuit 12
Is a predetermined L for each frame from these parallel data.
Latch a bit (that is, a given time slot). That is, the latch cycle of the latch circuit 12 is generated once in one frame of the configuration shown in FIG. 3 when all N frames are collected, and as a result, the latch circuit 12 receives data shown in FIG. 3 for N frames. Will be output in parallel.

The latched parallel data is again converted into serial data by the parallel-serial conversion circuit (P / S circuit) 13. As a result, (L × N) bits of serial data for N frames are given to the buffer memory circuits 14 and 15 (the buffer memory circuits 14 and 15 are collectively referred to as a double buffer memory circuit).

When writing the serial data to the buffer memory circuits 14 and 15, the serial data are sequentially written to the buffer memory circuits 14 and 15 according to the sequential addresses. Then, the buffer memory circuits 14 and 15 are alternately written and read in correspondence with the multi-frame cycle.

On the other hand, the read control of the buffer memory circuits 14 and 15 is performed by the control circuit 16. The control circuit 16 is, for example, as shown in FIG. Specify the sequential address when writing the branch data bit indicated by. This allows the buffer memory circuit
Data of 14 and 15 are read alternately in a multi-frame cycle. In other words, the control circuit is controlled by the clock on the branch output side.
By changing the read address of 16, the data S2 is branched in bit units corresponding to an arbitrary speed (clock) from the multiplexed serial data.

〔The invention's effect〕

As described above, according to the present invention, the double bit buffer memory is provided, and by arbitrarily setting the read address of the control circuit, a random bit arrangement can be configured without being limited by the periodicity / continuity of the bits. As a result, there is an effect that the data multiplexing efficiency is increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data branch circuit according to the present invention, FIG. 2 is a diagram showing an example of a frame configuration, and FIG.
The figure is a diagram showing a configuration example of a bitmap. 11 …… Serial-parallel exchange circuit (S / P circuit), 12 ……
Latch circuit, 13 …… Parallel-serial exchange circuit (P / S circuit), 14 …… Buffer memory circuit, 15 …… Buffer memory circuit, 16 …… (Read) control circuit, S1 …… Multiplexed serial data input, S2 …… Output data.

Claims (1)

[Claims] 1. A data branching circuit for branching predetermined data from multiplexed data in which a plurality of data are multiplexed and serially transmitted, and a serial-parallel conversion circuit for converting the multiplexed data into parallel data, A latch circuit that periodically selects a predetermined L (L is an integer of 1 or more) bits from the serial-parallel data, and a parallel-serial conversion circuit that converts the latched L-bit data to serial data. A double buffer memory circuit in which the serial data is written according to a sequential address, and a control circuit for controlling reading of the double buffer memory circuit, wherein the double buffer memory circuit alternately performs writing and reading at a predetermined cycle, During the read operation, the control circuit sequentially operates during the write operation. Reading the serial data in accordance with the dress, the data branching circuit, characterized in that the predetermined data so as to branch output.