JPH10285132A - Information transfer method and multiplex circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form continuous data and to continuously and efficiently transfer two pieces of different bit width information by setting two pieces of information different in bit width to the bus of larger bit width and transferring them, and inserting/adding dummy information according to need in a specified section where information of large bit width exists so as to transfer them. SOLUTION: Two pieces of different bit width information, two pieces of bit width information of 12 bits width information and eight bits width information, for example, are sequentially transferred at one slot period through a 12 bits width bus. In information processing in an eight bits unit, information is arranged in the highest eight bits of the 12 bits width bus and the whole 12 bits width bus is used and information processed at 12 bits is transferred. When 12 bits width information continue, whole 12 bits are set in dummy bit information if necessary.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a transfer method for transferring two different bit width information and a multiplexing circuit for converting the transfer information into a serial signal.

[0002]

2. Description of the Related Art When two pieces of information having different bit widths are transmitted by one transmission frame, it is necessary to configure the frames so that it is easy to establish frame synchronization in a receiving unit. For example, in order to configure the 8-bit width information and the 12-bit width information in one frame, as shown in an explanatory diagram of FIG. 5, two pieces of information are transferred using a 12-bit width bus and a serial signal is transmitted. To Each slot (1) to (7) of the serial signal consists of 12 bits, and for slots (1) and (2) where 8-bit width information exists, dummy (empty) bits are placed in the first 4 bits. Is inserted to make 12 bits, and the 12-bit width information is converted into a serial signal as a 12-bit slot.

[0003] The receiving unit determines whether the information is 8-bit width information or 12-bit width information based on the presence or absence of the dummy bit information. However, the receiving unit specifies the dummy bit information so as not to match the pattern of the transmission data. And it is configured to make a determination by detecting this code.

[0004]

In the method of serializing two pieces of information having a 12-bit width and an 8-bit width in units of 12 bits as in the above-mentioned conventional technique, an increase or decrease in the amount of 8-bit information is prevented. The information amount of the dummy bit increases or decreases in proportion. If all the transmission frame periods are 8-bit information, 1/3 of the frame becomes dummy bit information and transmission efficiency is reduced. Further, in order to transmit all information within a specified time, it is necessary to set the transmission speed of serial signal conversion to 3/2 times at the maximum.

The present invention solves the above-mentioned problem of the prior art and provides a transfer method for continuously and efficiently transferring two different bit width information and a multiplexing circuit for converting the transfer information into a serial signal. The purpose is to provide.

[0006]

In order to achieve the above object, according to the transfer method of the present invention, a transfer bus is set to have a 12-bit width, and 8-bit width information is stored in upper 8 bits of the 12-bit width bus. In this method, 12-bit width information is allocated and transferred using the entire bus width. In a specific section in which 12-bit width information is present, dummy information is added as necessary and transferred.

In the multiplexing circuit of the present invention, the 12-bit width information transferred by the transfer method is delayed by one slot, and the 8-bit width information selects the upper 8 bits of the 12-bit width bus in real time, 12-bit width information is the top 8 in real time
Bits and the lower 4 bits of the delay information, or the upper 4 bits of the real time information and the lower 8 bits of the delay information, as required. In a specific section where 12-bit information is present, 12 bits are selected. When an even number of pieces of width information continue, (12 × n) / 8 (where n is an even number of 2, 4, 6,...) Slots are used as blocks. When an odd number of pieces of 12-bit information continue, dummy bits are used. Is added as 4 bits, and (12 × m + 4) / 8 (where m = 1, 3, 5,..., An odd number) slots are used as blocks to sequentially perform parallel / serial conversion.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention described in claim 1 of the present invention is as follows.
A method of transferring two different bit width information, wherein
The bus width is set for the bit width information having the larger capacity among the two bit width information, and the bit width information having the larger capacity is allocated to the entire bus width, and the bit width information having the smaller capacity is assigned to the bus width. The method is characterized in that bit width information is transferred at a fixed slot period by allocating to upper bits or lower bits of a bus width and inserting dummy bit information as needed, and by using this method, two different bits are transferred.
When the two pieces of bit width information are, for example, 12-bit width information and 8-bit width information, the configuration is such that the 12-bit width information and the 8-bit width information are sequentially transferred in one slot cycle via the 12-bit width bus. For information to be processed in units of 8 bits, information is arranged in the upper 8 bits of a 12-bit bus, and
Information processed by bits is transferred using the entire 12-bit width bus. Particularly, when 12-bit width information is continuous, the entire 12 bits are dummy-added as necessary.
Set to bit information.

Further, the invention according to claim 2 of the present invention provides:
X bit width information via the Y bit width bus (however,
A circuit for inputting X, Y (X <Y) is an integer) and Y bit width information at a slot cycle and serializing the data in units of X bits, wherein the two bit width information are transmitted via a Y bit width bus. Means for delaying the two pieces of bit width information by a slot cycle; means for selecting upper or lower X bits of a bus having a Y bit width as X bit width information in real time; As information, the upper X bits of a bus having a Y bit width and the lower (YX) bits of delay information, or the upper (YX) bits of Y bit width information and lower X bits of delay information are selected as necessary. Means, and means for sequentially converting the selected X-bit information into parallel / serial data. With this configuration, two different bit width information can be converted into, for example, 12-bit width information and 8-bit width information. Then, The information transferred via the 12-bit width bus transferred by the method of claim 1 is delayed by one slot, and for 8-bit width information, the upper 8 bits of the transferred bus information are sequentially converted into parallel / serial. For 12-bit width information, when an even number of 12-bit width information continues, (12 × n) / 8 (where n = 2,
When an odd number of 12-bit information continues, 4 dummy bits are added and (12 × m + 4) / 8 (where m = 1, 3, 5)
In order to transfer the (odd number) slot as a block, the parallel / serial conversion is sequentially performed by adding dummy information as necessary.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a format diagram showing a configuration of bus information for explaining an embodiment of an information transfer method according to the present invention. In this example, five consecutive bits including dummy information after 8-bit width information are shown. 12 shows the operation when the 12-bit width information (width unit indicated by # in FIG. 1) is repeated,
8-bit width information and 12-bit width information (1), (2), (4)
This shows a format for transfer using a 2-bit width bus.

The 8-bit information is arranged in the upper 8 bits of the 12-bit bus, and "0" is inserted as dummy information in the lower 4 bits. In the 12-bit width information (1), (2), and (4), “0” is placed as the dummy information in the third byte (3) and the fifth byte (5) in the entire 12 bits. It has an inserted configuration.

FIG. 2 shows a process of parallel / serial conversion of a data format obtained by the method described with reference to FIG. 1 in units of 8 bits.

In FIG. 2, information transferred via a 12-bit bus is delayed by one slot, and information to be processed with 8 bits is the upper 8 bits of the transferred bus information.
For information to select bits and to process with 12 bits, the upper 8 bits (1) of the transferred information are selected in the first slot period, and one byte before the delay information, which is delay information, is selected in the second slot period. Select the lower 4 bits (2) of the bus information and the upper 4 bits (2) of the transferred bus information, and
In the fourth slot period, the lower 8 bits (3) of the bus information one byte before, which is delay information, are selected. In the fourth slot period, the upper 8 bits (4) of the transferred bus information are selected. During the slot period, the lower 4 bits (5) of the information one byte before the delay information and the upper 4 bits (5) of the transferred bus information are selected, and the parallel / serial conversion is sequentially performed.

As described above, it is possible to continuously transfer the bit width information at a constant slot cycle, and it is possible to improve the transmission efficiency.

FIG. 3 is a block diagram showing a configuration for explaining an embodiment of the multiplexing circuit according to the present invention, and FIG. 4 is a timing chart for explaining the operation of the multiplexing circuit shown in FIG. In the figure, the multiplexing circuit
The 12-bit width information ((e) in FIG.
(D)), the shift register 1 is delayed (state (f) in FIG. 4), and the upper 8 bits of the transferred 12-bit width information ((e) in FIG. 4) are selected signals shown in (Table 1). SEL1 (FIG. 4)
(G) The first AND circuit 2 that selectively outputs during the period of the logic "1" and the lower 8 bits of the delay information ((f) in FIG. , A second AND circuit 3 for selectively outputting during the period of the logic "1" of the selection signal SEL2 ((h) in FIG. 4), the lower 4 bits of the transferred 12-bit bus information and the shift register 1 The upper 4 bits of the delay information ((f) in FIG. 4), which is the output of (3), are selectively output during the period of the logic "1" of the selection signal SEL3 ((l) in FIG. 4) shown in (Table 1). The logical product circuit 4 and the outputs of the logical product circuits 2 to 4 are connected in an 8-bit bus shape ((nu) in FIG. 4).
And the 8-bit bus information is converted into a serial signal ((l) in FIG. 4) by the logic of clocks ck1 to ck3 ((a) to (c) in FIG. 4). Serial conversion circuit 6
It is constituted by.

[0017]

[Table 1]

[0018]

As described above, according to the information transfer method of the present invention, two pieces of information having different bit widths are set and transferred to the bus having the larger bit width, and the dummy (empty)
By inserting bits, continuous data can be formed.

According to the multiplexing circuit of the present invention, for example, the transferred 12-bit width information is delayed by 1 byte, and the upper 8 bits of the 12-bit width bus are selected in real time as the 8-bit width information. As the bit width information, the upper 8 bits of the real time and the lower 4 bits of the delay information, or the upper 4 bits of the real time information and the lower 8 bits of the delay information are selected as necessary, so that a continuous 8-bit width is obtained. This makes it possible to transmit the data in almost real time, thereby improving the transmission efficiency of two pieces of information having different bit widths.

[Brief description of the drawings]

FIG. 1 is a format diagram showing a configuration of bus information for explaining an embodiment of an information transfer method according to the present invention.

FIG. 2 is an explanatory diagram showing a process of parallel / serial conversion of a data format obtained by the method described with reference to FIG. 1 in units of 8 bits.

FIG. 3 is a block diagram illustrating a configuration for describing an embodiment of a multiplexing circuit according to the present invention.

FIG. 4 is a timing chart for explaining the operation of the multiplex circuit of FIG. 3;

FIG. 5 is a data format diagram for explaining a conventional multiplexing method.

[Explanation of symbols]

1 shift register, 2, 3, 4 ... logical product circuit, 5
... OR circuit, 6 ... Parallel / serial conversion circuit.

Claims (2)

[Claims] 1. A method for transferring two different bit width information, wherein a bus width is set in a bit width information having a larger capacity among the two bit width information, and a bit having a larger capacity is set. The width information is allocated to the entire bus width, the bit width information having the smaller capacity is allocated to the upper bit or the lower bit of the bus width, and dummy bit information is inserted as necessary, so that the bit width information is fixed. An information transfer method, wherein transfer is performed according to a slot cycle. 2. X-bit width information (X, Y (X <Y) is an integer) and Y-bit width information are input at a slot cycle via a Y-bit width bus and serialized in X-bit units. Means for inputting the two pieces of bit width information via a bus having a Y bit width, means for delaying the two pieces of bit width information at a slot cycle, Means for selecting the upper or lower X bits of the bus in real time; the upper X bits of the bus having a Y bit width as the Y bit width information;
Means for selecting bits or upper (YX) bits of the Y bit width information and lower X bits of the delay information as necessary, and means for sequentially performing parallel / serial conversion on the selected X-bit unit information. A multiplex circuit, comprising: