JP2002321407A - Image processing apparatus and imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing apparatus capable of processing a large amount of image data at a high speed and an imaging apparatus comprising the image processing apparatus. SOLUTION: Image data transmission between a plurality of image processing apparatus is carried out via an LVDS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for processing digital image data and an image forming apparatus having the image processing apparatus, and more particularly to a technique for transmitting a signal such as image data in the image processing apparatus or the image forming apparatus. About.

[0002]

2. Description of the Related Art FIG. 1 shows a conventional image processing apparatus for transmitting image data between a plurality of image processing circuits.

FIG. 1A shows three image processing circuits GP.
1, GP2 and GP3 are connected by a bus line for image data, and operate by a reference clock CLK. That is, each of the image processing circuits GP1, GP2, GP3 is connected to the reference clock CL.
Image processing in each circuit is performed by an operation synchronized with K, and image data is transmitted. In this image processing apparatus, it is necessary to increase the frequency of the reference clock CLK in order to increase the processing speed.

In FIG. 1B, each image processing circuit GP1,
High-speed processing is performed by operating GP2 and GP3 with a clock obtained by multiplying the reference clock by n. FIG.
In the image processing apparatus shown in FIG. 2B, the width of the bus line is set to n in order to match the transfer rate with the processing speed of each image processing circuit.
Doubled.

[0005]

As the speed of devices and systems increases and the amount of data to be processed increases, the speed of image processing devices has become higher.

When the speed of the image processing apparatus shown in FIG. 1A is increased, the frequency of the reference clock CLK is increased, and the operation of the data bus is also increased. And other problems arise. FIG.
When the speed of the image processing apparatus of (b) is increased, the above-described problem can be avoided, but problems such as difficulty in keeping the number of bits and the line bundle of the data bus within limits are caused.

An object of the present invention is to provide an image processing apparatus and an image forming apparatus which can solve the above-mentioned problems in the conventional image processing and can easily increase the speed.

[0008]

The above-mentioned object of the present invention is achieved by the following inventions.

1. A first image processing circuit, and an output interface for converting the image data, the line synchronization signal, the horizontal image effective area signal, and the vertical image effective area signal, which have been image-processed by the first image processing circuit, into a low voltage difference signal;
And an input interface for converting the input low-voltage differential signal to generate image data, a line synchronization signal, a horizontal image effective area signal, and a vertical image effective area signal; A second image processing unit having a second image processing circuit for processing image data to be processed, and performing LVDS transmission of data from the first image processing unit to the second image processing unit. apparatus.

[0010] 2. The output interface has a parallel / serial conversion circuit.
An image processing apparatus according to claim 1.

3. The input interface includes a serial / parallel conversion circuit.
Or the image processing device according to the above 2.

4. 3. The image processing apparatus according to claim 2, wherein the first image processing circuit inputs a reference clock, and the image processing circuit and the parallel / serial conversion circuit operate with a clock obtained by multiplying the reference clock.

5. 4. The image processing apparatus according to claim 3, wherein the input interface receives a reference clock, and the serial / parallel conversion circuit and the second image processing circuit operate with a clock obtained by multiplying the reference clock.

6. 6. The image processing apparatus according to any one of claims 1 to 5, wherein the first image processing circuit includes a shading correction unit.

[0015] 7. The image processing apparatus according to any one of claims 1 to 6, wherein the first image processing circuit includes a luminance / density conversion unit.

8. The first image processing circuit includes an MTF correction unit.
An image processing apparatus according to the item.

9. 9. The image processing apparatus according to claim 1, wherein the first image processing circuit has a scaling unit.

10. The first image processing circuit includes a density correction unit.
An image processing apparatus according to the item.

11. The image processing apparatus according to any one of claims 1 to 10, wherein the second image processing circuit includes an error diffusion processing unit.

[12] 12. The image processing apparatus according to any one of items 1 to 11, wherein the second image processing circuit includes a compression / expansion processing unit.

13. The image processing apparatus according to any one of claims 1 to 12, further comprising a storage device that stores image data processed by the second image processing circuit.

14. The input reference clock is multiplied by m,
an image processing circuit that processes input image data based on the clock multiplied by m and outputs image data of m times the input bits, and an image processing circuit connected to an output bus of the image processing circuit; A parallel / parallel converter that converts the output image data, line synchronization signal, horizontal image effective area signal, and vertical image effective area signal into parallel / serial
An image processing apparatus comprising: a serial conversion circuit; and an output interface having an LVDS driver that converts a signal that has been subjected to parallel / serial conversion into a low-voltage differential signal.

[15] The parallel / serial conversion circuit operates by a clock multiplied by m = P / Q (P> Q) to perform parallel / serial conversion for converting P-bit parallel data into Q-bit serial data. 15. The image processing device according to the above 14.

16. An LVDS receiver for reversely converting an LVDS-transmitted low-voltage differential signal, and serial / parallel conversion to generate image data, a line synchronization signal, a horizontal image effective area signal, and a vertical image effective area signal synchronized with a reference clock. An input interface having a serial / parallel conversion circuit, and an image processing circuit connected to the input interface and performing image processing by operating with a clock obtained by multiplying the input reference clock by m.
An image processing apparatus comprising:

17. The serial / parallel conversion circuit operates by a clock obtained by multiplying the input clock by m = P / Q (P> Q) to perform serial / parallel conversion for converting Q-bit serial data into P-bit parallel data. 17. The image processing apparatus according to 16, wherein the image processing apparatus is characterized in that:

18. Image reading means for reading an image to generate digital image data, an image processing apparatus having a plurality of image processing circuits for processing image data generated by the image reading means, and image data processed by the image processing circuit. In an image forming apparatus having an image writing device for forming an image, the plurality of image processing circuits are connected via an LVDS interface, and at least image data is transmitted by LVDS.

19. 19. The image forming apparatus according to claim 18, wherein the image processing device and the image writing device are connected via an LVDS interface, and at least image data is transmitted by LVDS.

[0028]

FIG. 2 is a block diagram of an image processing apparatus according to an embodiment of the present invention.

The first image processing section has an image processing circuit 10 as a first image processing circuit and an output interface 30. The image processing circuit 10 is connected to a bus B1, and transmits image data and control signals such as a line synchronization signal, a horizontal image effective area signal, and a vertical image effective area signal to the bus B1.
1 and a reference clock CLK. The image processing circuit 10 performs image processing such as MTF correction and scaling. The image processing circuit 10 is driven by a clock mCLK having a frequency mf obtained by multiplying an input reference clock CLK having a frequency f by m to perform the image processing.

The output interface 30 comprises a parallel / serial conversion circuit and an LVDS driver, and the parallel / serial conversion circuit converts the output of the image processing circuit 10 into serial data. In this conversion, the image data is processed at high speed by a clock mCLK multiplied by m.
The output of the parallel / serial conversion circuit is converted into a low-voltage differential signal by an LVDS driver and transmitted by LVDS.

LVDS (Low Voltage, Di)
(referential Signaling) is TIA
/ EIA-644, which enables high-speed data transmission using small, voltage-changed differential signals.

The second image processing section has an image processing circuit 20 as a first image processing circuit and an input interface 40. The image processing circuit 20 receives the input reference clock CLK.
Is processed by a clock mCLK obtained by multiplying m by m.
The processing in the image processing circuit 20 is, for example, image data compression / expansion processing or error diffusion processing. As described above, the image processing circuit 10 and the image processing circuit 20 perform different image processing, and the processing contents are various in addition to the above. What kind of image processing each performs is determined by the content of the processing performed by the image processing apparatus as a whole.

The input interface 40 comprises an LVDS receiver and a serial / parallel conversion circuit.
TTL / CMOS for low voltage differential signal by S receiver
After reverse conversion into a signal, serial / parallel conversion is performed to generate parallel data. The serial / parallel conversion circuit operates based on a clock mCLK obtained by multiplying the input clock by m to perform serial / parallel conversion.

The image processing in the image processing circuits 10 and 20 is a high-speed processing performed by a clock mCLK having a frequency mf obtained by multiplying the reference clock CLK by m, and a large amount of data is transmitted by LVDS transmission between the first and second image processing units. High-speed data transmission.

Next, the image processing circuit 10 and the image processing circuit 2
Transmission of a signal between 0 and 0 will be described with reference to FIGS. FIG.
Denotes an image processing circuit 10 (in FIGS. 3 and 4, indicated by Tx)
3 and an input signal of the image processing circuit 20 (indicated by Rx in FIGS. 3 and 4), and FIG. 4 is a partially enlarged view of FIG. FIG. 3A shows an output signal of the image processing circuit 10,
FIG. 3B shows an input signal of the image processing circuit 20.

The image processing circuit 10 has a reference clock CL
K, vertical image effective area signal Vvalid, line synchronization signal Index, horizontal image effective area signal Hval
id and image data DATA are input. In FIG. 4, (A) CLK is a reference clock input to the image processing circuit 10, and (B) DATA (k, 0) / Index / Hva.
The lid / Vvalid is connected to the image processing circuit 10 from the bus B1.
2 shows image data, a line synchronization signal, a horizontal image effective area signal, and a vertical image effective area signal, respectively.

In the image processing circuit 10, image data is processed by the clock mCLK multiplied by m as described above. (C) CLK (TxOUT) is a clock output from the image processing circuit 10, and (d) DATA (TxOU)
T) indicates image data output from the image processing circuit 10. (E) shows a clock output from the image processing circuit 20, and (g) shows image data output from the image processing circuit 20.

(D) DATA (TxOUT) is image data output from the image processing circuit 10 as described above,
(1) and k (2) to k (6) indicate image data of one pixel. The image processing circuit 10 receives Q-bit image data from the bus B1 and outputs a clock mCLK multiplied by m = P / Q.
And performs image processing to output P-bit image data to the output interface 30. The output interface 30 operates with the clock mCLK multiplied by m = P / Q to perform parallel / serial conversion for converting P-bit parallel data into Q-bit serial data.
Here, P, Q and m are positive integers and P> Q. Thus, the output interface 30 has a parallel / serial conversion circuit for reducing the number of bits.

The output interface 30 is TTL / CM
LV that converts 0S into a low-voltage differential signal for LVDS transmission
A DS driver and an input interface 40
Has an LVDS receiver for inversely converting the input low-voltage differential signal into a TTL / CMOS signal, and the data is transmitted from the output interface 30 to the input interface 40 by the LV.
DS transmission is performed.

The input interface 40 has a serial / parallel conversion circuit that operates with the clock mCLK multiplied by m = P / Q, and receives the LVDS transmitted low-voltage differential signal. The input interface 40 converts the low voltage differential signal transmitted by LVDS as described above to TTL / C
The signal is inversely converted into a MOS signal, and then serial / parallel conversion is performed. The serial / parallel conversion circuit of the input interface 40 receives Q-bit serial data and outputs P-bit parallel data to the image processing circuit 20. The image processing circuit 20 operates with the clock mCLK multiplied by m to perform image processing on the input image data (c) CLK (RxIN).

FIG. 5 is a block diagram showing an image forming apparatus according to the embodiment of the present invention. 1 is an image reading means, which has a CCD and an A / D converter, reads an image,
Output digital image data.

The image processing circuit 10 includes the shading correction means 11, the luminance / density conversion means 12, the MTF correction means 13, the scaling means 14, and the density / tone correction means 15, and includes image data. These image processings are performed. The image processing circuit 10 has a multiplication circuit, multiplies the input reference clock CLK by m, and generates a reference clock C
Clock mC having a frequency mf which is m times the frequency f of LK
LK operates to perform the above-described image processing.

The image processing circuit 20 performs image processing such as error diffusion processing, compression / decompression, and memory control on input image data.

The image processing circuit 10 and the image processing circuit 20 are connected to the LVDS via the output interface 30 and the input interface 40, so that high-speed processing and transmission of a large amount of image data can be performed. .

Reference numeral 50 denotes an output interface similar to the output interface 30 and comprises a parallel / serial conversion circuit and an LVDS conversion driver. The output interface 50 includes image data, an index synchronization signal,
The horizontal image effective area signal and the vertical image effective area signal are converted into a low voltage difference signal and transmitted by LVDS. The input interface 60 is an input interface similar to the input interface 40, and receives an LVDS-transmitted low-voltage differential signal and performs serial / parallel conversion.

Reference numeral 70 denotes a writing control unit for driving and controlling a light emitting element such as a laser diode, based on image data input through an input interface 60 comprising a serial / parallel conversion circuit and an LVDS receiver. Perform control. The write controller 70 performs image processing such as pulse width modulation (PWM) and write control using the clock mCLK multiplied by m. The input interface 60 and the writing control unit 70 constitute an image writing device.

Reference numeral 80 denotes an image memory as a storage device for storing the image data compressed by the image processing circuit 20. The image processing circuit 20 controls the writing to the memory 80 and outputs the image data from the memory 80 during image writing. The image data read control and the image data decompression process are performed.

[0048]

According to the present invention, it is possible to process a large amount of image data at a high speed, and to increase the speed and color of a copier or a printer. Since advanced image processing becomes possible, higher image quality and multi-functionality of the image forming apparatus are promoted.

According to one of the fourteenth to seventeenth aspects, an image processing apparatus which is resistant to noise, can process a large amount of image data with low power consumption, and is realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a conventional image processing apparatus.

FIG. 2 is a block diagram illustrating a processing apparatus according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating input / output signals of an image processing circuit.

FIG. 4 is a partially enlarged view of FIG. 3;

FIG. 5 is a block diagram showing an image forming apparatus according to the embodiment of the present invention.

[Description of Signs] 10, 20 Image processing circuit 30, 50 Output interface 40, 60 Input interface 70 Write control unit CLK Reference clock DATA Image data

Claims (19)

[Claims] 1. A first image processing circuit, and converts image data, a line synchronizing signal, a horizontal image effective area signal and a vertical image effective area signal processed by the first image processing circuit into a low voltage difference signal. An input interface that converts the input low-voltage differential signal, and generates an image data, a line synchronization signal, a horizontal image effective area signal, and a vertical image effective area signal; A second image processing unit having a second image processing circuit for processing the image data output by the input interface; and LVDS transmission of the data from the first image processing unit to the second image processing unit. Characteristic image processing device. 2. The apparatus according to claim 1, wherein said output interface includes a parallel / serial conversion circuit.
An image processing apparatus according to claim 1. 3. The input interface according to claim 1, further comprising a serial / parallel conversion circuit.
Alternatively, the image processing apparatus according to claim 2. 4. The apparatus according to claim 2, wherein the first image processing circuit inputs a reference clock, and the image processing circuit and the parallel / serial conversion circuit operate with a clock obtained by multiplying the reference clock. Image processing device. 5. The apparatus according to claim 3, wherein the input interface inputs a reference clock, and the serial / parallel conversion circuit and the second image processing circuit operate with a clock obtained by multiplying the reference clock. Image processing device. 6. The image processing apparatus according to claim 1, wherein the first image processing circuit has a shading correction unit. 7. The image processing apparatus according to claim 1, wherein the first image processing circuit has a luminance / density conversion unit. 8. The apparatus according to claim 1, wherein said first image processing circuit has MTF correction means.
An image processing apparatus according to the item. 9. The image processing apparatus according to claim 1, wherein the first image processing circuit has a scaling unit. 10. The apparatus according to claim 1, wherein said first image processing circuit has a density correcting means.
An image processing apparatus according to the item. 11. The image processing apparatus according to claim 1, wherein the second image processing circuit includes an error diffusion processing unit. 12. The image processing apparatus according to claim 1, wherein the second image processing circuit has a compression / decompression processing unit. 13. The image processing apparatus according to claim 1, further comprising a storage device that stores the image data processed by the second image processing circuit. 14. An input reference clock is multiplied by m, and m
An image processing circuit that processes input image data based on the multiplied clock and outputs image data of m times the input bits; and an image processing circuit that is connected to an output bus of the image processing circuit and outputs the image data. Parallel / serial conversion circuit for parallel / serial conversion of image data, line synchronization signal, horizontal image effective area signal and vertical image effective area signal, and LVDS for converting the parallel / serial converted signal to a low voltage difference signal An image processing apparatus, comprising: an output interface having a driver. 15. The parallel / serial conversion circuit includes
15. The image processing according to claim 14, wherein the image processing is performed by a clock multiplied by = P / Q (P> Q) to perform parallel / serial conversion for converting P-bit parallel data to Q-bit serial data. apparatus. 16. An LVDS receiver for inversely converting an LVDS-transmitted low-voltage differential signal, image data, a line synchronization signal, a horizontal image effective area signal, and a vertical image synchronized with a reference clock after serial / parallel conversion. An input interface having a serial / parallel conversion circuit for generating an effective area signal; and an image processing circuit connected to the input interface and operated by a clock obtained by multiplying an input reference clock by m to perform image processing. Characteristic image processing device. 17. The serial / parallel conversion circuit operates by a clock obtained by multiplying an input clock by m = P / Q (P> Q) to convert Q-bit serial data into P-bit parallel data. 17. The image processing apparatus according to claim 16, wherein parallel conversion is performed. 18. An image reading means for reading an image to generate digital image data, an image processing apparatus having a plurality of image processing circuits for processing the image data generated by the image reading means, and an image processed by the image processing circuit. In an image forming apparatus having an image writing device that forms an image based on image data, the plurality of image processing circuits are connected via an LVDS interface, and at least transmission of the image data is performed by an LVD.
An image forming apparatus, wherein the processing is performed by S. 19. The image forming apparatus according to claim 18, wherein the image processing device and the image writing device are connected via an LVDS interface, and at least image data is transmitted by LVDS.