JP4430491B2 - Image transfer apparatus and image forming apparatus - Google Patents

Description

  The present invention relates to an image transfer apparatus for transferring an image from one apparatus to another apparatus, and a composite type image forming apparatus having a plurality of functions such as a copy function, a printer function, a facsimile function, and the like provided with the image transfer apparatus. .

  The transfer of image data may be performed by LVDS (Low Voltage Differential Signaling). In this case, for example, DS90CR285 (channel link transmitter) and DS90CR286A (channel link receiver) manufactured by National Semiconductor are used. In DS90CR285, the parallel data for 28 bits is converted from parallel to serial, transferred by four LVDS data streams, and the transmission clock is transferred by the fifth LVDS link. This reaches the other party via the transmission line, is input to the DS90CR286A, and is converted into 28-bit parallel data and a clock signal.

  Here, if you want to receive image data transfer from the other party at your own convenience, send a signal indicating the line reference by LVDS, the other party receives this reference signal, and sends it back to the reference However, image data cannot be received at a desired timing with high accuracy due to the occurrence of a delay time in the transmission line.

  In addition, variation between devices exists as a cause of variation in delay time. For example, if you want to transfer more parallel data than the amount that can be transferred by a single device, the data will be divided and transferred to multiple devices. Specifically, even if the same signal is used on the transmitting side, the frequency is the same on the receiving side, but it must be handled as a signal whose phase cannot be guaranteed.

  As a technology related to this, the communication systems disclosed in Patent Documents 1 and 2 are known. The invention disclosed in Patent Document 1 receives a serial signal from a serialized transmission circuit that generates and transmits a serial signal from a clock and a parallel signal synchronized with the clock, and the parallelized reception circuit receives the clock and the parallel signal. The serialized transmission circuit includes a multiplier that multiplies the frequency of the input clock, and the parallelized reception circuit includes a frequency divider that divides the output clock. The same interface circuit (communication system) can be used in different color digital copying machines. That is, Patent Document 1 discloses a technique for enabling normal reception by correcting a delay amount in an apparatus that converts a parallel signal into a plurality of serial signals and transmits the signal regardless of variations in delay characteristics of the transmission line. Is described.

In the invention disclosed in Patent Document 2, the image reading unit transmits each LVDS transmission line including the same LSYNC signal, and the image processing unit causes a signal delay time generated in each transmission line. RGB image data to be written into the FIFO memory by creating write timing signals for controlling the write timing to the plurality of FIFO memories for writing the image data respectively based on the calculated signal delay times. This is to ensure that the phases can be matched. In the present invention, in an image data transfer system that transfers one image data divided into a plurality of LVDS devices, the same image data synchronization signal is included in each LVDS transmission path.
JP 2003-318741 A JP 2002-169770 A

  In the invention described in Patent Document 1, a delay element having variable delay time, a pattern generation means, and a pattern error determination means are provided in the serial signal path so that the delay amount of the delay element is adjusted, or a plurality of signals received by the receiving unit are received. The optimal clock is selected from the transmission clocks using the error rate measuring means, but the circuit is complicated because it is adjusted in an analog manner.

  In the invention described in Patent Document 2, in the image data transfer system that transfers one image data divided into a plurality of LVDS devices, the same image data synchronization signal is included in each LVDS transmission path. . For this reason, on the receiving side, a signal delay time difference occurring in the transmission line can be calculated, and variations in delay time can be corrected. However, in the invention described in Patent Document 2, an example of data transfer from an image reading unit (scanner) is described, and no consideration is given to starting image transfer in response to a request from the other side. .

  The present invention has been made in view of the actual situation of the prior art, and an object of the present invention is not to perform analog adjustment but to suppress the complexity of the circuit by synchronizing by digital processing, and to provide a plurality of asynchronous clocks. Is to reproduce the data transferred in the original synchronized signal.

In order to achieve the above object, the first means is an image transfer apparatus for transferring an image by LVDS between the A side device and the B side device , and the A side device is directed from the A side device to the B side device. Means for transmitting a line reference signal and other control signals, and the B side device receives a line reference signal and other control signals from the A side device, a line reference signal and other means for sending back a control signal, and after a predetermined timing from the signal indicating the reference line, the images transfer device provided with means for outputting the image data, a-side device includes a plurality of LVDS receivers for serial / parallel conversion , At least one LVDS transmitter that performs parallel / serial conversion, and the B side device corresponds to a plurality of LVDS receivers of the A side device, respectively Together provided Te, comprising: a plurality of LVDS transmitter performs parallel / serial conversion, with provided corresponding to at least one LVDS transmitter A side device, and at least one LVDS receiver performs serial / parallel conversion, a, At least one signal indicating the line reference to be transmitted by parallel / serial conversion from a plurality of LVDS transmitters on the B side device is input for each device to be serial / parallel converted by a plurality of LVDS receivers on the A side device. It is characterized by.

With the above configuration, at least one signal indicating the reference of the line to be transmitted after parallel / serial conversion from a plurality of LVDS transmitters on the B side device is inserted for each device that performs serial / parallel conversion on the plurality of LVDS receivers on the A side device since that, the delay time difference between the clock for each device is generated for each LVDS receiver, be treated as non-synchronization, the signal indicating a reference line for each of the LVDS receiver device exists, based on the signal it can be performed accurately in the image data transferred.

Second means, in the first means, in the A-side device, each clock to be output to each device of said plurality of LVDS receivers, indicating a reference of said line from said plurality of LVDS transmitter of the B-side equipment signal, wherein the other control signal, and captures the image data, a signal indicating the reference line of the device of the plurality of LVDS receivers instead placed on a common clock, the common the other control signals, and the image data It is characterized by processing as a clock. As a result, there is a signal indicating the line reference in the same manner as in the first means described above. Based on this signal, data transferred with a plurality of asynchronous clocks is reproduced as the original synchronized signal. Can do.

Third means, in the second means, in the loaded instead of the common clock of the A-side device, if the clock of the common clock is outputted to each of the plurality of LVDS receivers devices of low speed, the signal indicative of the reference line from the device of a plurality of LVDS receivers, and wherein the other control signals, and be substituted put drop the frequency component of the image data. Thus, even if the clock a common clock outputs for each device of the LVDS receiver slow, as in the second means, reproduction data transferred multiple asynchronous clocks as the source of the synchronization signal can do.

The fourth means is characterized in that the image forming apparatus includes the image transfer apparatus according to the first to third means.

  In an embodiment to be described later, the A side device transmits to 101, the B side device transmits to 106, the line reference signal is transmitted to the line synchronization signal (LSYNC), and the other control signals are transmitted to the image synchronization signal (PSYNC). LVDS transmitter 104, receiving means correspond to LVDS receiver 109, sending back means LVDS transmitters 107 and 108, and LVDS devices correspond to first and second LVDS receivers 102 and 103, respectively.

  According to the present invention, analog adjustment is not performed, and the complexity of the circuit is suppressed by synchronizing by digital processing, and data transferred by a plurality of asynchronous clocks can be reproduced to the original synchronized signal. .

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an image transfer apparatus according to an embodiment of the invention. In FIG. 1, the code | symbol 101 is an A side apparatus. This becomes the main, issues a request to the B-side device 106, and performs image transfer.

  The internal configuration of the A-side device 101 includes first and second LVDS receivers 102 and 103, an LVDS transmitter 104, and an A-side control unit 105. The first and second LDVS receivers (DS90CR286A) 102 and 103 perform serial / parallel conversion to convert 28 parallel signals per device. The LVDS transmitter (DS90CR215) 104 performs parallel / serial conversion, and transmits 21 parallel signals per device after parallel / serial conversion. The A side control unit 105 controls the entire A side device.

  The B side device 106 transfers an image in response to a request from the A side device 101. The internal configuration of the B-side device 106 includes first and second LVDS transmitters 107 and 108, an LVDS receiver 109, and a B-side control unit 110.

The LDVS transmitter (DS90CR285) performs parallel / serial conversion, and converts and transmits 28 parallel signals per device. Further, the LVDS receiver (DS90CR216A) performs serial / parallel conversion to convert 21 parallel signals per device. The B side control unit 110 controls the entire B side device.

  The A-side device 101 and the B-side device 106 are connected via a transmission path, thereby enabling mutual image transfer.

In FIG. 1, the transmitter 104 includes
1) LSYNC_R_N (R (red) color line synchronization signal), PSYNC_R_N (R color image synchronization signal)
2) LSYNC_G_N (G (green) color line synchronization signal), PSYNC_G_N (G color image synchronization signal)
3) LSYNC_B_N (B (blue) line synchronization signal), PSYNC_B_N (B color image synchronization signal)
4) LSYNC_K_N (K (black) color line synchronization signal), PSYNC_K_N (K color image synchronization signal)
5) Transmission clock CLK_T
Is entered.

  The LVDS transmitter 104 performs parallel / serial conversion on the input signal and transmits it to the LVDS receiver 109. The LVDS receiver 109 performs serial / parallel conversion to reproduce the original signal. Also, the reception clock is regenerated.

Thus, the reproduced signal 1) LSYNC_R_N_b, PSYNC_R_N_b
2) LSYNC_G_N_b, PSYNC_G_N_b
3) LSYNC_B_N_b, PSYNC_B_N_b
4) LSYNC_K_N_b, PSYNC_K_N_b
5) Reception CLK_R
Is input to the B-side control unit 110.

  The reception clock CLK_R is supplied to the first and second LVDS transmitters 107 and 108, and the second transmitter 108 is supplied with LSYNC_R_N_b, PSYNC_R_N_b, LSYNC_G_N_b, and PSYNC_G_N_b. Also, image data I_D_R_N [7: 0] _b and I_D_G_N [7: 0] _b from the B-side control unit 110 are supplied.

  The first transmitter 107 is supplied with LSYNC_B_N_b, PSYNC_B_N_b, LSYNC_K_N_b, and PSYNC_K_N_b. Further, image data I_D_B_N [7: 0] _b and I_D_K_N [7: 0] _b from the B-side control unit 110 are supplied. That is, with this configuration, 108 LVDS devices (second transmitter 108) function for R and G colors, and 107 LVDS devices (first transmitter 107) function for B and K colors. The devices are divided because only 28 parallel signals can be supported per device.

  These signals are input to the second and first LVDS receivers 103 and 102 of the A-side device 101, and the second and first LVDS receivers 103 and 102 perform serial / parallel conversion to convert the original signal. Reproduce. Also, the reception clock is regenerated.

This
1) I_ILSYNC_R_N, I_PLSYNC_R_N
2) I_ILSYNC_G_N, I_PLSYNC_G_N
3) I_D_R_N [7: 0]
4) I_D_G_N [7: 0]
5) CLK_RG
Is reproduced from the second receiver 103.

Also,
1) I_ILSYNC_B_N, I_PLSYNC_B_N
2) I_ILSYNC_K_N, I_PLSYNC_K_N
3) I_D_B_N [7: 0]
4) I_D_K_N [7: 0]
5) CLK_BK
Is reproduced from the first receiver 102.

  It should be noted that CLK_RG and CLK_BK are originally the same signal, but a phase difference is generated. These signals and clock are input to the A-side control unit 105.

  Thereby, when it is desired to acquire image data from the B-side device 106, the A-side device 101 can acquire an image by controlling each color for each line. However, since the image is transferred by dividing it into two LVDS transmitters, in this example, it is received as a signal synchronized with two types of clocks of RG and BK.

  FIG. 2 shows a timing chart.

In FIG. 2A, CLK_T is a transmission clock on the A side, and in synchronization with this,
1) LSYNC_R_N
2) PSYNC_R_N
3) LSYNC_B_N
4) PSYNC_B_N
Is output.

  These signals are low-active signals and are effective when they are at a low level. Here, PSYNC_x_N indicates an x-color image synchronization signal, and when this is Low, an x-color image transfer is requested. LSYNC_x_N indicates an x-color line synchronization signal. When this signal is Low for one clock, an image transfer for one line of x color is requested. Therefore, the start part of the R and B color image transfer requests is shown here. Since the G color and the K color are the same, description thereof is omitted here.

In FIG. 2B, CLK_RG is a regenerated reception clock for the R and G colors received by the A-side device.
1) I_LYNC_R_N
2) I_PSYNC_R_N
3) I_D_R_N [7: 0]
Is played.

  In these, upon the assertion of the above-mentioned PSYNC_R_N and LSYNC_R_N, the B side returns this and sends out image data in accordance with this.

Similarly, in FIG. 2 (c), CLK_BK is a reproduced reception clock for B and K colors received by the A-side device.
1) I_LYNC_B_N
2) I_PSYNC_B_N
3) I_D_B_N [7: 0]
Is played.

  Note that the clocks CLK_RG and CLK_BK need not be in phase.

  In this way, when it is desired to acquire image data from the B-side device 106, the A-side device 101 can acquire an image by controlling line by color for each color.

  Next, using the timing chart shown in FIG. Here, the case where the output clock of the LVDS receiver device (B side device 106) is earlier than the common clock (com_clk) is shown.

  In FIG. 3, CLK_BK is the LVDS receiver device output clock for B color and K color, I_D_B_N is the output data from the LVDS receiver device, I_D_B_N_1d is the data obtained by delaying I_D_B_N by 1CLK_BK, and Trg is in every 2CLK_BK state. The signal to be inverted, DD, is obtained by sampling I_D_B_N and I_D_B_N_1d at the same timing as the state change of trg. Trg_d1 and DD_d1 are obtained by sampling Trg and DD with a common clock (com_clk). b_val is a signal that becomes High when trg_d1 is different from the previous trg_d1 at the rising edge of com_clk, and b_data is a signal obtained by sampling the state of DD_d1 only at the clock edge at which b_val outputs High.

  The above description is only for data (I_D_B_N), but the same is true for I_LSYNC_B_N and I_PSYNC_B_N.

  Thereby, b_pssync [1: 0] and b_lsync [1: 0] can be generated.

  As described above, B-color data, PSYNC_N, and LSYNC_N synchronized with com_clk can be acquired. By performing the same processing for other colors, data synchronized with com_clk, PSYNC_N, and LSYNC_N can be acquired.

  Here, although PSYNC_N and LSYNC_N are 2-bit signals, when the bit 0 side of LSYNC_N [1: 0] is 0, b_data [15: 8], b_pssync_ [1], b_lsync [ If the control is performed so that the next bit is used without using [1], only valid data can be used.

  The image transfer apparatus according to the present embodiment is applied not only to a communication system including an information processing apparatus but also to a composite image forming apparatus having a plurality of functions such as a copy function, a printer function, and a facsimile function, a so-called MFP. You can also.

As described above, according to the present embodiment, a signal indicating a line reference and other control signals are transmitted from the A side to the B side, and the B side receives the above signal from the A side, A signal indicating the reference and other control signals are sent back, and the image data is output after a predetermined timing from the signal indicating the line reference, and parallel / serial conversion is performed from each LVDS transmitter of the B side device. Since at least one signal indicating the reference of the line to be transmitted is input for each device that performs serial / parallel conversion in each LVDS receiver of the A side device , a clock delay time difference occurs for each device of each LVDS receiver. , be treated as an asynchronous, the signal indicating a reference line for each of the LVDS receiver device is present, the positive and the signal based on You can transfer image data to the probability.

Also, in the A-side, each clock output for each device of the LVDS receiver, a signal indicating a reference line, the other control signals of its, and captures the image data, for each L VDS receiver instead placed on a common clock signal indicating the reference line from the device, other control signals, and since the image data is configured to perform processing as a common clock, the delay time difference between the clock in each device of the LVDS receiver occurs, asynchronous It is treated as, the signal indicating the reference of a line for each of the LVDS receiver device is present, to reproduce the data to be transferred in a plurality of asynchronous clocks to the signal based on the original synchronization signal be able to.

Further, in carrying instead of the common clock, when a common clock is slower than the output clock for each device of the LVDS receiver, a signal indicating a reference line of the device of the LVDS receiver, other control signals, and an image since the manner replaced placed drop the frequency components of the data, the common clock is even slower if the clock to be output for each device of the LVDS receiver, similarly to the above case, it is transferred in multiple asynchronous clocks Data can be reproduced as the original synchronized signal.

It is a block diagram which shows the structure of the image transfer apparatus which concerns on embodiment of invention. It is a timing chart which shows the timing of the data transfer between A side apparatus and B side apparatus. It is a timing chart which shows the timing at the time of changing data on a common clock and performing data transfer.

Explanation of symbols

101 A side device 102, 103, 109 LVDS receiver 104, 107, 108 LVDS transmitter 105 A side device control unit 106 B side device 110 B side device control unit

Claims (4)

An image transfer apparatus for transferring an image by LVDS between an A-side device and a B-side device, wherein the A-side device indicates a line reference from the A-side device to the B-side device and other control signals. The B side device receives a signal indicating the reference of the line and other control signals from the A side device, means for sending back the signal indicating the reference of the line and other control signals, and after a predetermined timing from a signal indicating a reference of said line, in images transfer apparatus comprising means for outputting the image data,
The A-side device includes a plurality of LVDS receivers that perform serial / parallel conversion, and at least one LVDS transmitter that performs parallel / serial conversion.
The B side device is provided corresponding to each of the plurality of LVDS receivers of the A side device, and corresponds to a plurality of LVDS transmitters that perform parallel / serial conversion, and the at least one LVDS transmitter of the A side device. And at least one LVDS receiver that performs serial / parallel conversion ,
A signal indicating the reference of the line to be transmitted by performing the parallel / serial conversion from the plurality of LVDS transmitters of the B side device is at least for each device to be serial / parallel converted by the plurality of LVDS receivers of the A side device. An image transfer apparatus for inputting one image. In the A-side device, each clock to be output to each device of said plurality of LVDS receivers, a signal indicating a reference of said line from said plurality of LVDS transmitter of the B-side device, the other control signals, and the image data 6. A signal indicating the reference of the line from the devices of the plurality of LVDS receivers , the other control signal, and the image data are processed as the common clock instead of being captured and replaced with a common clock. The image transfer apparatus according to 1. In the common clock placed instead in the A-side device, if the clock of the common clock is outputted to each of the plurality of LVDS receivers devices of slow, reference of the line from the device of the plurality of LVDS receivers signal indicating the other control signals, and an image transfer apparatus according to claim 2, wherein the substituted put drop the frequency component of the image data. An image forming apparatus comprising the image transfer apparatus according to claim 1.

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